1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 * 9 * based on 10 * 11 * samsung/clk.h 12 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 13 * Copyright (c) 2013 Linaro Ltd. 14 * Author: Thomas Abraham <thomas.ab@samsung.com> 15 */ 16 17 #ifndef CLK_ROCKCHIP_CLK_H 18 #define CLK_ROCKCHIP_CLK_H 19 20 #include <linux/io.h> 21 #include <linux/clk-provider.h> 22 23 struct clk; 24 25 #define HIWORD_UPDATE(val, mask, shift) \ 26 ((val) << (shift) | (mask) << ((shift) + 16)) 27 28 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 29 #define BOOST_PLL_H_CON(x) ((x) * 0x4) 30 #define BOOST_CLK_CON 0x0008 31 #define BOOST_BOOST_CON 0x000c 32 #define BOOST_SWITCH_CNT 0x0010 33 #define BOOST_HIGH_PERF_CNT0 0x0014 34 #define BOOST_HIGH_PERF_CNT1 0x0018 35 #define BOOST_STATIS_THRESHOLD 0x001c 36 #define BOOST_SHORT_SWITCH_CNT 0x0020 37 #define BOOST_SWITCH_THRESHOLD 0x0024 38 #define BOOST_FSM_STATUS 0x0028 39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) 40 #define BOOST_RECOVERY_MASK 0x1 41 #define BOOST_RECOVERY_SHIFT 1 42 #define BOOST_SW_CTRL_MASK 0x1 43 #define BOOST_SW_CTRL_SHIFT 2 44 #define BOOST_LOW_FREQ_EN_MASK 0x1 45 #define BOOST_LOW_FREQ_EN_SHIFT 3 46 #define BOOST_BUSY_STATE BIT(8) 47 48 #define PX30_PLL_CON(x) ((x) * 0x4) 49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 51 #define PX30_GLB_SRST_FST 0xb8 52 #define PX30_GLB_SRST_SND 0xbc 53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 54 #define PX30_MODE_CON 0xa0 55 #define PX30_MISC_CON 0xa4 56 #define PX30_SDMMC_CON0 0x380 57 #define PX30_SDMMC_CON1 0x384 58 #define PX30_SDIO_CON0 0x388 59 #define PX30_SDIO_CON1 0x38c 60 #define PX30_EMMC_CON0 0x390 61 #define PX30_EMMC_CON1 0x394 62 63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4) 64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40) 65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80) 66 #define PX30_PMU_MODE 0x0020 67 68 #define RV1108_PLL_CON(x) ((x) * 0x4) 69 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 70 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 71 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 72 #define RV1108_GLB_SRST_FST 0x1c0 73 #define RV1108_GLB_SRST_SND 0x1c4 74 #define RV1108_MISC_CON 0x1cc 75 #define RV1108_SDMMC_CON0 0x1d8 76 #define RV1108_SDMMC_CON1 0x1dc 77 #define RV1108_SDIO_CON0 0x1e0 78 #define RV1108_SDIO_CON1 0x1e4 79 #define RV1108_EMMC_CON0 0x1e8 80 #define RV1108_EMMC_CON1 0x1ec 81 82 #define RV1126_PMU_MODE 0x0 83 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 84 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 85 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 86 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 87 #define RV1126_PLL_CON(x) ((x) * 0x4) 88 #define RV1126_MODE_CON 0x90 89 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 90 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280) 91 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 92 #define RV1126_GLB_SRST_FST 0x408 93 #define RV1126_GLB_SRST_SND 0x40c 94 #define RV1126_SDMMC_CON0 0x440 95 #define RV1126_SDMMC_CON1 0x444 96 #define RV1126_SDIO_CON0 0x448 97 #define RV1126_SDIO_CON1 0x44c 98 #define RV1126_EMMC_CON0 0x450 99 #define RV1126_EMMC_CON1 0x454 100 101 #define RK2928_PLL_CON(x) ((x) * 0x4) 102 #define RK2928_MODE_CON 0x40 103 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 104 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) 105 #define RK2928_GLB_SRST_FST 0x100 106 #define RK2928_GLB_SRST_SND 0x104 107 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 108 #define RK2928_MISC_CON 0x134 109 110 #define RK3036_SDMMC_CON0 0x144 111 #define RK3036_SDMMC_CON1 0x148 112 #define RK3036_SDIO_CON0 0x14c 113 #define RK3036_SDIO_CON1 0x150 114 #define RK3036_EMMC_CON0 0x154 115 #define RK3036_EMMC_CON1 0x158 116 117 #define RK3228_GLB_SRST_FST 0x1f0 118 #define RK3228_GLB_SRST_SND 0x1f4 119 #define RK3228_SDMMC_CON0 0x1c0 120 #define RK3228_SDMMC_CON1 0x1c4 121 #define RK3228_SDIO_CON0 0x1c8 122 #define RK3228_SDIO_CON1 0x1cc 123 #define RK3228_EMMC_CON0 0x1d8 124 #define RK3228_EMMC_CON1 0x1dc 125 126 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 127 #define RK3288_MODE_CON 0x50 128 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 129 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) 130 #define RK3288_GLB_SRST_FST 0x1b0 131 #define RK3288_GLB_SRST_SND 0x1b4 132 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) 133 #define RK3288_MISC_CON 0x1e8 134 #define RK3288_SDMMC_CON0 0x200 135 #define RK3288_SDMMC_CON1 0x204 136 #define RK3288_SDIO0_CON0 0x208 137 #define RK3288_SDIO0_CON1 0x20c 138 #define RK3288_SDIO1_CON0 0x210 139 #define RK3288_SDIO1_CON1 0x214 140 #define RK3288_EMMC_CON0 0x218 141 #define RK3288_EMMC_CON1 0x21c 142 143 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x) 144 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 145 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 146 #define RK3308_GLB_SRST_FST 0xb8 147 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 148 #define RK3308_MODE_CON 0xa0 149 #define RK3308_SDMMC_CON0 0x480 150 #define RK3308_SDMMC_CON1 0x484 151 #define RK3308_SDIO_CON0 0x488 152 #define RK3308_SDIO_CON1 0x48c 153 #define RK3308_EMMC_CON0 0x490 154 #define RK3308_EMMC_CON1 0x494 155 156 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x) 157 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 158 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 159 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) 160 #define RK3328_GLB_SRST_FST 0x9c 161 #define RK3328_GLB_SRST_SND 0x98 162 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 163 #define RK3328_MODE_CON 0x80 164 #define RK3328_MISC_CON 0x84 165 #define RK3328_SDMMC_CON0 0x380 166 #define RK3328_SDMMC_CON1 0x384 167 #define RK3328_SDIO_CON0 0x388 168 #define RK3328_SDIO_CON1 0x38c 169 #define RK3328_EMMC_CON0 0x390 170 #define RK3328_EMMC_CON1 0x394 171 #define RK3328_SDMMC_EXT_CON0 0x398 172 #define RK3328_SDMMC_EXT_CON1 0x39C 173 174 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) 175 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 176 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 177 #define RK3368_GLB_SRST_FST 0x280 178 #define RK3368_GLB_SRST_SND 0x284 179 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 180 #define RK3368_MISC_CON 0x380 181 #define RK3368_SDMMC_CON0 0x400 182 #define RK3368_SDMMC_CON1 0x404 183 #define RK3368_SDIO0_CON0 0x408 184 #define RK3368_SDIO0_CON1 0x40c 185 #define RK3368_SDIO1_CON0 0x410 186 #define RK3368_SDIO1_CON1 0x414 187 #define RK3368_EMMC_CON0 0x418 188 #define RK3368_EMMC_CON1 0x41c 189 190 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x) 191 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 192 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 193 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 194 #define RK3399_GLB_SRST_FST 0x500 195 #define RK3399_GLB_SRST_SND 0x504 196 #define RK3399_GLB_CNT_TH 0x508 197 #define RK3399_MISC_CON 0x50c 198 #define RK3399_RST_CON 0x510 199 #define RK3399_RST_ST 0x514 200 #define RK3399_SDMMC_CON0 0x580 201 #define RK3399_SDMMC_CON1 0x584 202 #define RK3399_SDIO_CON0 0x588 203 #define RK3399_SDIO_CON1 0x58c 204 205 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) 206 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) 207 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) 208 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 209 210 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) 211 #define RK3568_MODE_CON0 0xc0 212 #define RK3568_MISC_CON0 0xc4 213 #define RK3568_MISC_CON1 0xc8 214 #define RK3568_MISC_CON2 0xcc 215 #define RK3568_GLB_CNT_TH 0xd0 216 #define RK3568_GLB_SRST_FST 0xd4 217 #define RK3568_GLB_SRST_SND 0xd8 218 #define RK3568_GLB_RST_CON 0xdc 219 #define RK3568_GLB_RST_ST 0xe0 220 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 221 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 222 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 223 #define RK3568_SDMMC0_CON0 0x580 224 #define RK3568_SDMMC0_CON1 0x584 225 #define RK3568_SDMMC1_CON0 0x588 226 #define RK3568_SDMMC1_CON1 0x58c 227 #define RK3568_SDMMC2_CON0 0x590 228 #define RK3568_SDMMC2_CON1 0x594 229 #define RK3568_EMMC_CON0 0x598 230 #define RK3568_EMMC_CON1 0x59c 231 232 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x) 233 #define RK3568_PMU_MODE_CON0 0x80 234 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 235 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 236 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 237 238 #define RK3588_PHP_CRU_BASE 0x8000 239 #define RK3588_PMU_CRU_BASE 0x30000 240 #define RK3588_BIGCORE0_CRU_BASE 0x50000 241 #define RK3588_BIGCORE1_CRU_BASE 0x52000 242 #define RK3588_DSU_CRU_BASE 0x58000 243 244 #define RK3588_PLL_CON(x) RK2928_PLL_CON(x) 245 #define RK3588_MODE_CON0 0x280 246 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) 247 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) 248 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) 249 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 250 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 251 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 252 #define RK3588_GLB_CNT_TH 0xc00 253 #define RK3588_GLB_SRST_FST 0xc08 254 #define RK3588_GLB_SRST_SND 0xc0c 255 #define RK3588_GLB_RST_CON 0xc10 256 #define RK3588_GLB_RST_ST 0xc04 257 #define RK3588_SDIO_CON0 0xC24 258 #define RK3588_SDIO_CON1 0xC28 259 #define RK3588_SDMMC_CON0 0xC30 260 #define RK3588_SDMMC_CON1 0xC34 261 262 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) 263 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) 264 265 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) 266 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) 267 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) 268 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) 269 270 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) 271 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) 272 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) 273 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) 274 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) 275 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) 276 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) 277 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) 278 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) 279 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) 280 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) 281 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) 282 283 enum rockchip_pll_type { 284 pll_rk3036, 285 pll_rk3066, 286 pll_rk3328, 287 pll_rk3399, 288 pll_rk3588, 289 pll_rk3588_core, 290 pll_rk3588_ddr, 291 }; 292 293 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 294 _postdiv2, _dsmpd, _frac) \ 295 { \ 296 .rate = _rate##U, \ 297 .fbdiv = _fbdiv, \ 298 .postdiv1 = _postdiv1, \ 299 .refdiv = _refdiv, \ 300 .postdiv2 = _postdiv2, \ 301 .dsmpd = _dsmpd, \ 302 .frac = _frac, \ 303 } 304 305 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 306 { \ 307 .rate = _rate##U, \ 308 .nr = _nr, \ 309 .nf = _nf, \ 310 .no = _no, \ 311 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ 312 } 313 314 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ 315 { \ 316 .rate = _rate##U, \ 317 .nr = _nr, \ 318 .nf = _nf, \ 319 .no = _no, \ 320 .nb = _nb, \ 321 } 322 323 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 324 { \ 325 .rate = _rate##U, \ 326 .p = _p, \ 327 .m = _m, \ 328 .s = _s, \ 329 .k = _k, \ 330 } 331 332 /** 333 * struct rockchip_clk_provider - information about clock provider 334 * @reg_base: virtual address for the register base. 335 * @clk_data: holds clock related data like clk* and number of clocks. 336 * @cru_node: device-node of the clock-provider 337 * @grf: regmap of the general-register-files syscon 338 * @lock: maintains exclusion between callbacks for a given clock-provider. 339 */ 340 struct rockchip_clk_provider { 341 void __iomem *reg_base; 342 struct clk_onecell_data clk_data; 343 struct device_node *cru_node; 344 struct regmap *grf; 345 spinlock_t lock; 346 }; 347 348 struct rockchip_pll_rate_table { 349 unsigned long rate; 350 union { 351 struct { 352 /* for RK3066 */ 353 unsigned int nr; 354 unsigned int nf; 355 unsigned int no; 356 unsigned int nb; 357 }; 358 struct { 359 /* for RK3036/RK3399 */ 360 unsigned int fbdiv; 361 unsigned int postdiv1; 362 unsigned int refdiv; 363 unsigned int postdiv2; 364 unsigned int dsmpd; 365 unsigned int frac; 366 }; 367 struct { 368 /* for RK3588 */ 369 unsigned int m; 370 unsigned int p; 371 unsigned int s; 372 unsigned int k; 373 }; 374 }; 375 }; 376 377 /** 378 * struct rockchip_pll_clock - information about pll clock 379 * @id: platform specific id of the clock. 380 * @name: name of this pll clock. 381 * @parent_names: name of the parent clock. 382 * @num_parents: number of parents 383 * @flags: optional flags for basic clock. 384 * @con_offset: offset of the register for configuring the PLL. 385 * @mode_offset: offset of the register for configuring the PLL-mode. 386 * @mode_shift: offset inside the mode-register for the mode of this pll. 387 * @lock_shift: offset inside the lock register for the lock status. 388 * @type: Type of PLL to be registered. 389 * @pll_flags: hardware-specific flags 390 * @rate_table: Table of usable pll rates 391 * 392 * Flags: 393 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the 394 * rate_table parameters and ajust them if necessary. 395 */ 396 struct rockchip_pll_clock { 397 unsigned int id; 398 const char *name; 399 const char *const *parent_names; 400 u8 num_parents; 401 unsigned long flags; 402 int con_offset; 403 int mode_offset; 404 int mode_shift; 405 int lock_shift; 406 enum rockchip_pll_type type; 407 u8 pll_flags; 408 struct rockchip_pll_rate_table *rate_table; 409 }; 410 411 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) 412 413 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ 414 _lshift, _pflags, _rtable) \ 415 { \ 416 .id = _id, \ 417 .type = _type, \ 418 .name = _name, \ 419 .parent_names = _pnames, \ 420 .num_parents = ARRAY_SIZE(_pnames), \ 421 .flags = CLK_GET_RATE_NOCACHE | _flags, \ 422 .con_offset = _con, \ 423 .mode_offset = _mode, \ 424 .mode_shift = _mshift, \ 425 .lock_shift = _lshift, \ 426 .pll_flags = _pflags, \ 427 .rate_table = _rtable, \ 428 } 429 430 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 431 enum rockchip_pll_type pll_type, 432 const char *name, const char *const *parent_names, 433 u8 num_parents, int con_offset, int grf_lock_offset, 434 int lock_shift, int mode_offset, int mode_shift, 435 struct rockchip_pll_rate_table *rate_table, 436 unsigned long flags, u8 clk_pll_flags); 437 438 struct rockchip_cpuclk_clksel { 439 int reg; 440 u32 val; 441 }; 442 443 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 444 #define ROCKCHIP_CPUCLK_MAX_CORES 4 445 struct rockchip_cpuclk_rate_table { 446 unsigned long prate; 447 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 448 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 449 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 450 }; 451 452 /** 453 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock 454 * @core_reg[]: register offset of the cores setting register 455 * @div_core_shift[]: cores divider offset used to divide the pll value 456 * @div_core_mask[]: cores divider mask 457 * @num_cores: number of cpu cores 458 * @mux_core_reg: register offset of the cores select parent 459 * @mux_core_alt: mux value to select alternate parent 460 * @mux_core_main: mux value to select main parent of core 461 * @mux_core_shift: offset of the core multiplexer 462 * @mux_core_mask: core multiplexer mask 463 */ 464 struct rockchip_cpuclk_reg_data { 465 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES]; 466 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; 467 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; 468 int num_cores; 469 int mux_core_reg; 470 u8 mux_core_alt; 471 u8 mux_core_main; 472 u8 mux_core_shift; 473 u32 mux_core_mask; 474 }; 475 476 struct clk *rockchip_clk_register_cpuclk(const char *name, 477 const char *const *parent_names, u8 num_parents, 478 const struct rockchip_cpuclk_reg_data *reg_data, 479 const struct rockchip_cpuclk_rate_table *rates, 480 int nrates, void __iomem *reg_base, spinlock_t *lock); 481 482 struct clk *rockchip_clk_register_mmc(const char *name, 483 const char *const *parent_names, u8 num_parents, 484 void __iomem *reg, int shift); 485 486 /* 487 * DDRCLK flags, including method of setting the rate 488 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. 489 */ 490 #define ROCKCHIP_DDRCLK_SIP BIT(0) 491 492 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 493 const char *const *parent_names, 494 u8 num_parents, int mux_offset, 495 int mux_shift, int mux_width, 496 int div_shift, int div_width, 497 int ddr_flags, void __iomem *reg_base, 498 spinlock_t *lock); 499 500 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) 501 502 struct clk *rockchip_clk_register_inverter(const char *name, 503 const char *const *parent_names, u8 num_parents, 504 void __iomem *reg, int shift, int flags, 505 spinlock_t *lock); 506 507 struct clk *rockchip_clk_register_muxgrf(const char *name, 508 const char *const *parent_names, u8 num_parents, 509 int flags, struct regmap *grf, int reg, 510 int shift, int width, int mux_flags); 511 512 #define PNAME(x) static const char *const x[] __initconst 513 514 enum rockchip_clk_branch_type { 515 branch_composite, 516 branch_mux, 517 branch_muxgrf, 518 branch_divider, 519 branch_fraction_divider, 520 branch_gate, 521 branch_mmc, 522 branch_inverter, 523 branch_factor, 524 branch_ddrclk, 525 branch_half_divider, 526 }; 527 528 struct rockchip_clk_branch { 529 unsigned int id; 530 enum rockchip_clk_branch_type branch_type; 531 const char *name; 532 const char *const *parent_names; 533 u8 num_parents; 534 unsigned long flags; 535 int muxdiv_offset; 536 u8 mux_shift; 537 u8 mux_width; 538 u8 mux_flags; 539 u32 *mux_table; 540 int div_offset; 541 u8 div_shift; 542 u8 div_width; 543 u8 div_flags; 544 struct clk_div_table *div_table; 545 int gate_offset; 546 u8 gate_shift; 547 u8 gate_flags; 548 struct rockchip_clk_branch *child; 549 }; 550 551 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 552 df, go, gs, gf) \ 553 { \ 554 .id = _id, \ 555 .branch_type = branch_composite, \ 556 .name = cname, \ 557 .parent_names = pnames, \ 558 .num_parents = ARRAY_SIZE(pnames), \ 559 .flags = f, \ 560 .muxdiv_offset = mo, \ 561 .mux_shift = ms, \ 562 .mux_width = mw, \ 563 .mux_flags = mf, \ 564 .div_shift = ds, \ 565 .div_width = dw, \ 566 .div_flags = df, \ 567 .gate_offset = go, \ 568 .gate_shift = gs, \ 569 .gate_flags = gf, \ 570 } 571 572 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ 573 mf, do, ds, dw, df, go, gs, gf) \ 574 { \ 575 .id = _id, \ 576 .branch_type = branch_composite, \ 577 .name = cname, \ 578 .parent_names = pnames, \ 579 .num_parents = ARRAY_SIZE(pnames), \ 580 .flags = f, \ 581 .muxdiv_offset = mo, \ 582 .mux_shift = ms, \ 583 .mux_width = mw, \ 584 .mux_flags = mf, \ 585 .div_offset = do, \ 586 .div_shift = ds, \ 587 .div_width = dw, \ 588 .div_flags = df, \ 589 .gate_offset = go, \ 590 .gate_shift = gs, \ 591 .gate_flags = gf, \ 592 } 593 594 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ 595 go, gs, gf) \ 596 { \ 597 .id = _id, \ 598 .branch_type = branch_composite, \ 599 .name = cname, \ 600 .parent_names = (const char *[]){ pname }, \ 601 .num_parents = 1, \ 602 .flags = f, \ 603 .muxdiv_offset = mo, \ 604 .div_shift = ds, \ 605 .div_width = dw, \ 606 .div_flags = df, \ 607 .gate_offset = go, \ 608 .gate_shift = gs, \ 609 .gate_flags = gf, \ 610 } 611 612 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ 613 df, dt, go, gs, gf) \ 614 { \ 615 .id = _id, \ 616 .branch_type = branch_composite, \ 617 .name = cname, \ 618 .parent_names = (const char *[]){ pname }, \ 619 .num_parents = 1, \ 620 .flags = f, \ 621 .muxdiv_offset = mo, \ 622 .div_shift = ds, \ 623 .div_width = dw, \ 624 .div_flags = df, \ 625 .div_table = dt, \ 626 .gate_offset = go, \ 627 .gate_shift = gs, \ 628 .gate_flags = gf, \ 629 } 630 631 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 632 go, gs, gf) \ 633 { \ 634 .id = _id, \ 635 .branch_type = branch_composite, \ 636 .name = cname, \ 637 .parent_names = pnames, \ 638 .num_parents = ARRAY_SIZE(pnames), \ 639 .flags = f, \ 640 .muxdiv_offset = mo, \ 641 .mux_shift = ms, \ 642 .mux_width = mw, \ 643 .mux_flags = mf, \ 644 .gate_offset = go, \ 645 .gate_shift = gs, \ 646 .gate_flags = gf, \ 647 } 648 649 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ 650 ds, dw, df) \ 651 { \ 652 .id = _id, \ 653 .branch_type = branch_composite, \ 654 .name = cname, \ 655 .parent_names = pnames, \ 656 .num_parents = ARRAY_SIZE(pnames), \ 657 .flags = f, \ 658 .muxdiv_offset = mo, \ 659 .mux_shift = ms, \ 660 .mux_width = mw, \ 661 .mux_flags = mf, \ 662 .div_shift = ds, \ 663 .div_width = dw, \ 664 .div_flags = df, \ 665 .gate_offset = -1, \ 666 } 667 668 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ 669 mw, mf, ds, dw, df, dt) \ 670 { \ 671 .id = _id, \ 672 .branch_type = branch_composite, \ 673 .name = cname, \ 674 .parent_names = pnames, \ 675 .num_parents = ARRAY_SIZE(pnames), \ 676 .flags = f, \ 677 .muxdiv_offset = mo, \ 678 .mux_shift = ms, \ 679 .mux_width = mw, \ 680 .mux_flags = mf, \ 681 .div_shift = ds, \ 682 .div_width = dw, \ 683 .div_flags = df, \ 684 .div_table = dt, \ 685 .gate_offset = -1, \ 686 } 687 688 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ 689 { \ 690 .id = _id, \ 691 .branch_type = branch_fraction_divider, \ 692 .name = cname, \ 693 .parent_names = (const char *[]){ pname }, \ 694 .num_parents = 1, \ 695 .flags = f, \ 696 .muxdiv_offset = mo, \ 697 .div_shift = 16, \ 698 .div_width = 16, \ 699 .div_flags = df, \ 700 .gate_offset = go, \ 701 .gate_shift = gs, \ 702 .gate_flags = gf, \ 703 } 704 705 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ 706 { \ 707 .id = _id, \ 708 .branch_type = branch_fraction_divider, \ 709 .name = cname, \ 710 .parent_names = (const char *[]){ pname }, \ 711 .num_parents = 1, \ 712 .flags = f, \ 713 .muxdiv_offset = mo, \ 714 .div_shift = 16, \ 715 .div_width = 16, \ 716 .div_flags = df, \ 717 .gate_offset = go, \ 718 .gate_shift = gs, \ 719 .gate_flags = gf, \ 720 .child = ch, \ 721 } 722 723 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ 724 { \ 725 .id = _id, \ 726 .branch_type = branch_fraction_divider, \ 727 .name = cname, \ 728 .parent_names = (const char *[]){ pname }, \ 729 .num_parents = 1, \ 730 .flags = f, \ 731 .muxdiv_offset = mo, \ 732 .div_shift = 16, \ 733 .div_width = 16, \ 734 .div_flags = df, \ 735 .gate_offset = -1, \ 736 .child = ch, \ 737 } 738 739 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ 740 ds, dw, df) \ 741 { \ 742 .id = _id, \ 743 .branch_type = branch_ddrclk, \ 744 .name = cname, \ 745 .parent_names = pnames, \ 746 .num_parents = ARRAY_SIZE(pnames), \ 747 .flags = f, \ 748 .muxdiv_offset = mo, \ 749 .mux_shift = ms, \ 750 .mux_width = mw, \ 751 .div_shift = ds, \ 752 .div_width = dw, \ 753 .div_flags = df, \ 754 .gate_offset = -1, \ 755 } 756 757 #define MUX(_id, cname, pnames, f, o, s, w, mf) \ 758 { \ 759 .id = _id, \ 760 .branch_type = branch_mux, \ 761 .name = cname, \ 762 .parent_names = pnames, \ 763 .num_parents = ARRAY_SIZE(pnames), \ 764 .flags = f, \ 765 .muxdiv_offset = o, \ 766 .mux_shift = s, \ 767 .mux_width = w, \ 768 .mux_flags = mf, \ 769 .gate_offset = -1, \ 770 } 771 772 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ 773 { \ 774 .id = _id, \ 775 .branch_type = branch_mux, \ 776 .name = cname, \ 777 .parent_names = pnames, \ 778 .num_parents = ARRAY_SIZE(pnames), \ 779 .flags = f, \ 780 .muxdiv_offset = o, \ 781 .mux_shift = s, \ 782 .mux_width = w, \ 783 .mux_flags = mf, \ 784 .gate_offset = -1, \ 785 .mux_table = mt, \ 786 } 787 788 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ 789 { \ 790 .id = _id, \ 791 .branch_type = branch_muxgrf, \ 792 .name = cname, \ 793 .parent_names = pnames, \ 794 .num_parents = ARRAY_SIZE(pnames), \ 795 .flags = f, \ 796 .muxdiv_offset = o, \ 797 .mux_shift = s, \ 798 .mux_width = w, \ 799 .mux_flags = mf, \ 800 .gate_offset = -1, \ 801 } 802 803 #define DIV(_id, cname, pname, f, o, s, w, df) \ 804 { \ 805 .id = _id, \ 806 .branch_type = branch_divider, \ 807 .name = cname, \ 808 .parent_names = (const char *[]){ pname }, \ 809 .num_parents = 1, \ 810 .flags = f, \ 811 .muxdiv_offset = o, \ 812 .div_shift = s, \ 813 .div_width = w, \ 814 .div_flags = df, \ 815 .gate_offset = -1, \ 816 } 817 818 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \ 819 { \ 820 .id = _id, \ 821 .branch_type = branch_divider, \ 822 .name = cname, \ 823 .parent_names = (const char *[]){ pname }, \ 824 .num_parents = 1, \ 825 .flags = f, \ 826 .muxdiv_offset = o, \ 827 .div_shift = s, \ 828 .div_width = w, \ 829 .div_flags = df, \ 830 .div_table = dt, \ 831 } 832 833 #define GATE(_id, cname, pname, f, o, b, gf) \ 834 { \ 835 .id = _id, \ 836 .branch_type = branch_gate, \ 837 .name = cname, \ 838 .parent_names = (const char *[]){ pname }, \ 839 .num_parents = 1, \ 840 .flags = f, \ 841 .gate_offset = o, \ 842 .gate_shift = b, \ 843 .gate_flags = gf, \ 844 } 845 846 #define MMC(_id, cname, pname, offset, shift) \ 847 { \ 848 .id = _id, \ 849 .branch_type = branch_mmc, \ 850 .name = cname, \ 851 .parent_names = (const char *[]){ pname }, \ 852 .num_parents = 1, \ 853 .muxdiv_offset = offset, \ 854 .div_shift = shift, \ 855 } 856 857 #define INVERTER(_id, cname, pname, io, is, if) \ 858 { \ 859 .id = _id, \ 860 .branch_type = branch_inverter, \ 861 .name = cname, \ 862 .parent_names = (const char *[]){ pname }, \ 863 .num_parents = 1, \ 864 .muxdiv_offset = io, \ 865 .div_shift = is, \ 866 .div_flags = if, \ 867 } 868 869 #define FACTOR(_id, cname, pname, f, fm, fd) \ 870 { \ 871 .id = _id, \ 872 .branch_type = branch_factor, \ 873 .name = cname, \ 874 .parent_names = (const char *[]){ pname }, \ 875 .num_parents = 1, \ 876 .flags = f, \ 877 .div_shift = fm, \ 878 .div_width = fd, \ 879 } 880 881 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ 882 { \ 883 .id = _id, \ 884 .branch_type = branch_factor, \ 885 .name = cname, \ 886 .parent_names = (const char *[]){ pname }, \ 887 .num_parents = 1, \ 888 .flags = f, \ 889 .div_shift = fm, \ 890 .div_width = fd, \ 891 .gate_offset = go, \ 892 .gate_shift = gb, \ 893 .gate_flags = gf, \ 894 } 895 896 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 897 df, go, gs, gf) \ 898 { \ 899 .id = _id, \ 900 .branch_type = branch_half_divider, \ 901 .name = cname, \ 902 .parent_names = pnames, \ 903 .num_parents = ARRAY_SIZE(pnames), \ 904 .flags = f, \ 905 .muxdiv_offset = mo, \ 906 .mux_shift = ms, \ 907 .mux_width = mw, \ 908 .mux_flags = mf, \ 909 .div_shift = ds, \ 910 .div_width = dw, \ 911 .div_flags = df, \ 912 .gate_offset = go, \ 913 .gate_shift = gs, \ 914 .gate_flags = gf, \ 915 } 916 917 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 918 ds, dw, df) \ 919 { \ 920 .id = _id, \ 921 .branch_type = branch_half_divider, \ 922 .name = cname, \ 923 .parent_names = pnames, \ 924 .num_parents = ARRAY_SIZE(pnames), \ 925 .flags = f, \ 926 .muxdiv_offset = mo, \ 927 .mux_shift = ms, \ 928 .mux_width = mw, \ 929 .mux_flags = mf, \ 930 .div_shift = ds, \ 931 .div_width = dw, \ 932 .div_flags = df, \ 933 .gate_offset = -1, \ 934 } 935 936 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \ 937 go, gs, gf) \ 938 { \ 939 .id = _id, \ 940 .branch_type = branch_half_divider, \ 941 .name = cname, \ 942 .parent_names = (const char *[]){ pname }, \ 943 .num_parents = 1, \ 944 .flags = f, \ 945 .muxdiv_offset = mo, \ 946 .div_shift = ds, \ 947 .div_width = dw, \ 948 .div_flags = df, \ 949 .gate_offset = go, \ 950 .gate_shift = gs, \ 951 .gate_flags = gf, \ 952 } 953 954 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \ 955 { \ 956 .id = _id, \ 957 .branch_type = branch_half_divider, \ 958 .name = cname, \ 959 .parent_names = (const char *[]){ pname }, \ 960 .num_parents = 1, \ 961 .flags = f, \ 962 .muxdiv_offset = o, \ 963 .div_shift = s, \ 964 .div_width = w, \ 965 .div_flags = df, \ 966 .gate_offset = -1, \ 967 } 968 969 /* SGRF clocks are only accessible from secure mode, so not controllable */ 970 #define SGRF_GATE(_id, cname, pname) \ 971 FACTOR(_id, cname, pname, 0, 1, 1) 972 973 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, 974 void __iomem *base, unsigned long nr_clks); 975 void rockchip_clk_of_add_provider(struct device_node *np, 976 struct rockchip_clk_provider *ctx); 977 unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, 978 unsigned int nr_clk); 979 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 980 struct rockchip_clk_branch *list, 981 unsigned int nr_clk); 982 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, 983 struct rockchip_pll_clock *pll_list, 984 unsigned int nr_pll, int grf_lock_offset); 985 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, 986 unsigned int lookup_id, const char *name, 987 const char *const *parent_names, u8 num_parents, 988 const struct rockchip_cpuclk_reg_data *reg_data, 989 const struct rockchip_cpuclk_rate_table *rates, 990 int nrates); 991 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 992 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 993 unsigned int reg, void (*cb)(void)); 994 995 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 996 997 struct clk *rockchip_clk_register_halfdiv(const char *name, 998 const char *const *parent_names, 999 u8 num_parents, void __iomem *base, 1000 int muxdiv_offset, u8 mux_shift, 1001 u8 mux_width, u8 mux_flags, 1002 u8 div_shift, u8 div_width, 1003 u8 div_flags, int gate_offset, 1004 u8 gate_shift, u8 gate_flags, 1005 unsigned long flags, 1006 spinlock_t *lock); 1007 1008 #ifdef CONFIG_RESET_CONTROLLER 1009 void rockchip_register_softrst_lut(struct device_node *np, 1010 const int *lookup_table, 1011 unsigned int num_regs, 1012 void __iomem *base, u8 flags); 1013 #else 1014 static inline void rockchip_register_softrst_lut(struct device_node *np, 1015 const int *lookup_table, 1016 unsigned int num_regs, 1017 void __iomem *base, u8 flags) 1018 { 1019 } 1020 #endif 1021 1022 static inline void rockchip_register_softrst(struct device_node *np, 1023 unsigned int num_regs, 1024 void __iomem *base, u8 flags) 1025 { 1026 return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); 1027 } 1028 1029 void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); 1030 1031 #endif 1032