1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 * 9 * based on 10 * 11 * samsung/clk.h 12 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 13 * Copyright (c) 2013 Linaro Ltd. 14 * Author: Thomas Abraham <thomas.ab@samsung.com> 15 */ 16 17 #ifndef CLK_ROCKCHIP_CLK_H 18 #define CLK_ROCKCHIP_CLK_H 19 20 #include <linux/io.h> 21 #include <linux/clk-provider.h> 22 23 struct clk; 24 25 #define HIWORD_UPDATE(val, mask, shift) \ 26 ((val) << (shift) | (mask) << ((shift) + 16)) 27 28 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 29 #define BOOST_PLL_H_CON(x) ((x) * 0x4) 30 #define BOOST_CLK_CON 0x0008 31 #define BOOST_BOOST_CON 0x000c 32 #define BOOST_SWITCH_CNT 0x0010 33 #define BOOST_HIGH_PERF_CNT0 0x0014 34 #define BOOST_HIGH_PERF_CNT1 0x0018 35 #define BOOST_STATIS_THRESHOLD 0x001c 36 #define BOOST_SHORT_SWITCH_CNT 0x0020 37 #define BOOST_SWITCH_THRESHOLD 0x0024 38 #define BOOST_FSM_STATUS 0x0028 39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) 40 #define BOOST_RECOVERY_MASK 0x1 41 #define BOOST_RECOVERY_SHIFT 1 42 #define BOOST_SW_CTRL_MASK 0x1 43 #define BOOST_SW_CTRL_SHIFT 2 44 #define BOOST_LOW_FREQ_EN_MASK 0x1 45 #define BOOST_LOW_FREQ_EN_SHIFT 3 46 #define BOOST_BUSY_STATE BIT(8) 47 48 #define PX30_PLL_CON(x) ((x) * 0x4) 49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 51 #define PX30_GLB_SRST_FST 0xb8 52 #define PX30_GLB_SRST_SND 0xbc 53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 54 #define PX30_MODE_CON 0xa0 55 #define PX30_MISC_CON 0xa4 56 #define PX30_SDMMC_CON0 0x380 57 #define PX30_SDMMC_CON1 0x384 58 #define PX30_SDIO_CON0 0x388 59 #define PX30_SDIO_CON1 0x38c 60 #define PX30_EMMC_CON0 0x390 61 #define PX30_EMMC_CON1 0x394 62 63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4) 64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40) 65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80) 66 #define PX30_PMU_MODE 0x0020 67 68 #define RV1108_PLL_CON(x) ((x) * 0x4) 69 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 70 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 71 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 72 #define RV1108_GLB_SRST_FST 0x1c0 73 #define RV1108_GLB_SRST_SND 0x1c4 74 #define RV1108_MISC_CON 0x1cc 75 #define RV1108_SDMMC_CON0 0x1d8 76 #define RV1108_SDMMC_CON1 0x1dc 77 #define RV1108_SDIO_CON0 0x1e0 78 #define RV1108_SDIO_CON1 0x1e4 79 #define RV1108_EMMC_CON0 0x1e8 80 #define RV1108_EMMC_CON1 0x1ec 81 82 #define RV1126_PMU_MODE 0x0 83 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 84 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 85 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 86 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 87 #define RV1126_PLL_CON(x) ((x) * 0x4) 88 #define RV1126_MODE_CON 0x90 89 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 90 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280) 91 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 92 #define RV1126_GLB_SRST_FST 0x408 93 #define RV1126_GLB_SRST_SND 0x40c 94 #define RV1126_SDMMC_CON0 0x440 95 #define RV1126_SDMMC_CON1 0x444 96 #define RV1126_SDIO_CON0 0x448 97 #define RV1126_SDIO_CON1 0x44c 98 #define RV1126_EMMC_CON0 0x450 99 #define RV1126_EMMC_CON1 0x454 100 101 #define RK2928_PLL_CON(x) ((x) * 0x4) 102 #define RK2928_MODE_CON 0x40 103 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 104 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) 105 #define RK2928_GLB_SRST_FST 0x100 106 #define RK2928_GLB_SRST_SND 0x104 107 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 108 #define RK2928_MISC_CON 0x134 109 110 #define RK3036_SDMMC_CON0 0x144 111 #define RK3036_SDMMC_CON1 0x148 112 #define RK3036_SDIO_CON0 0x14c 113 #define RK3036_SDIO_CON1 0x150 114 #define RK3036_EMMC_CON0 0x154 115 #define RK3036_EMMC_CON1 0x158 116 117 #define RK3228_GLB_SRST_FST 0x1f0 118 #define RK3228_GLB_SRST_SND 0x1f4 119 #define RK3228_SDMMC_CON0 0x1c0 120 #define RK3228_SDMMC_CON1 0x1c4 121 #define RK3228_SDIO_CON0 0x1c8 122 #define RK3228_SDIO_CON1 0x1cc 123 #define RK3228_EMMC_CON0 0x1d8 124 #define RK3228_EMMC_CON1 0x1dc 125 126 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 127 #define RK3288_MODE_CON 0x50 128 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 129 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) 130 #define RK3288_GLB_SRST_FST 0x1b0 131 #define RK3288_GLB_SRST_SND 0x1b4 132 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) 133 #define RK3288_MISC_CON 0x1e8 134 #define RK3288_SDMMC_CON0 0x200 135 #define RK3288_SDMMC_CON1 0x204 136 #define RK3288_SDIO0_CON0 0x208 137 #define RK3288_SDIO0_CON1 0x20c 138 #define RK3288_SDIO1_CON0 0x210 139 #define RK3288_SDIO1_CON1 0x214 140 #define RK3288_EMMC_CON0 0x218 141 #define RK3288_EMMC_CON1 0x21c 142 143 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x) 144 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 145 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 146 #define RK3308_GLB_SRST_FST 0xb8 147 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 148 #define RK3308_MODE_CON 0xa0 149 #define RK3308_SDMMC_CON0 0x480 150 #define RK3308_SDMMC_CON1 0x484 151 #define RK3308_SDIO_CON0 0x488 152 #define RK3308_SDIO_CON1 0x48c 153 #define RK3308_EMMC_CON0 0x490 154 #define RK3308_EMMC_CON1 0x494 155 156 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x) 157 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 158 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 159 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) 160 #define RK3328_GLB_SRST_FST 0x9c 161 #define RK3328_GLB_SRST_SND 0x98 162 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 163 #define RK3328_MODE_CON 0x80 164 #define RK3328_MISC_CON 0x84 165 #define RK3328_SDMMC_CON0 0x380 166 #define RK3328_SDMMC_CON1 0x384 167 #define RK3328_SDIO_CON0 0x388 168 #define RK3328_SDIO_CON1 0x38c 169 #define RK3328_EMMC_CON0 0x390 170 #define RK3328_EMMC_CON1 0x394 171 #define RK3328_SDMMC_EXT_CON0 0x398 172 #define RK3328_SDMMC_EXT_CON1 0x39C 173 174 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) 175 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 176 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 177 #define RK3368_GLB_SRST_FST 0x280 178 #define RK3368_GLB_SRST_SND 0x284 179 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 180 #define RK3368_MISC_CON 0x380 181 #define RK3368_SDMMC_CON0 0x400 182 #define RK3368_SDMMC_CON1 0x404 183 #define RK3368_SDIO0_CON0 0x408 184 #define RK3368_SDIO0_CON1 0x40c 185 #define RK3368_SDIO1_CON0 0x410 186 #define RK3368_SDIO1_CON1 0x414 187 #define RK3368_EMMC_CON0 0x418 188 #define RK3368_EMMC_CON1 0x41c 189 190 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x) 191 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 192 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 193 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 194 #define RK3399_GLB_SRST_FST 0x500 195 #define RK3399_GLB_SRST_SND 0x504 196 #define RK3399_GLB_CNT_TH 0x508 197 #define RK3399_MISC_CON 0x50c 198 #define RK3399_RST_CON 0x510 199 #define RK3399_RST_ST 0x514 200 #define RK3399_SDMMC_CON0 0x580 201 #define RK3399_SDMMC_CON1 0x584 202 #define RK3399_SDIO_CON0 0x588 203 #define RK3399_SDIO_CON1 0x58c 204 205 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) 206 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) 207 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) 208 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 209 210 #define RK3528_PMU_CRU_BASE 0x10000 211 #define RK3528_PCIE_CRU_BASE 0x20000 212 #define RK3528_DDRPHY_CRU_BASE 0x28000 213 #define RK3528_PLL_CON(x) RK2928_PLL_CON(x) 214 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) 215 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) 216 #define RK3528_MODE_CON 0x280 217 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 218 #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 219 #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 220 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) 221 #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) 222 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) 223 #define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) 224 #define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) 225 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) 226 #define RK3528_GLB_CNT_TH 0xc00 227 #define RK3528_GLB_SRST_FST 0xc08 228 #define RK3528_GLB_SRST_SND 0xc0c 229 230 #define RK3562_PMU0_CRU_BASE 0x10000 231 #define RK3562_PMU1_CRU_BASE 0x18000 232 #define RK3562_DDR_CRU_BASE 0x20000 233 #define RK3562_SUBDDR_CRU_BASE 0x28000 234 #define RK3562_PERI_CRU_BASE 0x30000 235 236 #define RK3562_PLL_CON(x) RK2928_PLL_CON(x) 237 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40) 238 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20) 239 #define RK3562_MODE_CON 0x600 240 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380) 241 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380) 242 #define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 243 #define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 244 #define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 245 #define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100) 246 #define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180) 247 #define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200) 248 #define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100) 249 #define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180) 250 #define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200) 251 #define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100) 252 #define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300) 253 #define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400) 254 #define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100) 255 #define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180) 256 #define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200) 257 #define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100) 258 #define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180) 259 #define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200) 260 #define RK3562_GLB_SRST_FST 0x614 261 #define RK3562_GLB_SRST_SND 0x618 262 #define RK3562_GLB_RST_CON 0x61c 263 #define RK3562_GLB_RST_ST 0x620 264 #define RK3562_SDMMC0_CON0 0x624 265 #define RK3562_SDMMC0_CON1 0x628 266 #define RK3562_SDMMC1_CON0 0x62c 267 #define RK3562_SDMMC1_CON1 0x630 268 269 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) 270 #define RK3568_MODE_CON0 0xc0 271 #define RK3568_MISC_CON0 0xc4 272 #define RK3568_MISC_CON1 0xc8 273 #define RK3568_MISC_CON2 0xcc 274 #define RK3568_GLB_CNT_TH 0xd0 275 #define RK3568_GLB_SRST_FST 0xd4 276 #define RK3568_GLB_SRST_SND 0xd8 277 #define RK3568_GLB_RST_CON 0xdc 278 #define RK3568_GLB_RST_ST 0xe0 279 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 280 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 281 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 282 #define RK3568_SDMMC0_CON0 0x580 283 #define RK3568_SDMMC0_CON1 0x584 284 #define RK3568_SDMMC1_CON0 0x588 285 #define RK3568_SDMMC1_CON1 0x58c 286 #define RK3568_SDMMC2_CON0 0x590 287 #define RK3568_SDMMC2_CON1 0x594 288 #define RK3568_EMMC_CON0 0x598 289 #define RK3568_EMMC_CON1 0x59c 290 291 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x) 292 #define RK3568_PMU_MODE_CON0 0x80 293 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 294 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 295 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 296 297 #define RK3576_PHP_CRU_BASE 0x8000 298 #define RK3576_SECURE_NS_CRU_BASE 0x10000 299 #define RK3576_PMU_CRU_BASE 0x20000 300 #define RK3576_BIGCORE_CRU_BASE 0x38000 301 #define RK3576_LITCORE_CRU_BASE 0x40000 302 #define RK3576_CCI_CRU_BASE 0x48000 303 304 #define RK3576_PLL_CON(x) RK2928_PLL_CON(x) 305 #define RK3576_MODE_CON0 0x280 306 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) 307 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) 308 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) 309 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 310 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 311 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 312 #define RK3576_GLB_CNT_TH 0xc00 313 #define RK3576_GLB_SRST_FST 0xc08 314 #define RK3576_GLB_SRST_SND 0xc0c 315 #define RK3576_GLB_RST_CON 0xc10 316 #define RK3576_GLB_RST_ST 0xc04 317 #define RK3576_SDIO_CON0 0xC24 318 #define RK3576_SDIO_CON1 0xC28 319 #define RK3576_SDMMC_CON0 0xC30 320 #define RK3576_SDMMC_CON1 0xC34 321 322 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) 323 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) 324 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) 325 326 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) 327 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) 328 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) 329 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) 330 331 #define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300) 332 #define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800) 333 #define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00) 334 335 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) 336 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) 337 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) 338 339 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) 340 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) 341 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) 342 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) 343 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) 344 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) 345 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) 346 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) 347 #define RK3576_NON_SECURE_GATING_CON00 0xc48 348 349 #define RK3588_PHP_CRU_BASE 0x8000 350 #define RK3588_PMU_CRU_BASE 0x30000 351 #define RK3588_BIGCORE0_CRU_BASE 0x50000 352 #define RK3588_BIGCORE1_CRU_BASE 0x52000 353 #define RK3588_DSU_CRU_BASE 0x58000 354 355 #define RK3588_PLL_CON(x) RK2928_PLL_CON(x) 356 #define RK3588_MODE_CON0 0x280 357 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280) 358 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280) 359 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280) 360 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 361 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800) 362 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) 363 #define RK3588_GLB_CNT_TH 0xc00 364 #define RK3588_GLB_SRST_FST 0xc08 365 #define RK3588_GLB_SRST_SND 0xc0c 366 #define RK3588_GLB_RST_CON 0xc10 367 #define RK3588_GLB_RST_ST 0xc04 368 #define RK3588_SDIO_CON0 0xC24 369 #define RK3588_SDIO_CON1 0xC28 370 #define RK3588_SDMMC_CON0 0xC30 371 #define RK3588_SDMMC_CON1 0xC34 372 373 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800) 374 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00) 375 376 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE) 377 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300) 378 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800) 379 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00) 380 381 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE) 382 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300) 383 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800) 384 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00) 385 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE) 386 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300) 387 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800) 388 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00) 389 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE) 390 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300) 391 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800) 392 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00) 393 394 enum rockchip_pll_type { 395 pll_rk3036, 396 pll_rk3066, 397 pll_rk3328, 398 pll_rk3399, 399 pll_rk3588, 400 pll_rk3588_core, 401 pll_rk3588_ddr, 402 }; 403 404 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 405 _postdiv2, _dsmpd, _frac) \ 406 { \ 407 .rate = _rate##U, \ 408 .fbdiv = _fbdiv, \ 409 .postdiv1 = _postdiv1, \ 410 .refdiv = _refdiv, \ 411 .postdiv2 = _postdiv2, \ 412 .dsmpd = _dsmpd, \ 413 .frac = _frac, \ 414 } 415 416 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 417 { \ 418 .rate = _rate##U, \ 419 .nr = _nr, \ 420 .nf = _nf, \ 421 .no = _no, \ 422 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ 423 } 424 425 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ 426 { \ 427 .rate = _rate##U, \ 428 .nr = _nr, \ 429 .nf = _nf, \ 430 .no = _no, \ 431 .nb = _nb, \ 432 } 433 434 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ 435 { \ 436 .rate = _rate##U, \ 437 .p = _p, \ 438 .m = _m, \ 439 .s = _s, \ 440 .k = _k, \ 441 } 442 443 /** 444 * struct rockchip_clk_provider - information about clock provider 445 * @reg_base: virtual address for the register base. 446 * @clk_data: holds clock related data like clk* and number of clocks. 447 * @cru_node: device-node of the clock-provider 448 * @grf: regmap of the general-register-files syscon 449 * @lock: maintains exclusion between callbacks for a given clock-provider. 450 */ 451 struct rockchip_clk_provider { 452 void __iomem *reg_base; 453 struct clk_onecell_data clk_data; 454 struct device_node *cru_node; 455 struct regmap *grf; 456 spinlock_t lock; 457 }; 458 459 struct rockchip_pll_rate_table { 460 unsigned long rate; 461 union { 462 struct { 463 /* for RK3066 */ 464 unsigned int nr; 465 unsigned int nf; 466 unsigned int no; 467 unsigned int nb; 468 }; 469 struct { 470 /* for RK3036/RK3399 */ 471 unsigned int fbdiv; 472 unsigned int postdiv1; 473 unsigned int refdiv; 474 unsigned int postdiv2; 475 unsigned int dsmpd; 476 unsigned int frac; 477 }; 478 struct { 479 /* for RK3588 */ 480 unsigned int m; 481 unsigned int p; 482 unsigned int s; 483 unsigned int k; 484 }; 485 }; 486 }; 487 488 /** 489 * struct rockchip_pll_clock - information about pll clock 490 * @id: platform specific id of the clock. 491 * @name: name of this pll clock. 492 * @parent_names: name of the parent clock. 493 * @num_parents: number of parents 494 * @flags: optional flags for basic clock. 495 * @con_offset: offset of the register for configuring the PLL. 496 * @mode_offset: offset of the register for configuring the PLL-mode. 497 * @mode_shift: offset inside the mode-register for the mode of this pll. 498 * @lock_shift: offset inside the lock register for the lock status. 499 * @type: Type of PLL to be registered. 500 * @pll_flags: hardware-specific flags 501 * @rate_table: Table of usable pll rates 502 * 503 * Flags: 504 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the 505 * rate_table parameters and ajust them if necessary. 506 * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only 507 */ 508 struct rockchip_pll_clock { 509 unsigned int id; 510 const char *name; 511 const char *const *parent_names; 512 u8 num_parents; 513 unsigned long flags; 514 int con_offset; 515 int mode_offset; 516 int mode_shift; 517 int lock_shift; 518 enum rockchip_pll_type type; 519 u8 pll_flags; 520 struct rockchip_pll_rate_table *rate_table; 521 }; 522 523 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) 524 #define ROCKCHIP_PLL_FIXED_MODE BIT(1) 525 526 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ 527 _lshift, _pflags, _rtable) \ 528 { \ 529 .id = _id, \ 530 .type = _type, \ 531 .name = _name, \ 532 .parent_names = _pnames, \ 533 .num_parents = ARRAY_SIZE(_pnames), \ 534 .flags = CLK_GET_RATE_NOCACHE | _flags, \ 535 .con_offset = _con, \ 536 .mode_offset = _mode, \ 537 .mode_shift = _mshift, \ 538 .lock_shift = _lshift, \ 539 .pll_flags = _pflags, \ 540 .rate_table = _rtable, \ 541 } 542 543 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 544 enum rockchip_pll_type pll_type, 545 const char *name, const char *const *parent_names, 546 u8 num_parents, int con_offset, int grf_lock_offset, 547 int lock_shift, int mode_offset, int mode_shift, 548 struct rockchip_pll_rate_table *rate_table, 549 unsigned long flags, u8 clk_pll_flags); 550 551 struct rockchip_cpuclk_clksel { 552 int reg; 553 u32 val; 554 }; 555 556 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6 557 #define ROCKCHIP_CPUCLK_MAX_CORES 4 558 struct rockchip_cpuclk_rate_table { 559 unsigned long prate; 560 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 561 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 562 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 563 }; 564 565 /** 566 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock 567 * @core_reg[]: register offset of the cores setting register 568 * @div_core_shift[]: cores divider offset used to divide the pll value 569 * @div_core_mask[]: cores divider mask 570 * @num_cores: number of cpu cores 571 * @mux_core_reg: register offset of the cores select parent 572 * @mux_core_alt: mux value to select alternate parent 573 * @mux_core_main: mux value to select main parent of core 574 * @mux_core_shift: offset of the core multiplexer 575 * @mux_core_mask: core multiplexer mask 576 */ 577 struct rockchip_cpuclk_reg_data { 578 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES]; 579 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; 580 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; 581 int num_cores; 582 int mux_core_reg; 583 u8 mux_core_alt; 584 u8 mux_core_main; 585 u8 mux_core_shift; 586 u32 mux_core_mask; 587 }; 588 589 struct clk *rockchip_clk_register_cpuclk(const char *name, 590 const char *const *parent_names, u8 num_parents, 591 const struct rockchip_cpuclk_reg_data *reg_data, 592 const struct rockchip_cpuclk_rate_table *rates, 593 int nrates, void __iomem *reg_base, spinlock_t *lock); 594 595 struct clk *rockchip_clk_register_mmc(const char *name, 596 const char *const *parent_names, u8 num_parents, 597 void __iomem *reg, int shift); 598 599 /* 600 * DDRCLK flags, including method of setting the rate 601 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. 602 */ 603 #define ROCKCHIP_DDRCLK_SIP BIT(0) 604 605 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 606 const char *const *parent_names, 607 u8 num_parents, int mux_offset, 608 int mux_shift, int mux_width, 609 int div_shift, int div_width, 610 int ddr_flags, void __iomem *reg_base, 611 spinlock_t *lock); 612 613 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) 614 615 struct clk *rockchip_clk_register_inverter(const char *name, 616 const char *const *parent_names, u8 num_parents, 617 void __iomem *reg, int shift, int flags, 618 spinlock_t *lock); 619 620 struct clk *rockchip_clk_register_muxgrf(const char *name, 621 const char *const *parent_names, u8 num_parents, 622 int flags, struct regmap *grf, int reg, 623 int shift, int width, int mux_flags); 624 625 #define PNAME(x) static const char *const x[] __initconst 626 627 enum rockchip_clk_branch_type { 628 branch_composite, 629 branch_mux, 630 branch_muxgrf, 631 branch_divider, 632 branch_fraction_divider, 633 branch_gate, 634 branch_linked_gate, 635 branch_mmc, 636 branch_inverter, 637 branch_factor, 638 branch_ddrclk, 639 branch_half_divider, 640 }; 641 642 struct rockchip_clk_branch { 643 unsigned int id; 644 enum rockchip_clk_branch_type branch_type; 645 const char *name; 646 const char *const *parent_names; 647 u8 num_parents; 648 unsigned long flags; 649 int muxdiv_offset; 650 u8 mux_shift; 651 u8 mux_width; 652 u8 mux_flags; 653 u32 *mux_table; 654 int div_offset; 655 u8 div_shift; 656 u8 div_width; 657 u8 div_flags; 658 struct clk_div_table *div_table; 659 int gate_offset; 660 u8 gate_shift; 661 u8 gate_flags; 662 unsigned int linked_clk_id; 663 struct rockchip_clk_branch *child; 664 }; 665 666 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 667 df, go, gs, gf) \ 668 { \ 669 .id = _id, \ 670 .branch_type = branch_composite, \ 671 .name = cname, \ 672 .parent_names = pnames, \ 673 .num_parents = ARRAY_SIZE(pnames), \ 674 .flags = f, \ 675 .muxdiv_offset = mo, \ 676 .mux_shift = ms, \ 677 .mux_width = mw, \ 678 .mux_flags = mf, \ 679 .div_shift = ds, \ 680 .div_width = dw, \ 681 .div_flags = df, \ 682 .gate_offset = go, \ 683 .gate_shift = gs, \ 684 .gate_flags = gf, \ 685 } 686 687 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ 688 mf, do, ds, dw, df, go, gs, gf) \ 689 { \ 690 .id = _id, \ 691 .branch_type = branch_composite, \ 692 .name = cname, \ 693 .parent_names = pnames, \ 694 .num_parents = ARRAY_SIZE(pnames), \ 695 .flags = f, \ 696 .muxdiv_offset = mo, \ 697 .mux_shift = ms, \ 698 .mux_width = mw, \ 699 .mux_flags = mf, \ 700 .div_offset = do, \ 701 .div_shift = ds, \ 702 .div_width = dw, \ 703 .div_flags = df, \ 704 .gate_offset = go, \ 705 .gate_shift = gs, \ 706 .gate_flags = gf, \ 707 } 708 709 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ 710 go, gs, gf) \ 711 { \ 712 .id = _id, \ 713 .branch_type = branch_composite, \ 714 .name = cname, \ 715 .parent_names = (const char *[]){ pname }, \ 716 .num_parents = 1, \ 717 .flags = f, \ 718 .muxdiv_offset = mo, \ 719 .div_shift = ds, \ 720 .div_width = dw, \ 721 .div_flags = df, \ 722 .gate_offset = go, \ 723 .gate_shift = gs, \ 724 .gate_flags = gf, \ 725 } 726 727 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ 728 df, dt, go, gs, gf) \ 729 { \ 730 .id = _id, \ 731 .branch_type = branch_composite, \ 732 .name = cname, \ 733 .parent_names = (const char *[]){ pname }, \ 734 .num_parents = 1, \ 735 .flags = f, \ 736 .muxdiv_offset = mo, \ 737 .div_shift = ds, \ 738 .div_width = dw, \ 739 .div_flags = df, \ 740 .div_table = dt, \ 741 .gate_offset = go, \ 742 .gate_shift = gs, \ 743 .gate_flags = gf, \ 744 } 745 746 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 747 go, gs, gf) \ 748 { \ 749 .id = _id, \ 750 .branch_type = branch_composite, \ 751 .name = cname, \ 752 .parent_names = pnames, \ 753 .num_parents = ARRAY_SIZE(pnames), \ 754 .flags = f, \ 755 .muxdiv_offset = mo, \ 756 .mux_shift = ms, \ 757 .mux_width = mw, \ 758 .mux_flags = mf, \ 759 .gate_offset = go, \ 760 .gate_shift = gs, \ 761 .gate_flags = gf, \ 762 } 763 764 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ 765 ds, dw, df) \ 766 { \ 767 .id = _id, \ 768 .branch_type = branch_composite, \ 769 .name = cname, \ 770 .parent_names = pnames, \ 771 .num_parents = ARRAY_SIZE(pnames), \ 772 .flags = f, \ 773 .muxdiv_offset = mo, \ 774 .mux_shift = ms, \ 775 .mux_width = mw, \ 776 .mux_flags = mf, \ 777 .div_shift = ds, \ 778 .div_width = dw, \ 779 .div_flags = df, \ 780 .gate_offset = -1, \ 781 } 782 783 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ 784 mw, mf, ds, dw, df, dt) \ 785 { \ 786 .id = _id, \ 787 .branch_type = branch_composite, \ 788 .name = cname, \ 789 .parent_names = pnames, \ 790 .num_parents = ARRAY_SIZE(pnames), \ 791 .flags = f, \ 792 .muxdiv_offset = mo, \ 793 .mux_shift = ms, \ 794 .mux_width = mw, \ 795 .mux_flags = mf, \ 796 .div_shift = ds, \ 797 .div_width = dw, \ 798 .div_flags = df, \ 799 .div_table = dt, \ 800 .gate_offset = -1, \ 801 } 802 803 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ 804 { \ 805 .id = _id, \ 806 .branch_type = branch_fraction_divider, \ 807 .name = cname, \ 808 .parent_names = (const char *[]){ pname }, \ 809 .num_parents = 1, \ 810 .flags = f, \ 811 .muxdiv_offset = mo, \ 812 .div_shift = 16, \ 813 .div_width = 16, \ 814 .div_flags = df, \ 815 .gate_offset = go, \ 816 .gate_shift = gs, \ 817 .gate_flags = gf, \ 818 } 819 820 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ 821 { \ 822 .id = _id, \ 823 .branch_type = branch_fraction_divider, \ 824 .name = cname, \ 825 .parent_names = (const char *[]){ pname }, \ 826 .num_parents = 1, \ 827 .flags = f, \ 828 .muxdiv_offset = mo, \ 829 .div_shift = 16, \ 830 .div_width = 16, \ 831 .div_flags = df, \ 832 .gate_offset = go, \ 833 .gate_shift = gs, \ 834 .gate_flags = gf, \ 835 .child = ch, \ 836 } 837 838 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ 839 { \ 840 .id = _id, \ 841 .branch_type = branch_fraction_divider, \ 842 .name = cname, \ 843 .parent_names = (const char *[]){ pname }, \ 844 .num_parents = 1, \ 845 .flags = f, \ 846 .muxdiv_offset = mo, \ 847 .div_shift = 16, \ 848 .div_width = 16, \ 849 .div_flags = df, \ 850 .gate_offset = -1, \ 851 .child = ch, \ 852 } 853 854 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ 855 ds, dw, df) \ 856 { \ 857 .id = _id, \ 858 .branch_type = branch_ddrclk, \ 859 .name = cname, \ 860 .parent_names = pnames, \ 861 .num_parents = ARRAY_SIZE(pnames), \ 862 .flags = f, \ 863 .muxdiv_offset = mo, \ 864 .mux_shift = ms, \ 865 .mux_width = mw, \ 866 .div_shift = ds, \ 867 .div_width = dw, \ 868 .div_flags = df, \ 869 .gate_offset = -1, \ 870 } 871 872 #define MUX(_id, cname, pnames, f, o, s, w, mf) \ 873 { \ 874 .id = _id, \ 875 .branch_type = branch_mux, \ 876 .name = cname, \ 877 .parent_names = pnames, \ 878 .num_parents = ARRAY_SIZE(pnames), \ 879 .flags = f, \ 880 .muxdiv_offset = o, \ 881 .mux_shift = s, \ 882 .mux_width = w, \ 883 .mux_flags = mf, \ 884 .gate_offset = -1, \ 885 } 886 887 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ 888 { \ 889 .id = _id, \ 890 .branch_type = branch_mux, \ 891 .name = cname, \ 892 .parent_names = pnames, \ 893 .num_parents = ARRAY_SIZE(pnames), \ 894 .flags = f, \ 895 .muxdiv_offset = o, \ 896 .mux_shift = s, \ 897 .mux_width = w, \ 898 .mux_flags = mf, \ 899 .gate_offset = -1, \ 900 .mux_table = mt, \ 901 } 902 903 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ 904 { \ 905 .id = _id, \ 906 .branch_type = branch_muxgrf, \ 907 .name = cname, \ 908 .parent_names = pnames, \ 909 .num_parents = ARRAY_SIZE(pnames), \ 910 .flags = f, \ 911 .muxdiv_offset = o, \ 912 .mux_shift = s, \ 913 .mux_width = w, \ 914 .mux_flags = mf, \ 915 .gate_offset = -1, \ 916 } 917 918 #define DIV(_id, cname, pname, f, o, s, w, df) \ 919 { \ 920 .id = _id, \ 921 .branch_type = branch_divider, \ 922 .name = cname, \ 923 .parent_names = (const char *[]){ pname }, \ 924 .num_parents = 1, \ 925 .flags = f, \ 926 .muxdiv_offset = o, \ 927 .div_shift = s, \ 928 .div_width = w, \ 929 .div_flags = df, \ 930 .gate_offset = -1, \ 931 } 932 933 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \ 934 { \ 935 .id = _id, \ 936 .branch_type = branch_divider, \ 937 .name = cname, \ 938 .parent_names = (const char *[]){ pname }, \ 939 .num_parents = 1, \ 940 .flags = f, \ 941 .muxdiv_offset = o, \ 942 .div_shift = s, \ 943 .div_width = w, \ 944 .div_flags = df, \ 945 .div_table = dt, \ 946 } 947 948 #define GATE(_id, cname, pname, f, o, b, gf) \ 949 { \ 950 .id = _id, \ 951 .branch_type = branch_gate, \ 952 .name = cname, \ 953 .parent_names = (const char *[]){ pname }, \ 954 .num_parents = 1, \ 955 .flags = f, \ 956 .gate_offset = o, \ 957 .gate_shift = b, \ 958 .gate_flags = gf, \ 959 } 960 961 #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ 962 { \ 963 .id = _id, \ 964 .branch_type = branch_linked_gate, \ 965 .name = cname, \ 966 .parent_names = (const char *[]){ pname }, \ 967 .linked_clk_id = linkedclk, \ 968 .num_parents = 1, \ 969 .flags = f, \ 970 .gate_offset = o, \ 971 .gate_shift = b, \ 972 .gate_flags = gf, \ 973 } 974 975 #define MMC(_id, cname, pname, offset, shift) \ 976 { \ 977 .id = _id, \ 978 .branch_type = branch_mmc, \ 979 .name = cname, \ 980 .parent_names = (const char *[]){ pname }, \ 981 .num_parents = 1, \ 982 .muxdiv_offset = offset, \ 983 .div_shift = shift, \ 984 } 985 986 #define INVERTER(_id, cname, pname, io, is, if) \ 987 { \ 988 .id = _id, \ 989 .branch_type = branch_inverter, \ 990 .name = cname, \ 991 .parent_names = (const char *[]){ pname }, \ 992 .num_parents = 1, \ 993 .muxdiv_offset = io, \ 994 .div_shift = is, \ 995 .div_flags = if, \ 996 } 997 998 #define FACTOR(_id, cname, pname, f, fm, fd) \ 999 { \ 1000 .id = _id, \ 1001 .branch_type = branch_factor, \ 1002 .name = cname, \ 1003 .parent_names = (const char *[]){ pname }, \ 1004 .num_parents = 1, \ 1005 .flags = f, \ 1006 .div_shift = fm, \ 1007 .div_width = fd, \ 1008 } 1009 1010 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ 1011 { \ 1012 .id = _id, \ 1013 .branch_type = branch_factor, \ 1014 .name = cname, \ 1015 .parent_names = (const char *[]){ pname }, \ 1016 .num_parents = 1, \ 1017 .flags = f, \ 1018 .div_shift = fm, \ 1019 .div_width = fd, \ 1020 .gate_offset = go, \ 1021 .gate_shift = gb, \ 1022 .gate_flags = gf, \ 1023 } 1024 1025 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 1026 df, go, gs, gf) \ 1027 { \ 1028 .id = _id, \ 1029 .branch_type = branch_half_divider, \ 1030 .name = cname, \ 1031 .parent_names = pnames, \ 1032 .num_parents = ARRAY_SIZE(pnames), \ 1033 .flags = f, \ 1034 .muxdiv_offset = mo, \ 1035 .mux_shift = ms, \ 1036 .mux_width = mw, \ 1037 .mux_flags = mf, \ 1038 .div_shift = ds, \ 1039 .div_width = dw, \ 1040 .div_flags = df, \ 1041 .gate_offset = go, \ 1042 .gate_shift = gs, \ 1043 .gate_flags = gf, \ 1044 } 1045 1046 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 1047 ds, dw, df) \ 1048 { \ 1049 .id = _id, \ 1050 .branch_type = branch_half_divider, \ 1051 .name = cname, \ 1052 .parent_names = pnames, \ 1053 .num_parents = ARRAY_SIZE(pnames), \ 1054 .flags = f, \ 1055 .muxdiv_offset = mo, \ 1056 .mux_shift = ms, \ 1057 .mux_width = mw, \ 1058 .mux_flags = mf, \ 1059 .div_shift = ds, \ 1060 .div_width = dw, \ 1061 .div_flags = df, \ 1062 .gate_offset = -1, \ 1063 } 1064 1065 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \ 1066 go, gs, gf) \ 1067 { \ 1068 .id = _id, \ 1069 .branch_type = branch_half_divider, \ 1070 .name = cname, \ 1071 .parent_names = (const char *[]){ pname }, \ 1072 .num_parents = 1, \ 1073 .flags = f, \ 1074 .muxdiv_offset = mo, \ 1075 .div_shift = ds, \ 1076 .div_width = dw, \ 1077 .div_flags = df, \ 1078 .gate_offset = go, \ 1079 .gate_shift = gs, \ 1080 .gate_flags = gf, \ 1081 } 1082 1083 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \ 1084 { \ 1085 .id = _id, \ 1086 .branch_type = branch_half_divider, \ 1087 .name = cname, \ 1088 .parent_names = (const char *[]){ pname }, \ 1089 .num_parents = 1, \ 1090 .flags = f, \ 1091 .muxdiv_offset = o, \ 1092 .div_shift = s, \ 1093 .div_width = w, \ 1094 .div_flags = df, \ 1095 .gate_offset = -1, \ 1096 } 1097 1098 /* SGRF clocks are only accessible from secure mode, so not controllable */ 1099 #define SGRF_GATE(_id, cname, pname) \ 1100 FACTOR(_id, cname, pname, 0, 1, 1) 1101 1102 static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx, 1103 unsigned int id) 1104 { 1105 return ctx->clk_data.clks[id]; 1106 } 1107 1108 static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx, 1109 struct clk *clk, unsigned int id) 1110 { 1111 ctx->clk_data.clks[id] = clk; 1112 } 1113 1114 struct rockchip_gate_link_platdata { 1115 struct rockchip_clk_provider *ctx; 1116 struct rockchip_clk_branch *clkbr; 1117 }; 1118 1119 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, 1120 void __iomem *base, unsigned long nr_clks); 1121 struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, 1122 void __iomem *base, unsigned long nr_clks); 1123 void rockchip_clk_finalize(struct rockchip_clk_provider *ctx); 1124 void rockchip_clk_of_add_provider(struct device_node *np, 1125 struct rockchip_clk_provider *ctx); 1126 unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, 1127 unsigned int nr_clk); 1128 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 1129 struct rockchip_clk_branch *list, 1130 unsigned int nr_clk); 1131 void rockchip_clk_register_late_branches(struct device *dev, 1132 struct rockchip_clk_provider *ctx, 1133 struct rockchip_clk_branch *list, 1134 unsigned int nr_clk); 1135 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, 1136 struct rockchip_pll_clock *pll_list, 1137 unsigned int nr_pll, int grf_lock_offset); 1138 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, 1139 unsigned int lookup_id, const char *name, 1140 const char *const *parent_names, u8 num_parents, 1141 const struct rockchip_cpuclk_reg_data *reg_data, 1142 const struct rockchip_cpuclk_rate_table *rates, 1143 int nrates); 1144 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 1145 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 1146 unsigned int reg, void (*cb)(void)); 1147 1148 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 1149 1150 struct clk *rockchip_clk_register_halfdiv(const char *name, 1151 const char *const *parent_names, 1152 u8 num_parents, void __iomem *base, 1153 int muxdiv_offset, u8 mux_shift, 1154 u8 mux_width, u8 mux_flags, 1155 u8 div_shift, u8 div_width, 1156 u8 div_flags, int gate_offset, 1157 u8 gate_shift, u8 gate_flags, 1158 unsigned long flags, 1159 spinlock_t *lock); 1160 1161 #ifdef CONFIG_RESET_CONTROLLER 1162 void rockchip_register_softrst_lut(struct device_node *np, 1163 const int *lookup_table, 1164 unsigned int num_regs, 1165 void __iomem *base, u8 flags); 1166 #else 1167 static inline void rockchip_register_softrst_lut(struct device_node *np, 1168 const int *lookup_table, 1169 unsigned int num_regs, 1170 void __iomem *base, u8 flags) 1171 { 1172 } 1173 #endif 1174 1175 static inline void rockchip_register_softrst(struct device_node *np, 1176 unsigned int num_regs, 1177 void __iomem *base, u8 flags) 1178 { 1179 return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); 1180 } 1181 1182 void rk3528_rst_init(struct device_node *np, void __iomem *reg_base); 1183 void rk3562_rst_init(struct device_node *np, void __iomem *reg_base); 1184 void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); 1185 void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); 1186 1187 #endif 1188