1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 * 9 * based on 10 * 11 * samsung/clk.h 12 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 13 * Copyright (c) 2013 Linaro Ltd. 14 * Author: Thomas Abraham <thomas.ab@samsung.com> 15 */ 16 17 #ifndef CLK_ROCKCHIP_CLK_H 18 #define CLK_ROCKCHIP_CLK_H 19 20 #include <linux/io.h> 21 #include <linux/clk-provider.h> 22 23 struct clk; 24 25 #define HIWORD_UPDATE(val, mask, shift) \ 26 ((val) << (shift) | (mask) << ((shift) + 16)) 27 28 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 29 #define BOOST_PLL_H_CON(x) ((x) * 0x4) 30 #define BOOST_CLK_CON 0x0008 31 #define BOOST_BOOST_CON 0x000c 32 #define BOOST_SWITCH_CNT 0x0010 33 #define BOOST_HIGH_PERF_CNT0 0x0014 34 #define BOOST_HIGH_PERF_CNT1 0x0018 35 #define BOOST_STATIS_THRESHOLD 0x001c 36 #define BOOST_SHORT_SWITCH_CNT 0x0020 37 #define BOOST_SWITCH_THRESHOLD 0x0024 38 #define BOOST_FSM_STATUS 0x0028 39 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c) 40 #define BOOST_RECOVERY_MASK 0x1 41 #define BOOST_RECOVERY_SHIFT 1 42 #define BOOST_SW_CTRL_MASK 0x1 43 #define BOOST_SW_CTRL_SHIFT 2 44 #define BOOST_LOW_FREQ_EN_MASK 0x1 45 #define BOOST_LOW_FREQ_EN_SHIFT 3 46 #define BOOST_BUSY_STATE BIT(8) 47 48 #define PX30_PLL_CON(x) ((x) * 0x4) 49 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 50 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 51 #define PX30_GLB_SRST_FST 0xb8 52 #define PX30_GLB_SRST_SND 0xbc 53 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 54 #define PX30_MODE_CON 0xa0 55 #define PX30_MISC_CON 0xa4 56 #define PX30_SDMMC_CON0 0x380 57 #define PX30_SDMMC_CON1 0x384 58 #define PX30_SDIO_CON0 0x388 59 #define PX30_SDIO_CON1 0x38c 60 #define PX30_EMMC_CON0 0x390 61 #define PX30_EMMC_CON1 0x394 62 63 #define PX30_PMU_PLL_CON(x) ((x) * 0x4) 64 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40) 65 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80) 66 #define PX30_PMU_MODE 0x0020 67 68 #define RV1108_PLL_CON(x) ((x) * 0x4) 69 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 70 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 71 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 72 #define RV1108_GLB_SRST_FST 0x1c0 73 #define RV1108_GLB_SRST_SND 0x1c4 74 #define RV1108_MISC_CON 0x1cc 75 #define RV1108_SDMMC_CON0 0x1d8 76 #define RV1108_SDMMC_CON1 0x1dc 77 #define RV1108_SDIO_CON0 0x1e0 78 #define RV1108_SDIO_CON1 0x1e4 79 #define RV1108_EMMC_CON0 0x1e8 80 #define RV1108_EMMC_CON1 0x1ec 81 82 #define RV1126_PMU_MODE 0x0 83 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 84 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 85 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 86 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 87 #define RV1126_PLL_CON(x) ((x) * 0x4) 88 #define RV1126_MODE_CON 0x90 89 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 90 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280) 91 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 92 #define RV1126_GLB_SRST_FST 0x408 93 #define RV1126_GLB_SRST_SND 0x40c 94 #define RV1126_SDMMC_CON0 0x440 95 #define RV1126_SDMMC_CON1 0x444 96 #define RV1126_SDIO_CON0 0x448 97 #define RV1126_SDIO_CON1 0x44c 98 #define RV1126_EMMC_CON0 0x450 99 #define RV1126_EMMC_CON1 0x454 100 101 #define RK2928_PLL_CON(x) ((x) * 0x4) 102 #define RK2928_MODE_CON 0x40 103 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 104 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) 105 #define RK2928_GLB_SRST_FST 0x100 106 #define RK2928_GLB_SRST_SND 0x104 107 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 108 #define RK2928_MISC_CON 0x134 109 110 #define RK3036_SDMMC_CON0 0x144 111 #define RK3036_SDMMC_CON1 0x148 112 #define RK3036_SDIO_CON0 0x14c 113 #define RK3036_SDIO_CON1 0x150 114 #define RK3036_EMMC_CON0 0x154 115 #define RK3036_EMMC_CON1 0x158 116 117 #define RK3228_GLB_SRST_FST 0x1f0 118 #define RK3228_GLB_SRST_SND 0x1f4 119 #define RK3228_SDMMC_CON0 0x1c0 120 #define RK3228_SDMMC_CON1 0x1c4 121 #define RK3228_SDIO_CON0 0x1c8 122 #define RK3228_SDIO_CON1 0x1cc 123 #define RK3228_EMMC_CON0 0x1d8 124 #define RK3228_EMMC_CON1 0x1dc 125 126 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 127 #define RK3288_MODE_CON 0x50 128 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 129 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) 130 #define RK3288_GLB_SRST_FST 0x1b0 131 #define RK3288_GLB_SRST_SND 0x1b4 132 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) 133 #define RK3288_MISC_CON 0x1e8 134 #define RK3288_SDMMC_CON0 0x200 135 #define RK3288_SDMMC_CON1 0x204 136 #define RK3288_SDIO0_CON0 0x208 137 #define RK3288_SDIO0_CON1 0x20c 138 #define RK3288_SDIO1_CON0 0x210 139 #define RK3288_SDIO1_CON1 0x214 140 #define RK3288_EMMC_CON0 0x218 141 #define RK3288_EMMC_CON1 0x21c 142 143 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x) 144 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 145 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 146 #define RK3308_GLB_SRST_FST 0xb8 147 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 148 #define RK3308_MODE_CON 0xa0 149 #define RK3308_SDMMC_CON0 0x480 150 #define RK3308_SDMMC_CON1 0x484 151 #define RK3308_SDIO_CON0 0x488 152 #define RK3308_SDIO_CON1 0x48c 153 #define RK3308_EMMC_CON0 0x490 154 #define RK3308_EMMC_CON1 0x494 155 156 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x) 157 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 158 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 159 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) 160 #define RK3328_GLB_SRST_FST 0x9c 161 #define RK3328_GLB_SRST_SND 0x98 162 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 163 #define RK3328_MODE_CON 0x80 164 #define RK3328_MISC_CON 0x84 165 #define RK3328_SDMMC_CON0 0x380 166 #define RK3328_SDMMC_CON1 0x384 167 #define RK3328_SDIO_CON0 0x388 168 #define RK3328_SDIO_CON1 0x38c 169 #define RK3328_EMMC_CON0 0x390 170 #define RK3328_EMMC_CON1 0x394 171 #define RK3328_SDMMC_EXT_CON0 0x398 172 #define RK3328_SDMMC_EXT_CON1 0x39C 173 174 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) 175 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 176 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 177 #define RK3368_GLB_SRST_FST 0x280 178 #define RK3368_GLB_SRST_SND 0x284 179 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 180 #define RK3368_MISC_CON 0x380 181 #define RK3368_SDMMC_CON0 0x400 182 #define RK3368_SDMMC_CON1 0x404 183 #define RK3368_SDIO0_CON0 0x408 184 #define RK3368_SDIO0_CON1 0x40c 185 #define RK3368_SDIO1_CON0 0x410 186 #define RK3368_SDIO1_CON1 0x414 187 #define RK3368_EMMC_CON0 0x418 188 #define RK3368_EMMC_CON1 0x41c 189 190 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x) 191 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 192 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 193 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 194 #define RK3399_GLB_SRST_FST 0x500 195 #define RK3399_GLB_SRST_SND 0x504 196 #define RK3399_GLB_CNT_TH 0x508 197 #define RK3399_MISC_CON 0x50c 198 #define RK3399_RST_CON 0x510 199 #define RK3399_RST_ST 0x514 200 #define RK3399_SDMMC_CON0 0x580 201 #define RK3399_SDMMC_CON1 0x584 202 #define RK3399_SDIO_CON0 0x588 203 #define RK3399_SDIO_CON1 0x58c 204 205 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) 206 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) 207 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) 208 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 209 210 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) 211 #define RK3568_MODE_CON0 0xc0 212 #define RK3568_MISC_CON0 0xc4 213 #define RK3568_MISC_CON1 0xc8 214 #define RK3568_MISC_CON2 0xcc 215 #define RK3568_GLB_CNT_TH 0xd0 216 #define RK3568_GLB_SRST_FST 0xd4 217 #define RK3568_GLB_SRST_SND 0xd8 218 #define RK3568_GLB_RST_CON 0xdc 219 #define RK3568_GLB_RST_ST 0xe0 220 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 221 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 222 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 223 #define RK3568_SDMMC0_CON0 0x580 224 #define RK3568_SDMMC0_CON1 0x584 225 #define RK3568_SDMMC1_CON0 0x588 226 #define RK3568_SDMMC1_CON1 0x58c 227 #define RK3568_SDMMC2_CON0 0x590 228 #define RK3568_SDMMC2_CON1 0x594 229 #define RK3568_EMMC_CON0 0x598 230 #define RK3568_EMMC_CON1 0x59c 231 232 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x) 233 #define RK3568_PMU_MODE_CON0 0x80 234 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 235 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) 236 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) 237 238 enum rockchip_pll_type { 239 pll_rk3036, 240 pll_rk3066, 241 pll_rk3328, 242 pll_rk3399, 243 }; 244 245 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 246 _postdiv2, _dsmpd, _frac) \ 247 { \ 248 .rate = _rate##U, \ 249 .fbdiv = _fbdiv, \ 250 .postdiv1 = _postdiv1, \ 251 .refdiv = _refdiv, \ 252 .postdiv2 = _postdiv2, \ 253 .dsmpd = _dsmpd, \ 254 .frac = _frac, \ 255 } 256 257 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 258 { \ 259 .rate = _rate##U, \ 260 .nr = _nr, \ 261 .nf = _nf, \ 262 .no = _no, \ 263 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ 264 } 265 266 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ 267 { \ 268 .rate = _rate##U, \ 269 .nr = _nr, \ 270 .nf = _nf, \ 271 .no = _no, \ 272 .nb = _nb, \ 273 } 274 275 /** 276 * struct rockchip_clk_provider - information about clock provider 277 * @reg_base: virtual address for the register base. 278 * @clk_data: holds clock related data like clk* and number of clocks. 279 * @cru_node: device-node of the clock-provider 280 * @grf: regmap of the general-register-files syscon 281 * @lock: maintains exclusion between callbacks for a given clock-provider. 282 */ 283 struct rockchip_clk_provider { 284 void __iomem *reg_base; 285 struct clk_onecell_data clk_data; 286 struct device_node *cru_node; 287 struct regmap *grf; 288 spinlock_t lock; 289 }; 290 291 struct rockchip_pll_rate_table { 292 unsigned long rate; 293 union { 294 struct { 295 /* for RK3066 */ 296 unsigned int nr; 297 unsigned int nf; 298 unsigned int no; 299 unsigned int nb; 300 }; 301 struct { 302 /* for RK3036/RK3399 */ 303 unsigned int fbdiv; 304 unsigned int postdiv1; 305 unsigned int refdiv; 306 unsigned int postdiv2; 307 unsigned int dsmpd; 308 unsigned int frac; 309 }; 310 }; 311 }; 312 313 /** 314 * struct rockchip_pll_clock - information about pll clock 315 * @id: platform specific id of the clock. 316 * @name: name of this pll clock. 317 * @parent_names: name of the parent clock. 318 * @num_parents: number of parents 319 * @flags: optional flags for basic clock. 320 * @con_offset: offset of the register for configuring the PLL. 321 * @mode_offset: offset of the register for configuring the PLL-mode. 322 * @mode_shift: offset inside the mode-register for the mode of this pll. 323 * @lock_shift: offset inside the lock register for the lock status. 324 * @type: Type of PLL to be registered. 325 * @pll_flags: hardware-specific flags 326 * @rate_table: Table of usable pll rates 327 * 328 * Flags: 329 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the 330 * rate_table parameters and ajust them if necessary. 331 */ 332 struct rockchip_pll_clock { 333 unsigned int id; 334 const char *name; 335 const char *const *parent_names; 336 u8 num_parents; 337 unsigned long flags; 338 int con_offset; 339 int mode_offset; 340 int mode_shift; 341 int lock_shift; 342 enum rockchip_pll_type type; 343 u8 pll_flags; 344 struct rockchip_pll_rate_table *rate_table; 345 }; 346 347 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) 348 349 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ 350 _lshift, _pflags, _rtable) \ 351 { \ 352 .id = _id, \ 353 .type = _type, \ 354 .name = _name, \ 355 .parent_names = _pnames, \ 356 .num_parents = ARRAY_SIZE(_pnames), \ 357 .flags = CLK_GET_RATE_NOCACHE | _flags, \ 358 .con_offset = _con, \ 359 .mode_offset = _mode, \ 360 .mode_shift = _mshift, \ 361 .lock_shift = _lshift, \ 362 .pll_flags = _pflags, \ 363 .rate_table = _rtable, \ 364 } 365 366 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 367 enum rockchip_pll_type pll_type, 368 const char *name, const char *const *parent_names, 369 u8 num_parents, int con_offset, int grf_lock_offset, 370 int lock_shift, int mode_offset, int mode_shift, 371 struct rockchip_pll_rate_table *rate_table, 372 unsigned long flags, u8 clk_pll_flags); 373 374 struct rockchip_cpuclk_clksel { 375 int reg; 376 u32 val; 377 }; 378 379 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5 380 #define ROCKCHIP_CPUCLK_MAX_CORES 4 381 struct rockchip_cpuclk_rate_table { 382 unsigned long prate; 383 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 384 }; 385 386 /** 387 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock 388 * @core_reg[]: register offset of the cores setting register 389 * @div_core_shift[]: cores divider offset used to divide the pll value 390 * @div_core_mask[]: cores divider mask 391 * @num_cores: number of cpu cores 392 * @mux_core_main: mux value to select main parent of core 393 * @mux_core_shift: offset of the core multiplexer 394 * @mux_core_mask: core multiplexer mask 395 */ 396 struct rockchip_cpuclk_reg_data { 397 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES]; 398 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES]; 399 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES]; 400 int num_cores; 401 u8 mux_core_alt; 402 u8 mux_core_main; 403 u8 mux_core_shift; 404 u32 mux_core_mask; 405 }; 406 407 struct clk *rockchip_clk_register_cpuclk(const char *name, 408 const char *const *parent_names, u8 num_parents, 409 const struct rockchip_cpuclk_reg_data *reg_data, 410 const struct rockchip_cpuclk_rate_table *rates, 411 int nrates, void __iomem *reg_base, spinlock_t *lock); 412 413 struct clk *rockchip_clk_register_mmc(const char *name, 414 const char *const *parent_names, u8 num_parents, 415 void __iomem *reg, int shift); 416 417 /* 418 * DDRCLK flags, including method of setting the rate 419 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. 420 */ 421 #define ROCKCHIP_DDRCLK_SIP BIT(0) 422 423 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 424 const char *const *parent_names, 425 u8 num_parents, int mux_offset, 426 int mux_shift, int mux_width, 427 int div_shift, int div_width, 428 int ddr_flags, void __iomem *reg_base, 429 spinlock_t *lock); 430 431 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) 432 433 struct clk *rockchip_clk_register_inverter(const char *name, 434 const char *const *parent_names, u8 num_parents, 435 void __iomem *reg, int shift, int flags, 436 spinlock_t *lock); 437 438 struct clk *rockchip_clk_register_muxgrf(const char *name, 439 const char *const *parent_names, u8 num_parents, 440 int flags, struct regmap *grf, int reg, 441 int shift, int width, int mux_flags); 442 443 #define PNAME(x) static const char *const x[] __initconst 444 445 enum rockchip_clk_branch_type { 446 branch_composite, 447 branch_mux, 448 branch_muxgrf, 449 branch_divider, 450 branch_fraction_divider, 451 branch_gate, 452 branch_mmc, 453 branch_inverter, 454 branch_factor, 455 branch_ddrclk, 456 branch_half_divider, 457 }; 458 459 struct rockchip_clk_branch { 460 unsigned int id; 461 enum rockchip_clk_branch_type branch_type; 462 const char *name; 463 const char *const *parent_names; 464 u8 num_parents; 465 unsigned long flags; 466 int muxdiv_offset; 467 u8 mux_shift; 468 u8 mux_width; 469 u8 mux_flags; 470 u32 *mux_table; 471 int div_offset; 472 u8 div_shift; 473 u8 div_width; 474 u8 div_flags; 475 struct clk_div_table *div_table; 476 int gate_offset; 477 u8 gate_shift; 478 u8 gate_flags; 479 struct rockchip_clk_branch *child; 480 }; 481 482 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 483 df, go, gs, gf) \ 484 { \ 485 .id = _id, \ 486 .branch_type = branch_composite, \ 487 .name = cname, \ 488 .parent_names = pnames, \ 489 .num_parents = ARRAY_SIZE(pnames), \ 490 .flags = f, \ 491 .muxdiv_offset = mo, \ 492 .mux_shift = ms, \ 493 .mux_width = mw, \ 494 .mux_flags = mf, \ 495 .div_shift = ds, \ 496 .div_width = dw, \ 497 .div_flags = df, \ 498 .gate_offset = go, \ 499 .gate_shift = gs, \ 500 .gate_flags = gf, \ 501 } 502 503 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ 504 mf, do, ds, dw, df, go, gs, gf) \ 505 { \ 506 .id = _id, \ 507 .branch_type = branch_composite, \ 508 .name = cname, \ 509 .parent_names = pnames, \ 510 .num_parents = ARRAY_SIZE(pnames), \ 511 .flags = f, \ 512 .muxdiv_offset = mo, \ 513 .mux_shift = ms, \ 514 .mux_width = mw, \ 515 .mux_flags = mf, \ 516 .div_offset = do, \ 517 .div_shift = ds, \ 518 .div_width = dw, \ 519 .div_flags = df, \ 520 .gate_offset = go, \ 521 .gate_shift = gs, \ 522 .gate_flags = gf, \ 523 } 524 525 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ 526 go, gs, gf) \ 527 { \ 528 .id = _id, \ 529 .branch_type = branch_composite, \ 530 .name = cname, \ 531 .parent_names = (const char *[]){ pname }, \ 532 .num_parents = 1, \ 533 .flags = f, \ 534 .muxdiv_offset = mo, \ 535 .div_shift = ds, \ 536 .div_width = dw, \ 537 .div_flags = df, \ 538 .gate_offset = go, \ 539 .gate_shift = gs, \ 540 .gate_flags = gf, \ 541 } 542 543 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ 544 df, dt, go, gs, gf) \ 545 { \ 546 .id = _id, \ 547 .branch_type = branch_composite, \ 548 .name = cname, \ 549 .parent_names = (const char *[]){ pname }, \ 550 .num_parents = 1, \ 551 .flags = f, \ 552 .muxdiv_offset = mo, \ 553 .div_shift = ds, \ 554 .div_width = dw, \ 555 .div_flags = df, \ 556 .div_table = dt, \ 557 .gate_offset = go, \ 558 .gate_shift = gs, \ 559 .gate_flags = gf, \ 560 } 561 562 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 563 go, gs, gf) \ 564 { \ 565 .id = _id, \ 566 .branch_type = branch_composite, \ 567 .name = cname, \ 568 .parent_names = pnames, \ 569 .num_parents = ARRAY_SIZE(pnames), \ 570 .flags = f, \ 571 .muxdiv_offset = mo, \ 572 .mux_shift = ms, \ 573 .mux_width = mw, \ 574 .mux_flags = mf, \ 575 .gate_offset = go, \ 576 .gate_shift = gs, \ 577 .gate_flags = gf, \ 578 } 579 580 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ 581 ds, dw, df) \ 582 { \ 583 .id = _id, \ 584 .branch_type = branch_composite, \ 585 .name = cname, \ 586 .parent_names = pnames, \ 587 .num_parents = ARRAY_SIZE(pnames), \ 588 .flags = f, \ 589 .muxdiv_offset = mo, \ 590 .mux_shift = ms, \ 591 .mux_width = mw, \ 592 .mux_flags = mf, \ 593 .div_shift = ds, \ 594 .div_width = dw, \ 595 .div_flags = df, \ 596 .gate_offset = -1, \ 597 } 598 599 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ 600 mw, mf, ds, dw, df, dt) \ 601 { \ 602 .id = _id, \ 603 .branch_type = branch_composite, \ 604 .name = cname, \ 605 .parent_names = pnames, \ 606 .num_parents = ARRAY_SIZE(pnames), \ 607 .flags = f, \ 608 .muxdiv_offset = mo, \ 609 .mux_shift = ms, \ 610 .mux_width = mw, \ 611 .mux_flags = mf, \ 612 .div_shift = ds, \ 613 .div_width = dw, \ 614 .div_flags = df, \ 615 .div_table = dt, \ 616 .gate_offset = -1, \ 617 } 618 619 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ 620 { \ 621 .id = _id, \ 622 .branch_type = branch_fraction_divider, \ 623 .name = cname, \ 624 .parent_names = (const char *[]){ pname }, \ 625 .num_parents = 1, \ 626 .flags = f, \ 627 .muxdiv_offset = mo, \ 628 .div_shift = 16, \ 629 .div_width = 16, \ 630 .div_flags = df, \ 631 .gate_offset = go, \ 632 .gate_shift = gs, \ 633 .gate_flags = gf, \ 634 } 635 636 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ 637 { \ 638 .id = _id, \ 639 .branch_type = branch_fraction_divider, \ 640 .name = cname, \ 641 .parent_names = (const char *[]){ pname }, \ 642 .num_parents = 1, \ 643 .flags = f, \ 644 .muxdiv_offset = mo, \ 645 .div_shift = 16, \ 646 .div_width = 16, \ 647 .div_flags = df, \ 648 .gate_offset = go, \ 649 .gate_shift = gs, \ 650 .gate_flags = gf, \ 651 .child = ch, \ 652 } 653 654 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ 655 { \ 656 .id = _id, \ 657 .branch_type = branch_fraction_divider, \ 658 .name = cname, \ 659 .parent_names = (const char *[]){ pname }, \ 660 .num_parents = 1, \ 661 .flags = f, \ 662 .muxdiv_offset = mo, \ 663 .div_shift = 16, \ 664 .div_width = 16, \ 665 .div_flags = df, \ 666 .gate_offset = -1, \ 667 .child = ch, \ 668 } 669 670 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ 671 ds, dw, df) \ 672 { \ 673 .id = _id, \ 674 .branch_type = branch_ddrclk, \ 675 .name = cname, \ 676 .parent_names = pnames, \ 677 .num_parents = ARRAY_SIZE(pnames), \ 678 .flags = f, \ 679 .muxdiv_offset = mo, \ 680 .mux_shift = ms, \ 681 .mux_width = mw, \ 682 .div_shift = ds, \ 683 .div_width = dw, \ 684 .div_flags = df, \ 685 .gate_offset = -1, \ 686 } 687 688 #define MUX(_id, cname, pnames, f, o, s, w, mf) \ 689 { \ 690 .id = _id, \ 691 .branch_type = branch_mux, \ 692 .name = cname, \ 693 .parent_names = pnames, \ 694 .num_parents = ARRAY_SIZE(pnames), \ 695 .flags = f, \ 696 .muxdiv_offset = o, \ 697 .mux_shift = s, \ 698 .mux_width = w, \ 699 .mux_flags = mf, \ 700 .gate_offset = -1, \ 701 } 702 703 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ 704 { \ 705 .id = _id, \ 706 .branch_type = branch_mux, \ 707 .name = cname, \ 708 .parent_names = pnames, \ 709 .num_parents = ARRAY_SIZE(pnames), \ 710 .flags = f, \ 711 .muxdiv_offset = o, \ 712 .mux_shift = s, \ 713 .mux_width = w, \ 714 .mux_flags = mf, \ 715 .gate_offset = -1, \ 716 .mux_table = mt, \ 717 } 718 719 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ 720 { \ 721 .id = _id, \ 722 .branch_type = branch_muxgrf, \ 723 .name = cname, \ 724 .parent_names = pnames, \ 725 .num_parents = ARRAY_SIZE(pnames), \ 726 .flags = f, \ 727 .muxdiv_offset = o, \ 728 .mux_shift = s, \ 729 .mux_width = w, \ 730 .mux_flags = mf, \ 731 .gate_offset = -1, \ 732 } 733 734 #define DIV(_id, cname, pname, f, o, s, w, df) \ 735 { \ 736 .id = _id, \ 737 .branch_type = branch_divider, \ 738 .name = cname, \ 739 .parent_names = (const char *[]){ pname }, \ 740 .num_parents = 1, \ 741 .flags = f, \ 742 .muxdiv_offset = o, \ 743 .div_shift = s, \ 744 .div_width = w, \ 745 .div_flags = df, \ 746 .gate_offset = -1, \ 747 } 748 749 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \ 750 { \ 751 .id = _id, \ 752 .branch_type = branch_divider, \ 753 .name = cname, \ 754 .parent_names = (const char *[]){ pname }, \ 755 .num_parents = 1, \ 756 .flags = f, \ 757 .muxdiv_offset = o, \ 758 .div_shift = s, \ 759 .div_width = w, \ 760 .div_flags = df, \ 761 .div_table = dt, \ 762 } 763 764 #define GATE(_id, cname, pname, f, o, b, gf) \ 765 { \ 766 .id = _id, \ 767 .branch_type = branch_gate, \ 768 .name = cname, \ 769 .parent_names = (const char *[]){ pname }, \ 770 .num_parents = 1, \ 771 .flags = f, \ 772 .gate_offset = o, \ 773 .gate_shift = b, \ 774 .gate_flags = gf, \ 775 } 776 777 #define MMC(_id, cname, pname, offset, shift) \ 778 { \ 779 .id = _id, \ 780 .branch_type = branch_mmc, \ 781 .name = cname, \ 782 .parent_names = (const char *[]){ pname }, \ 783 .num_parents = 1, \ 784 .muxdiv_offset = offset, \ 785 .div_shift = shift, \ 786 } 787 788 #define INVERTER(_id, cname, pname, io, is, if) \ 789 { \ 790 .id = _id, \ 791 .branch_type = branch_inverter, \ 792 .name = cname, \ 793 .parent_names = (const char *[]){ pname }, \ 794 .num_parents = 1, \ 795 .muxdiv_offset = io, \ 796 .div_shift = is, \ 797 .div_flags = if, \ 798 } 799 800 #define FACTOR(_id, cname, pname, f, fm, fd) \ 801 { \ 802 .id = _id, \ 803 .branch_type = branch_factor, \ 804 .name = cname, \ 805 .parent_names = (const char *[]){ pname }, \ 806 .num_parents = 1, \ 807 .flags = f, \ 808 .div_shift = fm, \ 809 .div_width = fd, \ 810 } 811 812 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ 813 { \ 814 .id = _id, \ 815 .branch_type = branch_factor, \ 816 .name = cname, \ 817 .parent_names = (const char *[]){ pname }, \ 818 .num_parents = 1, \ 819 .flags = f, \ 820 .div_shift = fm, \ 821 .div_width = fd, \ 822 .gate_offset = go, \ 823 .gate_shift = gb, \ 824 .gate_flags = gf, \ 825 } 826 827 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 828 df, go, gs, gf) \ 829 { \ 830 .id = _id, \ 831 .branch_type = branch_half_divider, \ 832 .name = cname, \ 833 .parent_names = pnames, \ 834 .num_parents = ARRAY_SIZE(pnames), \ 835 .flags = f, \ 836 .muxdiv_offset = mo, \ 837 .mux_shift = ms, \ 838 .mux_width = mw, \ 839 .mux_flags = mf, \ 840 .div_shift = ds, \ 841 .div_width = dw, \ 842 .div_flags = df, \ 843 .gate_offset = go, \ 844 .gate_shift = gs, \ 845 .gate_flags = gf, \ 846 } 847 848 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 849 ds, dw, df) \ 850 { \ 851 .id = _id, \ 852 .branch_type = branch_half_divider, \ 853 .name = cname, \ 854 .parent_names = pnames, \ 855 .num_parents = ARRAY_SIZE(pnames), \ 856 .flags = f, \ 857 .muxdiv_offset = mo, \ 858 .mux_shift = ms, \ 859 .mux_width = mw, \ 860 .mux_flags = mf, \ 861 .div_shift = ds, \ 862 .div_width = dw, \ 863 .div_flags = df, \ 864 .gate_offset = -1, \ 865 } 866 867 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \ 868 go, gs, gf) \ 869 { \ 870 .id = _id, \ 871 .branch_type = branch_half_divider, \ 872 .name = cname, \ 873 .parent_names = (const char *[]){ pname }, \ 874 .num_parents = 1, \ 875 .flags = f, \ 876 .muxdiv_offset = mo, \ 877 .div_shift = ds, \ 878 .div_width = dw, \ 879 .div_flags = df, \ 880 .gate_offset = go, \ 881 .gate_shift = gs, \ 882 .gate_flags = gf, \ 883 } 884 885 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \ 886 { \ 887 .id = _id, \ 888 .branch_type = branch_half_divider, \ 889 .name = cname, \ 890 .parent_names = (const char *[]){ pname }, \ 891 .num_parents = 1, \ 892 .flags = f, \ 893 .muxdiv_offset = o, \ 894 .div_shift = s, \ 895 .div_width = w, \ 896 .div_flags = df, \ 897 .gate_offset = -1, \ 898 } 899 900 /* SGRF clocks are only accessible from secure mode, so not controllable */ 901 #define SGRF_GATE(_id, cname, pname) \ 902 FACTOR(_id, cname, pname, 0, 1, 1) 903 904 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, 905 void __iomem *base, unsigned long nr_clks); 906 void rockchip_clk_of_add_provider(struct device_node *np, 907 struct rockchip_clk_provider *ctx); 908 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, 909 struct clk *clk, unsigned int id); 910 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 911 struct rockchip_clk_branch *list, 912 unsigned int nr_clk); 913 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, 914 struct rockchip_pll_clock *pll_list, 915 unsigned int nr_pll, int grf_lock_offset); 916 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, 917 unsigned int lookup_id, const char *name, 918 const char *const *parent_names, u8 num_parents, 919 const struct rockchip_cpuclk_reg_data *reg_data, 920 const struct rockchip_cpuclk_rate_table *rates, 921 int nrates); 922 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 923 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 924 unsigned int reg, void (*cb)(void)); 925 926 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 927 928 struct clk *rockchip_clk_register_halfdiv(const char *name, 929 const char *const *parent_names, 930 u8 num_parents, void __iomem *base, 931 int muxdiv_offset, u8 mux_shift, 932 u8 mux_width, u8 mux_flags, 933 u8 div_shift, u8 div_width, 934 u8 div_flags, int gate_offset, 935 u8 gate_shift, u8 gate_flags, 936 unsigned long flags, 937 spinlock_t *lock); 938 939 #ifdef CONFIG_RESET_CONTROLLER 940 void rockchip_register_softrst(struct device_node *np, 941 unsigned int num_regs, 942 void __iomem *base, u8 flags); 943 #else 944 static inline void rockchip_register_softrst(struct device_node *np, 945 unsigned int num_regs, 946 void __iomem *base, u8 flags) 947 { 948 } 949 #endif 950 951 #endif 952