1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/platform_device.h> 11 #include <linux/syscore_ops.h> 12 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 13 #include "clk.h" 14 15 #define RK3588_GRF_SOC_STATUS0 0x600 16 #define RK3588_PHYREF_ALT_GATE 0xc38 17 18 enum rk3588_plls { 19 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, 20 }; 21 22 static struct rockchip_pll_rate_table rk3588_pll_rates[] = { 23 /* _mhz, _p, _m, _s, _k */ 24 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), 25 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), 26 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), 27 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), 28 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), 29 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), 30 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), 31 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), 32 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), 33 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), 34 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), 35 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), 36 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), 37 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), 38 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), 39 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), 40 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), 41 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), 42 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), 43 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), 44 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), 45 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), 46 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), 47 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), 48 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), 49 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), 50 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), 51 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), 52 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), 53 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), 54 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), 55 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), 56 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), 57 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), 58 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), 59 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), 60 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), 61 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), 62 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), 63 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), 64 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), 65 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), 66 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), 67 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), 68 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), 69 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), 70 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), 71 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), 72 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), 73 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), 74 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), 75 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), 76 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), 77 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), 78 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), 79 RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), 80 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), 81 RK3588_PLL_RATE(900000000, 2, 300, 2, 0), 82 RK3588_PLL_RATE(850000000, 3, 425, 2, 0), 83 RK3588_PLL_RATE(816000000, 2, 272, 2, 0), 84 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), 85 RK3588_PLL_RATE(786000000, 1, 131, 2, 0), 86 RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), 87 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), 88 RK3588_PLL_RATE(600000000, 2, 200, 2, 0), 89 RK3588_PLL_RATE(594000000, 2, 198, 2, 0), 90 RK3588_PLL_RATE(408000000, 2, 272, 3, 0), 91 RK3588_PLL_RATE(312000000, 2, 208, 3, 0), 92 RK3588_PLL_RATE(216000000, 2, 288, 4, 0), 93 RK3588_PLL_RATE(100000000, 3, 400, 5, 0), 94 RK3588_PLL_RATE(96000000, 2, 256, 5, 0), 95 { /* sentinel */ }, 96 }; 97 98 #define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 99 #define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 100 #define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 101 #define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 102 #define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f 103 #define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 104 #define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 105 #define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 106 #define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 107 #define RK3588_CLK_DSU_SEL_DF_MASK 0x1 108 #define RK3588_CLK_DSU_SEL_DF_SHIFT 15 109 #define RK3588_CLK_DSU_DF_SRC_MASK 0x3 110 #define RK3588_CLK_DSU_DF_SRC_SHIFT 12 111 #define RK3588_CLK_DSU_DF_DIV_MASK 0x1f 112 #define RK3588_CLK_DSU_DF_DIV_SHIFT 7 113 #define RK3588_ACLKM_DSU_DIV_MASK 0x1f 114 #define RK3588_ACLKM_DSU_DIV_SHIFT 1 115 #define RK3588_ACLKS_DSU_DIV_MASK 0x1f 116 #define RK3588_ACLKS_DSU_DIV_SHIFT 6 117 #define RK3588_ACLKMP_DSU_DIV_MASK 0x1f 118 #define RK3588_ACLKMP_DSU_DIV_SHIFT 11 119 #define RK3588_PERIPH_DSU_DIV_MASK 0x1f 120 #define RK3588_PERIPH_DSU_DIV_SHIFT 0 121 #define RK3588_ATCLK_DSU_DIV_MASK 0x1f 122 #define RK3588_ATCLK_DSU_DIV_SHIFT 0 123 #define RK3588_GICCLK_DSU_DIV_MASK 0x1f 124 #define RK3588_GICCLK_DSU_DIV_SHIFT 5 125 126 #define RK3588_CORE_B0_SEL(_apllcore) \ 127 { \ 128 .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ 129 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 130 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 131 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 132 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 133 } 134 135 #define RK3588_CORE_B1_SEL(_apllcore) \ 136 { \ 137 .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ 138 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 139 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 140 } 141 142 #define RK3588_CORE_B2_SEL(_apllcore) \ 143 { \ 144 .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ 145 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 146 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 147 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 148 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 149 } 150 151 #define RK3588_CORE_B3_SEL(_apllcore) \ 152 { \ 153 .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ 154 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 155 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 156 } 157 158 #define RK3588_CORE_L_SEL0(_offs, _apllcore) \ 159 { \ 160 .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ 161 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 162 RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ 163 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 164 RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ 165 } 166 167 #define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ 168 { \ 169 .reg = RK3588_DSU_CLKSEL_CON(0), \ 170 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ 171 RK3588_CLK_DSU_DF_SRC_SHIFT) | \ 172 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ 173 RK3588_CLK_DSU_DF_DIV_SHIFT), \ 174 } 175 176 #define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ 177 { \ 178 .reg = RK3588_DSU_CLKSEL_CON(1), \ 179 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ 180 RK3588_ACLKM_DSU_DIV_SHIFT) | \ 181 HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ 182 RK3588_ACLKMP_DSU_DIV_SHIFT) | \ 183 HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ 184 RK3588_ACLKS_DSU_DIV_SHIFT), \ 185 } 186 187 #define RK3588_CORE_L_SEL3(_periph) \ 188 { \ 189 .reg = RK3588_DSU_CLKSEL_CON(2), \ 190 .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ 191 RK3588_PERIPH_DSU_DIV_SHIFT), \ 192 } 193 194 #define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ 195 { \ 196 .reg = RK3588_DSU_CLKSEL_CON(3), \ 197 .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ 198 RK3588_GICCLK_DSU_DIV_SHIFT) | \ 199 HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ 200 RK3588_ATCLK_DSU_DIV_SHIFT), \ 201 } 202 203 #define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ 204 { \ 205 .prate = _prate##U, \ 206 .pre_muxs = { \ 207 RK3588_CORE_B0_SEL(0), \ 208 RK3588_CORE_B1_SEL(0), \ 209 }, \ 210 .post_muxs = { \ 211 RK3588_CORE_B0_SEL(_apllcore), \ 212 RK3588_CORE_B1_SEL(_apllcore), \ 213 }, \ 214 } 215 216 #define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ 217 { \ 218 .prate = _prate##U, \ 219 .pre_muxs = { \ 220 RK3588_CORE_B2_SEL(0), \ 221 RK3588_CORE_B3_SEL(0), \ 222 }, \ 223 .post_muxs = { \ 224 RK3588_CORE_B2_SEL(_apllcore), \ 225 RK3588_CORE_B3_SEL(_apllcore), \ 226 }, \ 227 } 228 229 #define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ 230 { \ 231 .prate = _prate##U, \ 232 .pre_muxs = { \ 233 RK3588_CORE_L_SEL0(0, 0), \ 234 RK3588_CORE_L_SEL0(1, 0), \ 235 RK3588_CORE_L_SEL1(3, 2), \ 236 RK3588_CORE_L_SEL2(2, 3, 3), \ 237 RK3588_CORE_L_SEL3(4), \ 238 RK3588_CORE_L_SEL4(4, 4), \ 239 }, \ 240 .post_muxs = { \ 241 RK3588_CORE_L_SEL0(0, _apllcore), \ 242 RK3588_CORE_L_SEL0(1, _apllcore), \ 243 RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ 244 }, \ 245 } 246 247 static struct rockchip_clk_provider *early_ctx; 248 249 static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { 250 RK3588_CPUB01CLK_RATE(2496000000, 1), 251 RK3588_CPUB01CLK_RATE(2400000000, 1), 252 RK3588_CPUB01CLK_RATE(2304000000, 1), 253 RK3588_CPUB01CLK_RATE(2208000000, 1), 254 RK3588_CPUB01CLK_RATE(2184000000, 1), 255 RK3588_CPUB01CLK_RATE(2088000000, 1), 256 RK3588_CPUB01CLK_RATE(2040000000, 1), 257 RK3588_CPUB01CLK_RATE(2016000000, 1), 258 RK3588_CPUB01CLK_RATE(1992000000, 1), 259 RK3588_CPUB01CLK_RATE(1896000000, 1), 260 RK3588_CPUB01CLK_RATE(1800000000, 1), 261 RK3588_CPUB01CLK_RATE(1704000000, 0), 262 RK3588_CPUB01CLK_RATE(1608000000, 0), 263 RK3588_CPUB01CLK_RATE(1584000000, 0), 264 RK3588_CPUB01CLK_RATE(1560000000, 0), 265 RK3588_CPUB01CLK_RATE(1536000000, 0), 266 RK3588_CPUB01CLK_RATE(1512000000, 0), 267 RK3588_CPUB01CLK_RATE(1488000000, 0), 268 RK3588_CPUB01CLK_RATE(1464000000, 0), 269 RK3588_CPUB01CLK_RATE(1440000000, 0), 270 RK3588_CPUB01CLK_RATE(1416000000, 0), 271 RK3588_CPUB01CLK_RATE(1392000000, 0), 272 RK3588_CPUB01CLK_RATE(1368000000, 0), 273 RK3588_CPUB01CLK_RATE(1344000000, 0), 274 RK3588_CPUB01CLK_RATE(1320000000, 0), 275 RK3588_CPUB01CLK_RATE(1296000000, 0), 276 RK3588_CPUB01CLK_RATE(1272000000, 0), 277 RK3588_CPUB01CLK_RATE(1248000000, 0), 278 RK3588_CPUB01CLK_RATE(1224000000, 0), 279 RK3588_CPUB01CLK_RATE(1200000000, 0), 280 RK3588_CPUB01CLK_RATE(1104000000, 0), 281 RK3588_CPUB01CLK_RATE(1008000000, 0), 282 RK3588_CPUB01CLK_RATE(912000000, 0), 283 RK3588_CPUB01CLK_RATE(816000000, 0), 284 RK3588_CPUB01CLK_RATE(696000000, 0), 285 RK3588_CPUB01CLK_RATE(600000000, 0), 286 RK3588_CPUB01CLK_RATE(408000000, 0), 287 RK3588_CPUB01CLK_RATE(312000000, 0), 288 RK3588_CPUB01CLK_RATE(216000000, 0), 289 RK3588_CPUB01CLK_RATE(96000000, 0), 290 }; 291 292 static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { 293 .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), 294 .div_core_shift[0] = 8, 295 .div_core_mask[0] = 0x1f, 296 .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), 297 .div_core_shift[1] = 0, 298 .div_core_mask[1] = 0x1f, 299 .num_cores = 2, 300 .mux_core_alt = 1, 301 .mux_core_main = 2, 302 .mux_core_shift = 6, 303 .mux_core_mask = 0x3, 304 }; 305 306 static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { 307 RK3588_CPUB23CLK_RATE(2496000000, 1), 308 RK3588_CPUB23CLK_RATE(2400000000, 1), 309 RK3588_CPUB23CLK_RATE(2304000000, 1), 310 RK3588_CPUB23CLK_RATE(2208000000, 1), 311 RK3588_CPUB23CLK_RATE(2184000000, 1), 312 RK3588_CPUB23CLK_RATE(2088000000, 1), 313 RK3588_CPUB23CLK_RATE(2040000000, 1), 314 RK3588_CPUB23CLK_RATE(2016000000, 1), 315 RK3588_CPUB23CLK_RATE(1992000000, 1), 316 RK3588_CPUB23CLK_RATE(1896000000, 1), 317 RK3588_CPUB23CLK_RATE(1800000000, 1), 318 RK3588_CPUB23CLK_RATE(1704000000, 0), 319 RK3588_CPUB23CLK_RATE(1608000000, 0), 320 RK3588_CPUB23CLK_RATE(1584000000, 0), 321 RK3588_CPUB23CLK_RATE(1560000000, 0), 322 RK3588_CPUB23CLK_RATE(1536000000, 0), 323 RK3588_CPUB23CLK_RATE(1512000000, 0), 324 RK3588_CPUB23CLK_RATE(1488000000, 0), 325 RK3588_CPUB23CLK_RATE(1464000000, 0), 326 RK3588_CPUB23CLK_RATE(1440000000, 0), 327 RK3588_CPUB23CLK_RATE(1416000000, 0), 328 RK3588_CPUB23CLK_RATE(1392000000, 0), 329 RK3588_CPUB23CLK_RATE(1368000000, 0), 330 RK3588_CPUB23CLK_RATE(1344000000, 0), 331 RK3588_CPUB23CLK_RATE(1320000000, 0), 332 RK3588_CPUB23CLK_RATE(1296000000, 0), 333 RK3588_CPUB23CLK_RATE(1272000000, 0), 334 RK3588_CPUB23CLK_RATE(1248000000, 0), 335 RK3588_CPUB23CLK_RATE(1224000000, 0), 336 RK3588_CPUB23CLK_RATE(1200000000, 0), 337 RK3588_CPUB23CLK_RATE(1104000000, 0), 338 RK3588_CPUB23CLK_RATE(1008000000, 0), 339 RK3588_CPUB23CLK_RATE(912000000, 0), 340 RK3588_CPUB23CLK_RATE(816000000, 0), 341 RK3588_CPUB23CLK_RATE(696000000, 0), 342 RK3588_CPUB23CLK_RATE(600000000, 0), 343 RK3588_CPUB23CLK_RATE(408000000, 0), 344 RK3588_CPUB23CLK_RATE(312000000, 0), 345 RK3588_CPUB23CLK_RATE(216000000, 0), 346 RK3588_CPUB23CLK_RATE(96000000, 0), 347 }; 348 349 static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { 350 .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), 351 .div_core_shift[0] = 8, 352 .div_core_mask[0] = 0x1f, 353 .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), 354 .div_core_shift[1] = 0, 355 .div_core_mask[1] = 0x1f, 356 .num_cores = 2, 357 .mux_core_alt = 1, 358 .mux_core_main = 2, 359 .mux_core_shift = 6, 360 .mux_core_mask = 0x3, 361 }; 362 363 static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { 364 RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), 365 RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), 366 RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), 367 RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), 368 RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), 369 RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), 370 RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), 371 RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), 372 RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), 373 RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), 374 RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), 375 RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), 376 RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), 377 RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), 378 RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), 379 RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), 380 RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), 381 RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), 382 RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), 383 RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), 384 RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), 385 RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), 386 RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), 387 RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), 388 RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), 389 RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), 390 RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), 391 RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), 392 RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), 393 RK3588_CPULCLK_RATE(912000000, 0, 2, 1), 394 RK3588_CPULCLK_RATE(816000000, 0, 2, 1), 395 RK3588_CPULCLK_RATE(696000000, 0, 2, 1), 396 RK3588_CPULCLK_RATE(600000000, 0, 2, 1), 397 RK3588_CPULCLK_RATE(408000000, 0, 2, 1), 398 RK3588_CPULCLK_RATE(312000000, 0, 2, 1), 399 RK3588_CPULCLK_RATE(216000000, 0, 2, 1), 400 RK3588_CPULCLK_RATE(96000000, 0, 2, 1), 401 }; 402 403 static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { 404 .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), 405 .div_core_shift[0] = 0, 406 .div_core_mask[0] = 0x1f, 407 .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), 408 .div_core_shift[1] = 7, 409 .div_core_mask[1] = 0x1f, 410 .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), 411 .div_core_shift[2] = 0, 412 .div_core_mask[2] = 0x1f, 413 .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), 414 .div_core_shift[3] = 7, 415 .div_core_mask[3] = 0x1f, 416 .num_cores = 4, 417 .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), 418 .mux_core_alt = 1, 419 .mux_core_main = 2, 420 .mux_core_shift = 14, 421 .mux_core_mask = 0x3, 422 }; 423 424 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 425 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; 426 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; 427 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; 428 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; 429 PNAME(gpll_24m_p) = { "gpll", "xin24m" }; 430 PNAME(gpll_aupll_p) = { "gpll", "aupll" }; 431 PNAME(gpll_lpll_p) = { "gpll", "lpll" }; 432 PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 433 PNAME(gpll_spll_p) = { "gpll", "spll" }; 434 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; 435 PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; 436 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; 437 PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; 438 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; 439 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; 440 PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; 441 PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; 442 PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; 443 PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; 444 PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; 445 PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; 446 PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; 447 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; 448 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; 449 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; 450 PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; 451 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; 452 PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; 453 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; 454 PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; 455 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 456 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 457 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 458 PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; 459 PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; 460 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; 461 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 462 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; 463 PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; 464 PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; 465 PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; 466 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; 467 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; 468 PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; 469 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; 470 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; 471 PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; 472 PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; 473 PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; 474 PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; 475 PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; 476 PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; 477 PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; 478 PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; 479 PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; 480 PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; 481 PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; 482 PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; 483 PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; 484 PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; 485 PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; 486 PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; 487 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; 488 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 489 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 490 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 491 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 492 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 493 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 494 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 495 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 496 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 497 PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; 498 PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; 499 PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; 500 PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; 501 PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; 502 PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 503 PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 504 PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 505 PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; 506 PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; 507 PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; 508 PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 509 PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "xin32k", "clk_pmu1_100m_src" }; 510 PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 511 PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; 512 PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; 513 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; 514 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 515 PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; 516 PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; 517 PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; 518 519 #define MFLAGS CLK_MUX_HIWORD_MASK 520 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 521 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 522 523 static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = 524 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 525 RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); 526 527 static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = 528 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 529 RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); 530 531 static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = 532 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 533 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); 534 535 static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = 536 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 537 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); 538 539 static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = 540 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 541 RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); 542 543 static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = 544 MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, 545 RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); 546 547 static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = 548 MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, 549 RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); 550 551 static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = 552 MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, 553 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); 554 555 static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = 556 MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, 557 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); 558 559 static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = 560 MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, 561 RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); 562 563 static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = 564 MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, 565 RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); 566 567 static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = 568 MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, 569 RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); 570 571 static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = 572 MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, 573 RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); 574 575 static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = 576 MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, 577 RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); 578 579 static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = 580 MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, 581 RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); 582 583 static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = 584 MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, 585 RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); 586 587 static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = 588 MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, 589 RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); 590 591 static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = 592 MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, 593 RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); 594 595 static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = 596 MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, 597 RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); 598 599 static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = 600 MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, 601 RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); 602 603 static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = 604 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, 605 RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); 606 607 static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = 608 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, 609 RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); 610 611 static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = 612 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, 613 RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); 614 615 static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = 616 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, 617 RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); 618 619 static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = 620 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, 621 RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); 622 623 static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = 624 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, 625 RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); 626 627 static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = 628 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, 629 RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); 630 631 static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = 632 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, 633 RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); 634 635 static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = 636 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, 637 RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); 638 639 static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = 640 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, 641 RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); 642 643 static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = 644 MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, 645 RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); 646 647 static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { 648 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, 649 CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), 650 RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 651 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, 652 CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), 653 RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 654 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, 655 CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), 656 RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 657 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, 658 0, RK3588_PLL_CON(88), 659 RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), 660 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, 661 0, RK3588_PLL_CON(96), 662 RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), 663 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, 664 CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), 665 RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), 666 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, 667 CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), 668 RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), 669 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, 670 0, RK3588_PLL_CON(120), 671 RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 672 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, 673 CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), 674 RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), 675 }; 676 677 static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { 678 /* 679 * CRU Clock-Architecture 680 */ 681 /* fixed */ 682 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 683 684 /* top */ 685 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, 686 RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, 687 RK3588_CLKGATE_CON(0), 0, GFLAGS), 688 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, 689 RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, 690 RK3588_CLKGATE_CON(0), 1, GFLAGS), 691 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, 692 RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 693 RK3588_CLKGATE_CON(0), 2, GFLAGS), 694 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 695 RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, 696 RK3588_CLKGATE_CON(0), 3, GFLAGS), 697 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, 698 RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 699 RK3588_CLKGATE_CON(0), 4, GFLAGS), 700 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, 701 RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, 702 RK3588_CLKGATE_CON(0), 5, GFLAGS), 703 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, 704 RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, 705 RK3588_CLKGATE_CON(0), 6, GFLAGS), 706 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, 707 RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, 708 RK3588_CLKGATE_CON(0), 7, GFLAGS), 709 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, 710 RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, 711 RK3588_CLKGATE_CON(0), 8, GFLAGS), 712 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, 713 RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, 714 RK3588_CLKGATE_CON(0), 9, GFLAGS), 715 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, 716 RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, 717 RK3588_CLKGATE_CON(0), 10, GFLAGS), 718 COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, 719 RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, 720 RK3588_CLKGATE_CON(0), 11, GFLAGS), 721 COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, 722 RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, 723 RK3588_CLKGATE_CON(0), 12, GFLAGS), 724 COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, 725 RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, 726 RK3588_CLKGATE_CON(0), 13, GFLAGS), 727 COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, 728 RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, 729 RK3588_CLKGATE_CON(0), 14, GFLAGS), 730 COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 731 RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, 732 RK3588_CLKGATE_CON(0), 15, GFLAGS), 733 COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 734 RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, 735 RK3588_CLKGATE_CON(1), 10, GFLAGS), 736 COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, 737 RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, 738 RK3588_CLKGATE_CON(1), 11, GFLAGS), 739 COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 740 RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, 741 RK3588_CLKGATE_CON(1), 12, GFLAGS), 742 COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 743 RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, 744 RK3588_CLKGATE_CON(1), 13, GFLAGS), 745 COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 746 RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, 747 RK3588_CLKGATE_CON(1), 14, GFLAGS), 748 COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, 749 RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, 750 RK3588_CLKGATE_CON(1), 0, GFLAGS), 751 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 752 RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, 753 RK3588_CLKGATE_CON(1), 1, GFLAGS), 754 COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 755 RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, 756 RK3588_CLKGATE_CON(1), 2, GFLAGS), 757 COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, 758 RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, 759 RK3588_CLKGATE_CON(5), 9, GFLAGS), 760 COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, 761 RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, 762 RK3588_CLKGATE_CON(5), 10, GFLAGS), 763 COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, 764 RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, 765 RK3588_CLKGATE_CON(5), 11, GFLAGS), 766 COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, 767 RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, 768 RK3588_CLKGATE_CON(5), 12, GFLAGS), 769 COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, 770 RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, 771 RK3588_CLKGATE_CON(5), 13, GFLAGS), 772 COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, 773 RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, 774 RK3588_CLKGATE_CON(5), 3, GFLAGS), 775 COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, CLK_IS_CRITICAL, 776 RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, 777 RK3588_CLKGATE_CON(5), 4, GFLAGS), 778 COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, CLK_IS_CRITICAL, 779 RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, 780 RK3588_CLKGATE_CON(5), 5, GFLAGS), 781 COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, 782 RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, 783 RK3588_CLKGATE_CON(5), 6, GFLAGS), 784 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, 785 RK3588_CLKGATE_CON(3), 14, GFLAGS), 786 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, 787 RK3588_CLKGATE_CON(4), 3, GFLAGS), 788 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, 789 RK3588_CLKGATE_CON(1), 6, GFLAGS), 790 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, 791 RK3588_CLKGATE_CON(1), 8, GFLAGS), 792 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, 793 RK3588_CLKGATE_CON(5), 0, GFLAGS), 794 795 /* bigcore0 */ 796 COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, 797 CLK_IS_CRITICAL, 798 RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, 799 RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), 800 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, 801 RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), 802 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, 803 RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), 804 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, 805 RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), 806 807 /* bigcore1 */ 808 COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, 809 CLK_IS_CRITICAL, 810 RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, 811 RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), 812 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, 813 RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), 814 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, 815 RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), 816 GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, 817 RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), 818 819 /* dsu */ 820 COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 821 RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, 822 RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), 823 COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 824 RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 825 RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), 826 COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 827 RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 828 RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), 829 COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, 830 RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 831 RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), 832 COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, 833 RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 834 RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), 835 COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, 836 RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 837 RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), 838 COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, 839 RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 840 RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), 841 COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 842 RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 843 RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), 844 COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 845 RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 846 RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), 847 COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 848 RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, 849 RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), 850 COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 851 RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, 852 RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), 853 COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 854 RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, 855 RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), 856 GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, 857 RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), 858 GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, 859 RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), 860 GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, 861 RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), 862 GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, 863 RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), 864 GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, 865 RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), 866 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, 867 RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), 868 GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, 869 RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), 870 871 /* audio */ 872 COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, 873 RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, 874 RK3588_CLKGATE_CON(7), 0, GFLAGS), 875 COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, 876 RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, 877 RK3588_CLKGATE_CON(7), 1, GFLAGS), 878 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, 879 RK3588_CLKGATE_CON(7), 12, GFLAGS), 880 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, 881 RK3588_CLKGATE_CON(7), 13, GFLAGS), 882 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, 883 RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, 884 RK3588_CLKGATE_CON(7), 14, GFLAGS), 885 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", 886 CLK_SET_RATE_PARENT, 887 RK3588_CLKSEL_CON(29), 0, 888 RK3588_CLKGATE_CON(7), 15, GFLAGS, 889 &rk3588_i2s2_2ch_fracmux), 890 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 891 RK3588_CLKGATE_CON(8), 0, GFLAGS), 892 MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, 893 RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), 894 895 COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, 896 RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, 897 RK3588_CLKGATE_CON(8), 1, GFLAGS), 898 COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", 899 CLK_SET_RATE_PARENT, 900 RK3588_CLKSEL_CON(31), 0, 901 RK3588_CLKGATE_CON(8), 2, GFLAGS, 902 &rk3588_i2s3_2ch_fracmux), 903 GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, 904 RK3588_CLKGATE_CON(8), 3, GFLAGS), 905 GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, 906 RK3588_CLKGATE_CON(8), 4, GFLAGS), 907 MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, 908 RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), 909 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, 910 RK3588_CLKGATE_CON(7), 11, GFLAGS), 911 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, 912 RK3588_CLKGATE_CON(7), 4, GFLAGS), 913 914 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, 915 RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, 916 RK3588_CLKGATE_CON(7), 5, GFLAGS), 917 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", 918 CLK_SET_RATE_PARENT, 919 RK3588_CLKSEL_CON(25), 0, 920 RK3588_CLKGATE_CON(7), 6, GFLAGS, 921 &rk3588_i2s0_8ch_tx_fracmux), 922 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 923 RK3588_CLKGATE_CON(7), 7, GFLAGS), 924 925 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, 926 RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, 927 RK3588_CLKGATE_CON(7), 8, GFLAGS), 928 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", 929 CLK_SET_RATE_PARENT, 930 RK3588_CLKSEL_CON(27), 0, 931 RK3588_CLKGATE_CON(7), 9, GFLAGS, 932 &rk3588_i2s0_8ch_rx_fracmux), 933 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 934 RK3588_CLKGATE_CON(7), 10, GFLAGS), 935 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, 936 RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), 937 938 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, 939 RK3588_CLKGATE_CON(9), 6, GFLAGS), 940 COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, 941 RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, 942 RK3588_CLKGATE_CON(9), 7, GFLAGS), 943 944 GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, 945 RK3588_CLKGATE_CON(8), 14, GFLAGS), 946 COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, 947 RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, 948 RK3588_CLKGATE_CON(8), 15, GFLAGS), 949 COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", 950 CLK_SET_RATE_PARENT, 951 RK3588_CLKSEL_CON(33), 0, 952 RK3588_CLKGATE_CON(9), 0, GFLAGS, 953 &rk3588_spdif0_fracmux), 954 GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, 955 RK3588_CLKGATE_CON(9), 1, GFLAGS), 956 957 GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, 958 RK3588_CLKGATE_CON(9), 2, GFLAGS), 959 COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, 960 RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, 961 RK3588_CLKGATE_CON(9), 3, GFLAGS), 962 COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", 963 CLK_SET_RATE_PARENT, 964 RK3588_CLKSEL_CON(35), 0, 965 RK3588_CLKGATE_CON(9), 4, GFLAGS, 966 &rk3588_spdif1_fracmux), 967 GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, 968 RK3588_CLKGATE_CON(9), 5, GFLAGS), 969 970 COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, 971 RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, 972 RK3588_CLKGATE_CON(68), 0, GFLAGS), 973 COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, 974 RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, 975 RK3588_CLKGATE_CON(68), 3, GFLAGS), 976 977 /* bus */ 978 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, 979 RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 980 RK3588_CLKGATE_CON(10), 0, GFLAGS), 981 982 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, 983 RK3588_CLKGATE_CON(16), 11, GFLAGS), 984 GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, 985 RK3588_CLKGATE_CON(16), 12, GFLAGS), 986 GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, 987 RK3588_CLKGATE_CON(16), 13, GFLAGS), 988 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, 989 RK3588_CLKGATE_CON(19), 3, GFLAGS), 990 GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 991 RK3588_CLKGATE_CON(19), 4, GFLAGS), 992 GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 993 RK3588_CLKGATE_CON(19), 5, GFLAGS), 994 995 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, 996 RK3588_CLKGATE_CON(15), 3, GFLAGS), 997 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, 998 RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, 999 RK3588_CLKGATE_CON(15), 4, GFLAGS), 1000 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1001 RK3588_CLKGATE_CON(15), 5, GFLAGS), 1002 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, 1003 RK3588_CLKGATE_CON(15), 6, GFLAGS), 1004 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, 1005 RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, 1006 RK3588_CLKGATE_CON(15), 7, GFLAGS), 1007 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1008 RK3588_CLKGATE_CON(15), 8, GFLAGS), 1009 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, 1010 RK3588_CLKGATE_CON(15), 9, GFLAGS), 1011 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, 1012 RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, 1013 RK3588_CLKGATE_CON(15), 10, GFLAGS), 1014 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1015 RK3588_CLKGATE_CON(15), 11, GFLAGS), 1016 1017 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, 1018 RK3588_CLKGATE_CON(15), 12, GFLAGS), 1019 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, 1020 RK3588_CLKGATE_CON(15), 13, GFLAGS), 1021 COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, 1022 RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, 1023 RK3588_CLKGATE_CON(15), 14, GFLAGS), 1024 GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, 1025 RK3588_CLKGATE_CON(15), 15, GFLAGS), 1026 GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, 1027 RK3588_CLKGATE_CON(16), 0, GFLAGS), 1028 GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, 1029 RK3588_CLKGATE_CON(16), 1, GFLAGS), 1030 GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, 1031 RK3588_CLKGATE_CON(16), 2, GFLAGS), 1032 GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, 1033 RK3588_CLKGATE_CON(16), 3, GFLAGS), 1034 GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, 1035 RK3588_CLKGATE_CON(16), 4, GFLAGS), 1036 GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, 1037 RK3588_CLKGATE_CON(16), 5, GFLAGS), 1038 GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, 1039 RK3588_CLKGATE_CON(16), 6, GFLAGS), 1040 GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, 1041 RK3588_CLKGATE_CON(16), 7, GFLAGS), 1042 GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, 1043 RK3588_CLKGATE_CON(16), 8, GFLAGS), 1044 GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, 1045 RK3588_CLKGATE_CON(16), 9, GFLAGS), 1046 GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, 1047 RK3588_CLKGATE_CON(16), 10, GFLAGS), 1048 1049 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, 1050 RK3588_CLKGATE_CON(15), 0, GFLAGS), 1051 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, 1052 RK3588_CLKGATE_CON(15), 1, GFLAGS), 1053 1054 GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, 1055 RK3588_CLKGATE_CON(11), 8, GFLAGS), 1056 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1057 RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, 1058 RK3588_CLKGATE_CON(11), 9, GFLAGS), 1059 GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, 1060 RK3588_CLKGATE_CON(11), 10, GFLAGS), 1061 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1062 RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, 1063 RK3588_CLKGATE_CON(11), 11, GFLAGS), 1064 GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, 1065 RK3588_CLKGATE_CON(11), 12, GFLAGS), 1066 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1067 RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, 1068 RK3588_CLKGATE_CON(11), 13, GFLAGS), 1069 1070 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, 1071 RK3588_CLKGATE_CON(17), 6, GFLAGS), 1072 GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, 1073 RK3588_CLKGATE_CON(17), 7, GFLAGS), 1074 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, 1075 RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, 1076 RK3588_CLKGATE_CON(17), 8, GFLAGS), 1077 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, 1078 RK3588_CLKGATE_CON(10), 5, GFLAGS), 1079 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, 1080 RK3588_CLKGATE_CON(10), 6, GFLAGS), 1081 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, 1082 RK3588_CLKGATE_CON(10), 7, GFLAGS), 1083 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, 1084 RK3588_CLKGATE_CON(10), 3, GFLAGS), 1085 1086 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, 1087 RK3588_CLKGATE_CON(16), 14, GFLAGS), 1088 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, 1089 RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, 1090 RK3588_CLKGATE_CON(16), 15, GFLAGS), 1091 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, 1092 RK3588_CLKGATE_CON(17), 0, GFLAGS), 1093 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, 1094 RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, 1095 RK3588_CLKGATE_CON(17), 1, GFLAGS), 1096 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, 1097 RK3588_CLKGATE_CON(17), 2, GFLAGS), 1098 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, 1099 RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, 1100 RK3588_CLKGATE_CON(17), 3, GFLAGS), 1101 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, 1102 RK3588_CLKGATE_CON(17), 4, GFLAGS), 1103 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, 1104 RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, 1105 RK3588_CLKGATE_CON(17), 5, GFLAGS), 1106 1107 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, 1108 RK3588_CLKGATE_CON(10), 8, GFLAGS), 1109 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, 1110 RK3588_CLKGATE_CON(10), 9, GFLAGS), 1111 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, 1112 RK3588_CLKGATE_CON(10), 10, GFLAGS), 1113 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, 1114 RK3588_CLKGATE_CON(10), 11, GFLAGS), 1115 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, 1116 RK3588_CLKGATE_CON(10), 12, GFLAGS), 1117 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, 1118 RK3588_CLKGATE_CON(10), 13, GFLAGS), 1119 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, 1120 RK3588_CLKGATE_CON(10), 14, GFLAGS), 1121 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, 1122 RK3588_CLKGATE_CON(10), 15, GFLAGS), 1123 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, 1124 RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, 1125 RK3588_CLKGATE_CON(11), 0, GFLAGS), 1126 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, 1127 RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, 1128 RK3588_CLKGATE_CON(11), 1, GFLAGS), 1129 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, 1130 RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, 1131 RK3588_CLKGATE_CON(11), 2, GFLAGS), 1132 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, 1133 RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, 1134 RK3588_CLKGATE_CON(11), 3, GFLAGS), 1135 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, 1136 RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, 1137 RK3588_CLKGATE_CON(11), 4, GFLAGS), 1138 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, 1139 RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, 1140 RK3588_CLKGATE_CON(11), 5, GFLAGS), 1141 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, 1142 RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, 1143 RK3588_CLKGATE_CON(11), 6, GFLAGS), 1144 COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, 1145 RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, 1146 RK3588_CLKGATE_CON(11), 7, GFLAGS), 1147 1148 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, 1149 RK3588_CLKGATE_CON(18), 9, GFLAGS), 1150 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, 1151 RK3588_CLKGATE_CON(18), 10, GFLAGS), 1152 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, 1153 RK3588_CLKGATE_CON(18), 11, GFLAGS), 1154 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, 1155 RK3588_CLKGATE_CON(18), 13, GFLAGS), 1156 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, 1157 RK3588_CLKGATE_CON(18), 12, GFLAGS), 1158 1159 GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, 1160 RK3588_CLKGATE_CON(11), 14, GFLAGS), 1161 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, 1162 RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, 1163 RK3588_CLKGATE_CON(11), 15, GFLAGS), 1164 1165 GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, 1166 RK3588_CLKGATE_CON(14), 6, GFLAGS), 1167 GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, 1168 RK3588_CLKGATE_CON(14), 7, GFLAGS), 1169 GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, 1170 RK3588_CLKGATE_CON(14), 8, GFLAGS), 1171 GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, 1172 RK3588_CLKGATE_CON(14), 9, GFLAGS), 1173 GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, 1174 RK3588_CLKGATE_CON(14), 10, GFLAGS), 1175 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, 1176 RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, 1177 RK3588_CLKGATE_CON(14), 11, GFLAGS), 1178 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, 1179 RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, 1180 RK3588_CLKGATE_CON(14), 12, GFLAGS), 1181 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, 1182 RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, 1183 RK3588_CLKGATE_CON(14), 13, GFLAGS), 1184 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, 1185 RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, 1186 RK3588_CLKGATE_CON(14), 14, GFLAGS), 1187 COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, 1188 RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, 1189 RK3588_CLKGATE_CON(14), 15, GFLAGS), 1190 1191 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, 1192 RK3588_CLKGATE_CON(18), 6, GFLAGS), 1193 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, 1194 RK3588_CLKGATE_CON(12), 0, GFLAGS), 1195 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, 1196 RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, 1197 RK3588_CLKGATE_CON(12), 1, GFLAGS), 1198 1199 GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, 1200 RK3588_CLKGATE_CON(12), 2, GFLAGS), 1201 GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, 1202 RK3588_CLKGATE_CON(12), 3, GFLAGS), 1203 GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, 1204 RK3588_CLKGATE_CON(12), 4, GFLAGS), 1205 GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, 1206 RK3588_CLKGATE_CON(12), 5, GFLAGS), 1207 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, 1208 RK3588_CLKGATE_CON(12), 6, GFLAGS), 1209 GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, 1210 RK3588_CLKGATE_CON(12), 7, GFLAGS), 1211 GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, 1212 RK3588_CLKGATE_CON(12), 8, GFLAGS), 1213 GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, 1214 RK3588_CLKGATE_CON(12), 9, GFLAGS), 1215 GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, 1216 RK3588_CLKGATE_CON(12), 10, GFLAGS), 1217 1218 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, 1219 RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, 1220 RK3588_CLKGATE_CON(12), 11, GFLAGS), 1221 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1222 RK3588_CLKSEL_CON(42), 0, 1223 RK3588_CLKGATE_CON(12), 12, GFLAGS, 1224 &rk3588_uart1_fracmux), 1225 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, 1226 RK3588_CLKGATE_CON(12), 13, GFLAGS), 1227 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, 1228 RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, 1229 RK3588_CLKGATE_CON(12), 14, GFLAGS), 1230 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1231 RK3588_CLKSEL_CON(44), 0, 1232 RK3588_CLKGATE_CON(12), 15, GFLAGS, 1233 &rk3588_uart2_fracmux), 1234 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, 1235 RK3588_CLKGATE_CON(13), 0, GFLAGS), 1236 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, 1237 RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, 1238 RK3588_CLKGATE_CON(13), 1, GFLAGS), 1239 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1240 RK3588_CLKSEL_CON(46), 0, 1241 RK3588_CLKGATE_CON(13), 2, GFLAGS, 1242 &rk3588_uart3_fracmux), 1243 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, 1244 RK3588_CLKGATE_CON(13), 3, GFLAGS), 1245 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, 1246 RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, 1247 RK3588_CLKGATE_CON(13), 4, GFLAGS), 1248 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1249 RK3588_CLKSEL_CON(48), 0, 1250 RK3588_CLKGATE_CON(13), 5, GFLAGS, 1251 &rk3588_uart4_fracmux), 1252 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, 1253 RK3588_CLKGATE_CON(13), 6, GFLAGS), 1254 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, 1255 RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, 1256 RK3588_CLKGATE_CON(13), 7, GFLAGS), 1257 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1258 RK3588_CLKSEL_CON(50), 0, 1259 RK3588_CLKGATE_CON(13), 8, GFLAGS, 1260 &rk3588_uart5_fracmux), 1261 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, 1262 RK3588_CLKGATE_CON(13), 9, GFLAGS), 1263 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, 1264 RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, 1265 RK3588_CLKGATE_CON(13), 10, GFLAGS), 1266 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1267 RK3588_CLKSEL_CON(52), 0, 1268 RK3588_CLKGATE_CON(13), 11, GFLAGS, 1269 &rk3588_uart6_fracmux), 1270 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, 1271 RK3588_CLKGATE_CON(13), 12, GFLAGS), 1272 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, 1273 RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, 1274 RK3588_CLKGATE_CON(13), 13, GFLAGS), 1275 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1276 RK3588_CLKSEL_CON(54), 0, 1277 RK3588_CLKGATE_CON(13), 14, GFLAGS, 1278 &rk3588_uart7_fracmux), 1279 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, 1280 RK3588_CLKGATE_CON(13), 15, GFLAGS), 1281 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, 1282 RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, 1283 RK3588_CLKGATE_CON(14), 0, GFLAGS), 1284 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1285 RK3588_CLKSEL_CON(56), 0, 1286 RK3588_CLKGATE_CON(14), 1, GFLAGS, 1287 &rk3588_uart8_fracmux), 1288 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, 1289 RK3588_CLKGATE_CON(14), 2, GFLAGS), 1290 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, 1291 RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, 1292 RK3588_CLKGATE_CON(14), 3, GFLAGS), 1293 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1294 RK3588_CLKSEL_CON(58), 0, 1295 RK3588_CLKGATE_CON(14), 4, GFLAGS, 1296 &rk3588_uart9_fracmux), 1297 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, 1298 RK3588_CLKGATE_CON(14), 5, GFLAGS), 1299 1300 /* center */ 1301 COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, 1302 CLK_IS_CRITICAL, 1303 RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, 1304 RK3588_CLKGATE_CON(69), 0, GFLAGS), 1305 COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, 1306 CLK_IS_CRITICAL, 1307 RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, 1308 RK3588_CLKGATE_CON(69), 1, GFLAGS), 1309 COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, 1310 CLK_IS_CRITICAL, 1311 RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, 1312 RK3588_CLKGATE_CON(69), 2, GFLAGS), 1313 COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, 1314 CLK_IS_CRITICAL, 1315 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 1316 RK3588_CLKGATE_CON(69), 3, GFLAGS), 1317 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, 1318 RK3588_CLKGATE_CON(69), 5, GFLAGS), 1319 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, 1320 RK3588_CLKGATE_CON(69), 6, GFLAGS), 1321 COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, 1322 CLK_IS_CRITICAL, 1323 RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, 1324 RK3588_CLKGATE_CON(69), 8, GFLAGS), 1325 COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, 1326 CLK_IS_CRITICAL, 1327 RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, 1328 RK3588_CLKGATE_CON(69), 9, GFLAGS), 1329 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, 1330 RK3588_CLKGATE_CON(69), 14, GFLAGS), 1331 COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, 1332 RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, 1333 RK3588_CLKGATE_CON(69), 15, GFLAGS), 1334 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, 1335 RK3588_CLKGATE_CON(70), 0, GFLAGS), 1336 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, 1337 RK3588_CLKGATE_CON(70), 1, GFLAGS), 1338 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, 1339 RK3588_CLKGATE_CON(70), 2, GFLAGS), 1340 COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 1341 RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, 1342 RK3588_CLKGATE_CON(70), 4, GFLAGS), 1343 GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, 1344 RK3588_CLKGATE_CON(70), 7, GFLAGS), 1345 GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, 1346 RK3588_CLKGATE_CON(70), 8, GFLAGS), 1347 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, 1348 RK3588_CLKGATE_CON(70), 9, GFLAGS), 1349 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, 1350 RK3588_CLKGATE_CON(70), 10, GFLAGS), 1351 1352 /* gpu */ 1353 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, 1354 RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, 1355 RK3588_CLKGATE_CON(66), 1, GFLAGS), 1356 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, 1357 RK3588_CLKGATE_CON(66), 4, GFLAGS), 1358 GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, 1359 RK3588_CLKGATE_CON(66), 6, GFLAGS), 1360 COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, 1361 RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, 1362 RK3588_CLKGATE_CON(66), 7, GFLAGS), 1363 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 1364 RK3588_CLKGATE_CON(67), 0, GFLAGS), 1365 GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, 1366 RK3588_CLKGATE_CON(67), 1, GFLAGS), 1367 1368 /* isp1 */ 1369 COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, 1370 RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, 1371 RK3588_CLKGATE_CON(26), 0, GFLAGS), 1372 COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, 1373 RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, 1374 RK3588_CLKGATE_CON(26), 1, GFLAGS), 1375 COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, 1376 RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, 1377 RK3588_CLKGATE_CON(26), 2, GFLAGS), 1378 GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, 1379 RK3588_CLKGATE_CON(26), 3, GFLAGS), 1380 GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, 1381 RK3588_CLKGATE_CON(26), 4, GFLAGS), 1382 1383 /* npu */ 1384 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, 1385 RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, 1386 RK3588_CLKGATE_CON(29), 0, GFLAGS), 1387 COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, 1388 RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, 1389 RK3588_CLKGATE_CON(29), 1, GFLAGS), 1390 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, 1391 RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, 1392 RK3588_CLKGATE_CON(29), 4, GFLAGS), 1393 GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, 1394 RK3588_CLKGATE_CON(27), 0, GFLAGS), 1395 GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, 1396 RK3588_CLKGATE_CON(27), 2, GFLAGS), 1397 GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, 1398 RK3588_CLKGATE_CON(28), 0, GFLAGS), 1399 GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, 1400 RK3588_CLKGATE_CON(28), 2, GFLAGS), 1401 COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, 1402 RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, 1403 RK3588_CLKGATE_CON(30), 1, GFLAGS), 1404 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, 1405 RK3588_CLKGATE_CON(30), 3, GFLAGS), 1406 COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, 1407 RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, 1408 RK3588_CLKGATE_CON(30), 5, GFLAGS), 1409 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, 1410 RK3588_CLKGATE_CON(29), 12, GFLAGS), 1411 GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, 1412 RK3588_CLKGATE_CON(29), 13, GFLAGS), 1413 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 1414 RK3588_CLKGATE_CON(29), 14, GFLAGS), 1415 GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, 1416 RK3588_CLKGATE_CON(29), 15, GFLAGS), 1417 GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, 1418 RK3588_CLKGATE_CON(30), 6, GFLAGS), 1419 GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, 1420 RK3588_CLKGATE_CON(30), 8, GFLAGS), 1421 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, 1422 RK3588_CLKGATE_CON(29), 6, GFLAGS), 1423 COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, 1424 RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, 1425 RK3588_CLKGATE_CON(29), 7, GFLAGS), 1426 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, 1427 RK3588_CLKGATE_CON(29), 8, GFLAGS), 1428 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, 1429 RK3588_CLKGATE_CON(29), 9, GFLAGS), 1430 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, 1431 RK3588_CLKGATE_CON(29), 10, GFLAGS), 1432 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, 1433 RK3588_CLKGATE_CON(29), 11, GFLAGS), 1434 1435 /* nvm */ 1436 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, 1437 RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, 1438 RK3588_CLKGATE_CON(31), 0, GFLAGS), 1439 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, 1440 RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, 1441 RK3588_CLKGATE_CON(31), 1, GFLAGS), 1442 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, 1443 RK3588_CLKGATE_CON(31), 5, GFLAGS), 1444 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, 1445 RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, 1446 RK3588_CLKGATE_CON(31), 6, GFLAGS), 1447 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, 1448 RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, 1449 RK3588_CLKGATE_CON(31), 7, GFLAGS), 1450 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, 1451 RK3588_CLKGATE_CON(31), 8, GFLAGS), 1452 1453 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, 1454 RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, 1455 RK3588_CLKGATE_CON(31), 9, GFLAGS), 1456 1457 /* php */ 1458 COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, 1459 RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, 1460 RK3588_CLKGATE_CON(34), 10, GFLAGS), 1461 COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, 1462 RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, 1463 RK3588_CLKGATE_CON(34), 11, GFLAGS), 1464 COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, 1465 RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, 1466 RK3588_CLKGATE_CON(35), 5, GFLAGS), 1467 COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, 1468 RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, 1469 RK3588_CLKGATE_CON(35), 6, GFLAGS), 1470 1471 COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, 1472 RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, 1473 RK3588_CLKGATE_CON(32), 6, GFLAGS), 1474 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, 1475 RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, 1476 RK3588_CLKGATE_CON(32), 7, GFLAGS), 1477 COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, 1478 RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, 1479 RK3588_CLKGATE_CON(32), 0, GFLAGS), 1480 GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, 1481 RK3588_CLKGATE_CON(34), 6, GFLAGS), 1482 GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, 1483 RK3588_CLKGATE_CON(32), 8, GFLAGS), 1484 GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, 1485 RK3588_CLKGATE_CON(34), 7, GFLAGS), 1486 GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, 1487 RK3588_CLKGATE_CON(34), 8, GFLAGS), 1488 GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, 1489 RK3588_CLKGATE_CON(32), 13, GFLAGS), 1490 GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, 1491 RK3588_CLKGATE_CON(32), 14, GFLAGS), 1492 GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, 1493 RK3588_CLKGATE_CON(32), 15, GFLAGS), 1494 GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, 1495 RK3588_CLKGATE_CON(33), 0, GFLAGS), 1496 GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, 1497 RK3588_CLKGATE_CON(33), 1, GFLAGS), 1498 GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, 1499 RK3588_CLKGATE_CON(33), 2, GFLAGS), 1500 GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, 1501 RK3588_CLKGATE_CON(33), 3, GFLAGS), 1502 GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, 1503 RK3588_CLKGATE_CON(33), 4, GFLAGS), 1504 GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, 1505 RK3588_CLKGATE_CON(33), 5, GFLAGS), 1506 GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, 1507 RK3588_CLKGATE_CON(33), 6, GFLAGS), 1508 GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, 1509 RK3588_CLKGATE_CON(33), 7, GFLAGS), 1510 GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, 1511 RK3588_CLKGATE_CON(33), 8, GFLAGS), 1512 GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, 1513 RK3588_CLKGATE_CON(33), 9, GFLAGS), 1514 GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, 1515 RK3588_CLKGATE_CON(33), 10, GFLAGS), 1516 GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, 1517 RK3588_CLKGATE_CON(33), 11, GFLAGS), 1518 GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, 1519 RK3588_CLKGATE_CON(33), 12, GFLAGS), 1520 GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, 1521 RK3588_CLKGATE_CON(33), 13, GFLAGS), 1522 GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, 1523 RK3588_CLKGATE_CON(33), 14, GFLAGS), 1524 GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, 1525 RK3588_CLKGATE_CON(33), 15, GFLAGS), 1526 GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, 1527 RK3588_CLKGATE_CON(34), 0, GFLAGS), 1528 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, 1529 RK3588_CLKGATE_CON(34), 1, GFLAGS), 1530 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, 1531 RK3588_CLKGATE_CON(34), 2, GFLAGS), 1532 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, 1533 RK3588_CLKGATE_CON(34), 3, GFLAGS), 1534 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, 1535 RK3588_CLKGATE_CON(34), 4, GFLAGS), 1536 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, 1537 RK3588_CLKGATE_CON(34), 5, GFLAGS), 1538 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, 1539 RK3588_CLKGATE_CON(37), 0, GFLAGS), 1540 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, 1541 RK3588_CLKGATE_CON(37), 1, GFLAGS), 1542 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, 1543 RK3588_CLKGATE_CON(37), 2, GFLAGS), 1544 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, 1545 RK3588_CLKGATE_CON(32), 3, GFLAGS), 1546 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, 1547 RK3588_CLKGATE_CON(32), 4, GFLAGS), 1548 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, 1549 RK3588_CLKGATE_CON(32), 10, GFLAGS), 1550 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, 1551 RK3588_CLKGATE_CON(32), 11, GFLAGS), 1552 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, 1553 RK3588_CLKGATE_CON(37), 4, GFLAGS), 1554 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, 1555 RK3588_CLKGATE_CON(37), 5, GFLAGS), 1556 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, 1557 RK3588_CLKGATE_CON(37), 6, GFLAGS), 1558 GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, 1559 RK3588_CLKGATE_CON(37), 7, GFLAGS), 1560 GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, 1561 RK3588_CLKGATE_CON(37), 8, GFLAGS), 1562 GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, 1563 RK3588_CLKGATE_CON(37), 9, GFLAGS), 1564 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, 1565 RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, 1566 RK3588_CLKGATE_CON(37), 10, GFLAGS), 1567 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, 1568 RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, 1569 RK3588_CLKGATE_CON(37), 11, GFLAGS), 1570 COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, 1571 RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, 1572 RK3588_CLKGATE_CON(37), 12, GFLAGS), 1573 GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, 1574 RK3588_CLKGATE_CON(35), 7, GFLAGS), 1575 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, 1576 RK3588_CLKGATE_CON(35), 8, GFLAGS), 1577 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, 1578 RK3588_CLKGATE_CON(35), 9, GFLAGS), 1579 COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, 1580 RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, 1581 RK3588_CLKGATE_CON(35), 10, GFLAGS), 1582 GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, 1583 RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), 1584 GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, 1585 RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), 1586 GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, 1587 RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), 1588 GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, 1589 RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), 1590 1591 /* rga */ 1592 COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, 1593 RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, 1594 RK3588_CLKGATE_CON(76), 6, GFLAGS), 1595 COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, 1596 RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, 1597 RK3588_CLKGATE_CON(76), 0, GFLAGS), 1598 COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, 1599 RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, 1600 RK3588_CLKGATE_CON(76), 1, GFLAGS), 1601 GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, 1602 RK3588_CLKGATE_CON(76), 4, GFLAGS), 1603 GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, 1604 RK3588_CLKGATE_CON(76), 5, GFLAGS), 1605 1606 /* vdec */ 1607 COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, 1608 RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, 1609 RK3588_CLKGATE_CON(40), 0, GFLAGS), 1610 COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, 1611 RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, 1612 RK3588_CLKGATE_CON(40), 1, GFLAGS), 1613 COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, 1614 RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, 1615 RK3588_CLKGATE_CON(40), 2, GFLAGS), 1616 COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, 1617 RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, 1618 RK3588_CLKGATE_CON(40), 7, GFLAGS), 1619 COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1620 RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, 1621 RK3588_CLKGATE_CON(40), 8, GFLAGS), 1622 COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, 1623 RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, 1624 RK3588_CLKGATE_CON(40), 9, GFLAGS), 1625 COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, 1626 RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, 1627 RK3588_CLKGATE_CON(41), 0, GFLAGS), 1628 COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, 1629 RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, 1630 RK3588_CLKGATE_CON(41), 1, GFLAGS), 1631 COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, 1632 RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, 1633 RK3588_CLKGATE_CON(41), 6, GFLAGS), 1634 COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1635 RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, 1636 RK3588_CLKGATE_CON(41), 7, GFLAGS), 1637 COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, 1638 RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, 1639 RK3588_CLKGATE_CON(41), 8, GFLAGS), 1640 1641 /* sdio */ 1642 COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, 1643 RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, 1644 RK3588_CLKGATE_CON(75), 0, GFLAGS), 1645 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, 1646 RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, 1647 RK3588_CLKGATE_CON(75), 3, GFLAGS), 1648 MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), 1649 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), 1650 1651 /* usb */ 1652 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, 1653 RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, 1654 RK3588_CLKGATE_CON(42), 0, GFLAGS), 1655 COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, 1656 RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, 1657 RK3588_CLKGATE_CON(42), 1, GFLAGS), 1658 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, 1659 RK3588_CLKGATE_CON(42), 5, GFLAGS), 1660 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, 1661 RK3588_CLKGATE_CON(42), 6, GFLAGS), 1662 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, 1663 RK3588_CLKGATE_CON(42), 8, GFLAGS), 1664 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, 1665 RK3588_CLKGATE_CON(42), 9, GFLAGS), 1666 1667 /* vdpu */ 1668 COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, 1669 RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, 1670 RK3588_CLKGATE_CON(44), 0, GFLAGS), 1671 COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, 1672 RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, 1673 RK3588_CLKGATE_CON(44), 1, GFLAGS), 1674 COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, 1675 RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, 1676 RK3588_CLKGATE_CON(44), 2, GFLAGS), 1677 COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, 1678 RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, 1679 RK3588_CLKGATE_CON(44), 3, GFLAGS), 1680 GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, 1681 RK3588_CLKGATE_CON(45), 4, GFLAGS), 1682 COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, 1683 RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, 1684 RK3588_CLKGATE_CON(45), 6, GFLAGS), 1685 GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, 1686 RK3588_CLKGATE_CON(44), 11, GFLAGS), 1687 GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, 1688 RK3588_CLKGATE_CON(44), 13, GFLAGS), 1689 GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, 1690 RK3588_CLKGATE_CON(44), 15, GFLAGS), 1691 GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, 1692 RK3588_CLKGATE_CON(45), 1, GFLAGS), 1693 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, 1694 RK3588_CLKGATE_CON(45), 3, GFLAGS), 1695 GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, 1696 RK3588_CLKGATE_CON(45), 7, GFLAGS), 1697 GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, 1698 RK3588_CLKGATE_CON(45), 8, GFLAGS), 1699 COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, 1700 RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, 1701 RK3588_CLKGATE_CON(45), 9, GFLAGS), 1702 GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, 1703 RK3588_CLKGATE_CON(45), 10, GFLAGS), 1704 GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, 1705 RK3588_CLKGATE_CON(45), 11, GFLAGS), 1706 COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, 1707 RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, 1708 RK3588_CLKGATE_CON(45), 12, GFLAGS), 1709 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, 1710 RK3588_CLKGATE_CON(44), 9, GFLAGS), 1711 1712 /* venc */ 1713 COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, 1714 RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, 1715 RK3588_CLKGATE_CON(48), 0, GFLAGS), 1716 COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, 1717 RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, 1718 RK3588_CLKGATE_CON(48), 1, GFLAGS), 1719 COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, 1720 RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, 1721 RK3588_CLKGATE_CON(47), 0, GFLAGS), 1722 COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, 1723 RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, 1724 RK3588_CLKGATE_CON(47), 1, GFLAGS), 1725 GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, 1726 RK3588_CLKGATE_CON(47), 4, GFLAGS), 1727 GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, 1728 RK3588_CLKGATE_CON(47), 5, GFLAGS), 1729 COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, 1730 RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, 1731 RK3588_CLKGATE_CON(47), 6, GFLAGS), 1732 COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, 1733 RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, 1734 RK3588_CLKGATE_CON(48), 6, GFLAGS), 1735 1736 /* vi */ 1737 COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, 1738 RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, 1739 RK3588_CLKGATE_CON(49), 0, GFLAGS), 1740 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, 1741 RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, 1742 RK3588_CLKGATE_CON(49), 1, GFLAGS), 1743 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, 1744 RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, 1745 RK3588_CLKGATE_CON(49), 2, GFLAGS), 1746 COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, 1747 RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, 1748 RK3588_CLKGATE_CON(51), 10, GFLAGS), 1749 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, 1750 RK3588_CLKGATE_CON(51), 11, GFLAGS), 1751 GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, 1752 RK3588_CLKGATE_CON(51), 12, GFLAGS), 1753 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, 1754 RK3588_CLKGATE_CON(50), 4, GFLAGS), 1755 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, 1756 RK3588_CLKGATE_CON(50), 5, GFLAGS), 1757 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, 1758 RK3588_CLKGATE_CON(50), 6, GFLAGS), 1759 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, 1760 RK3588_CLKGATE_CON(50), 7, GFLAGS), 1761 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, 1762 RK3588_CLKGATE_CON(50), 8, GFLAGS), 1763 GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, 1764 RK3588_CLKGATE_CON(50), 9, GFLAGS), 1765 GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, 1766 RK3588_CLKGATE_CON(49), 14, GFLAGS), 1767 GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, 1768 RK3588_CLKGATE_CON(49), 15, GFLAGS), 1769 COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, 1770 RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, 1771 RK3588_CLKGATE_CON(50), 0, GFLAGS), 1772 GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, 1773 RK3588_CLKGATE_CON(50), 1, GFLAGS), 1774 GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, 1775 RK3588_CLKGATE_CON(50), 2, GFLAGS), 1776 COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, 1777 RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, 1778 RK3588_CLKGATE_CON(50), 3, GFLAGS), 1779 COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, 1780 RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, 1781 RK3588_CLKGATE_CON(49), 9, GFLAGS), 1782 GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, 1783 RK3588_CLKGATE_CON(49), 10, GFLAGS), 1784 GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, 1785 RK3588_CLKGATE_CON(49), 11, GFLAGS), 1786 GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, 1787 RK3588_CLKGATE_CON(49), 12, GFLAGS), 1788 GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, 1789 RK3588_CLKGATE_CON(49), 13, GFLAGS), 1790 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, 1791 RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, 1792 RK3588_CLKGATE_CON(49), 6, GFLAGS), 1793 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, 1794 RK3588_CLKGATE_CON(49), 7, GFLAGS), 1795 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, 1796 RK3588_CLKGATE_CON(49), 8, GFLAGS), 1797 1798 /* vo0 */ 1799 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, 1800 RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, 1801 RK3588_CLKGATE_CON(55), 0, GFLAGS), 1802 COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, 1803 RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, 1804 RK3588_CLKGATE_CON(55), 1, GFLAGS), 1805 COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, 1806 RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, 1807 RK3588_CLKGATE_CON(55), 2, GFLAGS), 1808 COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, 1809 RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, 1810 RK3588_CLKGATE_CON(55), 3, GFLAGS), 1811 COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, 1812 RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, 1813 RK3588_CLKGATE_CON(55), 4, GFLAGS), 1814 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, 1815 RK3588_CLKGATE_CON(56), 4, GFLAGS), 1816 GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, 1817 RK3588_CLKGATE_CON(56), 5, GFLAGS), 1818 GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, 1819 RK3588_CLKGATE_CON(56), 6, GFLAGS), 1820 GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, 1821 RK3588_CLKGATE_CON(56), 7, GFLAGS), 1822 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, 1823 RK3588_CLKGATE_CON(56), 8, GFLAGS), 1824 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, 1825 RK3588_CLKGATE_CON(56), 9, GFLAGS), 1826 GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, 1827 RK3588_CLKGATE_CON(55), 11, GFLAGS), 1828 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, 1829 RK3588_CLKGATE_CON(55), 14, GFLAGS), 1830 GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, 1831 RK3588_CLKGATE_CON(56), 0, GFLAGS), 1832 GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, 1833 RK3588_CLKGATE_CON(56), 1, GFLAGS), 1834 COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, 1835 RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, 1836 RK3588_CLKGATE_CON(56), 11, GFLAGS), 1837 COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", 1838 CLK_SET_RATE_PARENT, 1839 RK3588_CLKSEL_CON(119), 0, 1840 RK3588_CLKGATE_CON(56), 12, GFLAGS, 1841 &rk3588_i2s4_8ch_tx_fracmux), 1842 GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, 1843 RK3588_CLKGATE_CON(56), 13, GFLAGS), 1844 COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, 1845 RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, 1846 RK3588_CLKGATE_CON(56), 15, GFLAGS), 1847 COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", 1848 CLK_SET_RATE_PARENT, 1849 RK3588_CLKSEL_CON(121), 0, 1850 RK3588_CLKGATE_CON(57), 0, GFLAGS, 1851 &rk3588_i2s8_8ch_tx_fracmux), 1852 GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, 1853 RK3588_CLKGATE_CON(57), 1, GFLAGS), 1854 COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, 1855 RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, 1856 RK3588_CLKGATE_CON(57), 3, GFLAGS), 1857 COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", 1858 CLK_SET_RATE_PARENT, 1859 RK3588_CLKSEL_CON(123), 0, 1860 RK3588_CLKGATE_CON(57), 4, GFLAGS, 1861 &rk3588_spdif2_dp0_fracmux), 1862 GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, 1863 RK3588_CLKGATE_CON(57), 5, GFLAGS), 1864 GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, 1865 RK3588_CLKGATE_CON(57), 6, GFLAGS), 1866 COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, 1867 RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, 1868 RK3588_CLKGATE_CON(57), 8, GFLAGS), 1869 COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", 1870 CLK_SET_RATE_PARENT, 1871 RK3588_CLKSEL_CON(125), 0, 1872 RK3588_CLKGATE_CON(57), 9, GFLAGS, 1873 &rk3588_spdif5_dp1_fracmux), 1874 GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, 1875 RK3588_CLKGATE_CON(57), 10, GFLAGS), 1876 GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, 1877 RK3588_CLKGATE_CON(57), 11, GFLAGS), 1878 COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, 1879 RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, 1880 RK3588_CLKGATE_CON(56), 2, GFLAGS), 1881 COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, 1882 RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, 1883 RK3588_CLKGATE_CON(56), 3, GFLAGS), 1884 1885 /* vo1 */ 1886 COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, 1887 RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, 1888 RK3588_CLKGATE_CON(65), 9, GFLAGS), 1889 COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, 1890 RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, 1891 RK3588_CLKGATE_CON(59), 0, GFLAGS), 1892 COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, 1893 RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, 1894 RK3588_CLKGATE_CON(59), 1, GFLAGS), 1895 COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, 1896 RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, 1897 RK3588_CLKGATE_CON(59), 2, GFLAGS), 1898 COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, 1899 RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, 1900 RK3588_CLKGATE_CON(59), 3, GFLAGS), 1901 COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, 1902 RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, 1903 RK3588_CLKGATE_CON(59), 4, GFLAGS), 1904 COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, 1905 RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, 1906 RK3588_CLKGATE_CON(59), 5, GFLAGS), 1907 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, 1908 RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, 1909 RK3588_CLKGATE_CON(52), 0, GFLAGS), 1910 COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, 1911 RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, 1912 RK3588_CLKGATE_CON(52), 1, GFLAGS), 1913 COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, 1914 RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, 1915 RK3588_CLKGATE_CON(52), 2, GFLAGS), 1916 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, 1917 RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, 1918 RK3588_CLKGATE_CON(52), 3, GFLAGS), 1919 COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 1920 RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, 1921 RK3588_CLKGATE_CON(74), 0, GFLAGS), 1922 COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 1923 RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, 1924 RK3588_CLKGATE_CON(74), 2, GFLAGS), 1925 MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, 1926 RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), 1927 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, 1928 RK3588_CLKGATE_CON(62), 0, GFLAGS), 1929 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, 1930 RK3588_CLKGATE_CON(62), 1, GFLAGS), 1931 COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, 1932 RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, 1933 RK3588_CLKGATE_CON(62), 2, GFLAGS), 1934 GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, 1935 RK3588_CLKGATE_CON(62), 3, GFLAGS), 1936 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, 1937 RK3588_CLKGATE_CON(62), 4, GFLAGS), 1938 COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, 1939 RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, 1940 RK3588_CLKGATE_CON(62), 5, GFLAGS), 1941 GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, 1942 RK3588_CLKGATE_CON(60), 4, GFLAGS), 1943 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, 1944 RK3588_CLKGATE_CON(60), 7, GFLAGS), 1945 GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, 1946 RK3588_CLKGATE_CON(61), 9, GFLAGS), 1947 GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, 1948 RK3588_CLKGATE_CON(61), 10, GFLAGS), 1949 GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, 1950 RK3588_CLKGATE_CON(61), 11, GFLAGS), 1951 COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, 1952 RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, 1953 RK3588_CLKGATE_CON(61), 12, GFLAGS), 1954 COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", 1955 CLK_SET_RATE_PARENT, 1956 RK3588_CLKSEL_CON(139), 0, 1957 RK3588_CLKGATE_CON(61), 13, GFLAGS, 1958 &rk3588_hdmirx_aud_fracmux), 1959 GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, 1960 RK3588_CLKGATE_CON(61), 14, GFLAGS), 1961 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, 1962 RK3588_CLKGATE_CON(60), 11, GFLAGS), 1963 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, 1964 RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, 1965 RK3588_CLKGATE_CON(60), 15, GFLAGS), 1966 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, 1967 RK3588_CLKGATE_CON(61), 0, GFLAGS), 1968 GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, 1969 RK3588_CLKGATE_CON(61), 2, GFLAGS), 1970 COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, 1971 RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, 1972 RK3588_CLKGATE_CON(61), 6, GFLAGS), 1973 GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, 1974 RK3588_CLKGATE_CON(61), 7, GFLAGS), 1975 GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, 1976 RK3588_CLKGATE_CON(60), 9, GFLAGS), 1977 GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, 1978 RK3588_CLKGATE_CON(60), 10, GFLAGS), 1979 GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, 1980 RK3588_CLKGATE_CON(59), 14, GFLAGS), 1981 GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, 1982 RK3588_CLKGATE_CON(59), 15, GFLAGS), 1983 GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, 1984 RK3588_CLKGATE_CON(65), 8, GFLAGS), 1985 COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, 1986 RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, 1987 RK3588_CLKGATE_CON(65), 5, GFLAGS), 1988 COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", 1989 CLK_SET_RATE_PARENT, 1990 RK3588_CLKSEL_CON(156), 0, 1991 RK3588_CLKGATE_CON(65), 6, GFLAGS, 1992 &rk3588_i2s10_8ch_rx_fracmux), 1993 GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, 1994 RK3588_CLKGATE_CON(65), 7, GFLAGS), 1995 COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, 1996 RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, 1997 RK3588_CLKGATE_CON(60), 1, GFLAGS), 1998 COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", 1999 CLK_SET_RATE_PARENT, 2000 RK3588_CLKSEL_CON(130), 0, 2001 RK3588_CLKGATE_CON(60), 2, GFLAGS, 2002 &rk3588_i2s7_8ch_rx_fracmux), 2003 GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, 2004 RK3588_CLKGATE_CON(60), 3, GFLAGS), 2005 COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, 2006 RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, 2007 RK3588_CLKGATE_CON(65), 1, GFLAGS), 2008 COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", 2009 CLK_SET_RATE_PARENT, 2010 RK3588_CLKSEL_CON(154), 0, 2011 RK3588_CLKGATE_CON(65), 2, GFLAGS, 2012 &rk3588_i2s9_8ch_rx_fracmux), 2013 GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, 2014 RK3588_CLKGATE_CON(65), 3, GFLAGS), 2015 COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, 2016 RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, 2017 RK3588_CLKGATE_CON(62), 6, GFLAGS), 2018 COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, 2019 RK3588_CLKSEL_CON(141), 0, 2020 RK3588_CLKGATE_CON(62), 7, GFLAGS, 2021 &rk3588_i2s5_8ch_tx_fracmux), 2022 GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, 2023 RK3588_CLKGATE_CON(62), 8, GFLAGS), 2024 COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, 2025 RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, 2026 RK3588_CLKGATE_CON(62), 13, GFLAGS), 2027 COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", 2028 CLK_SET_RATE_PARENT, 2029 RK3588_CLKSEL_CON(145), 0, 2030 RK3588_CLKGATE_CON(62), 14, GFLAGS, 2031 &rk3588_i2s6_8ch_tx_fracmux), 2032 GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, 2033 RK3588_CLKGATE_CON(62), 15, GFLAGS), 2034 COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, 2035 RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, 2036 RK3588_CLKGATE_CON(63), 0, GFLAGS), 2037 COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, 2038 RK3588_CLKSEL_CON(147), 0, 2039 RK3588_CLKGATE_CON(63), 1, GFLAGS, 2040 &rk3588_i2s6_8ch_rx_fracmux), 2041 GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, 2042 RK3588_CLKGATE_CON(63), 2, GFLAGS), 2043 MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2044 RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), 2045 COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, 2046 RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, 2047 RK3588_CLKGATE_CON(63), 5, GFLAGS), 2048 COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", 2049 CLK_SET_RATE_PARENT, 2050 RK3588_CLKSEL_CON(149), 0, 2051 RK3588_CLKGATE_CON(63), 6, GFLAGS, 2052 &rk3588_spdif3_fracmux), 2053 GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, 2054 RK3588_CLKGATE_CON(63), 7, GFLAGS), 2055 COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, 2056 RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, 2057 RK3588_CLKGATE_CON(63), 9, GFLAGS), 2058 COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", 2059 CLK_SET_RATE_PARENT, 2060 RK3588_CLKSEL_CON(151), 0, 2061 RK3588_CLKGATE_CON(63), 10, GFLAGS, 2062 &rk3588_spdif4_fracmux), 2063 GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, 2064 RK3588_CLKGATE_CON(63), 11, GFLAGS), 2065 COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, 2066 RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, 2067 RK3588_CLKGATE_CON(63), 13, GFLAGS), 2068 COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, 2069 RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, 2070 RK3588_CLKGATE_CON(63), 15, GFLAGS), 2071 COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, 2072 RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, 2073 RK3588_CLKGATE_CON(64), 1, GFLAGS), 2074 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, 2075 RK3588_CLKGATE_CON(73), 12, GFLAGS), 2076 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, 2077 RK3588_CLKGATE_CON(73), 13, GFLAGS), 2078 GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, 2079 RK3588_CLKGATE_CON(72), 5, GFLAGS), 2080 GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, 2081 RK3588_CLKGATE_CON(72), 6, GFLAGS), 2082 GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, 2083 RK3588_CLKGATE_CON(72), 2, GFLAGS), 2084 GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, 2085 RK3588_CLKGATE_CON(72), 4, GFLAGS), 2086 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, 2087 RK3588_CLKGATE_CON(52), 8, GFLAGS), 2088 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, 2089 RK3588_CLKGATE_CON(52), 9, GFLAGS), 2090 COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, 2091 RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, 2092 RK3588_CLKGATE_CON(52), 10, GFLAGS), 2093 COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, 2094 RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, 2095 RK3588_CLKGATE_CON(52), 11, GFLAGS), 2096 COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2097 RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, 2098 RK3588_CLKGATE_CON(52), 12, GFLAGS), 2099 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 2100 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2101 RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, 2102 RK3588_CLKGATE_CON(52), 13, GFLAGS), 2103 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 2104 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2105 RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, 2106 RK3588_CLKGATE_CON(53), 0, GFLAGS), 2107 COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, 2108 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2109 RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, 2110 RK3588_CLKGATE_CON(53), 1, GFLAGS), 2111 COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, 2112 RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, 2113 RK3588_CLKGATE_CON(53), 2, GFLAGS), 2114 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, 2115 RK3588_CLKGATE_CON(53), 4, GFLAGS), 2116 GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, 2117 RK3588_CLKGATE_CON(53), 5, GFLAGS), 2118 COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, 2119 RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, 2120 RK3588_CLKGATE_CON(53), 6, GFLAGS), 2121 COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, 2122 RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, 2123 RK3588_CLKGATE_CON(53), 7, GFLAGS), 2124 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, 2125 RK3588_CLKGATE_CON(53), 8, GFLAGS), 2126 GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, 2127 RK3588_CLKGATE_CON(53), 10, GFLAGS), 2128 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, 2129 RK3588_CLKGATE_CON(2), 8, GFLAGS), 2130 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, 2131 RK3588_CLKGATE_CON(2), 15, GFLAGS), 2132 2133 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, 2134 RK3588_CLKGATE_CON(77), 0, GFLAGS), 2135 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, 2136 RK3588_CLKGATE_CON(77), 1, GFLAGS), 2137 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, 2138 RK3588_CLKGATE_CON(77), 2, GFLAGS), 2139 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, 2140 RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, 2141 RK3588_CLKGATE_CON(77), 3, GFLAGS), 2142 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, 2143 RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, 2144 RK3588_CLKGATE_CON(77), 4, GFLAGS), 2145 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, 2146 RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, 2147 RK3588_CLKGATE_CON(77), 5, GFLAGS), 2148 MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, 2149 RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), 2150 MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, 2151 RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), 2152 MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, 2153 RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), 2154 2155 /* pmu */ 2156 COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, 2157 RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, 2158 RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), 2159 COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, 2160 RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 2161 RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), 2162 COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, 2163 RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, 2164 RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), 2165 COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, 2166 RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, 2167 RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), 2168 COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, 2169 RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, 2170 RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), 2171 COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, 2172 RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 2173 RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), 2174 COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, 2175 RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, 2176 RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), 2177 GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, 2178 RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), 2179 COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, 2180 RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, 2181 RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), 2182 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, 2183 RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), 2184 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, 2185 RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), 2186 GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, 2187 RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), 2188 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, 2189 RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), 2190 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, 2191 RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, 2192 RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), 2193 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, 2194 RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), 2195 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, 2196 RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, 2197 RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), 2198 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, 2199 RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), 2200 COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, 2201 RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, 2202 RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), 2203 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", 2204 CLK_SET_RATE_PARENT, 2205 RK3588_PMU_CLKSEL_CON(6), 0, 2206 RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, 2207 &rk3588_i2s1_8ch_tx_fracmux), 2208 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 2209 RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), 2210 COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, 2211 RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, 2212 RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), 2213 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", 2214 CLK_SET_RATE_PARENT, 2215 RK3588_PMU_CLKSEL_CON(8), 0, 2216 RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, 2217 &rk3588_i2s1_8ch_rx_fracmux), 2218 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 2219 RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), 2220 MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2221 RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), 2222 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, 2223 RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), 2224 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, 2225 RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), 2226 GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, 2227 RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), 2228 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, 2229 RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), 2230 COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, 2231 RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, 2232 RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), 2233 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, 2234 RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), 2235 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, 2236 RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), 2237 COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 2238 RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 2239 RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), 2240 GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, 2241 RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), 2242 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, 2243 RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), 2244 COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, 2245 RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, 2246 RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), 2247 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, 2248 RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), 2249 GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, 2250 RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), 2251 COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, 2252 RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, 2253 RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), 2254 GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, 2255 RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), 2256 GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, 2257 RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), 2258 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, 2259 RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, 2260 RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), 2261 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, 2262 RK3588_PMU_CLKSEL_CON(4), 0, 2263 RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, 2264 &rk3588_uart0_fracmux), 2265 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, 2266 RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), 2267 GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, 2268 RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), 2269 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, 2270 RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), 2271 COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, 2272 RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 2273 RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), 2274 COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, 2275 RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, 2276 RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), 2277 COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, 2278 CLK_IS_CRITICAL, 2279 RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, 2280 RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), 2281 COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, 2282 CLK_IS_CRITICAL, 2283 RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, 2284 RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), 2285 2286 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, 2287 RK3588_PHYREF_ALT_GATE, 0, GFLAGS), 2288 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, 2289 RK3588_PHYREF_ALT_GATE, 1, GFLAGS), 2290 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, 2291 RK3588_PHYREF_ALT_GATE, 2, GFLAGS), 2292 GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, 2293 RK3588_PHYREF_ALT_GATE, 3, GFLAGS), 2294 2295 GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, 2296 RK3588_CLKGATE_CON(63), 12, GFLAGS), 2297 GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, 2298 RK3588_CLKGATE_CON(63), 14, GFLAGS), 2299 GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, 2300 RK3588_CLKGATE_CON(64), 0, GFLAGS), 2301 GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, 2302 RK3588_CLKGATE_CON(63), 8, GFLAGS), 2303 GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, 2304 RK3588_CLKGATE_CON(63), 4, GFLAGS), 2305 GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, 2306 RK3588_CLKGATE_CON(63), 3, GFLAGS), 2307 GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, 2308 RK3588_CLKGATE_CON(62), 12, GFLAGS), 2309 GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, 2310 RK3588_CLKGATE_CON(65), 0, GFLAGS), 2311 GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, 2312 RK3588_CLKGATE_CON(60), 0, GFLAGS), 2313 GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, 2314 RK3588_CLKGATE_CON(65), 4, GFLAGS), 2315 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, 2316 RK3588_CLKGATE_CON(60), 5, GFLAGS), 2317 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, 2318 RK3588_CLKGATE_CON(60), 6, GFLAGS), 2319 GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, 2320 RK3588_CLKGATE_CON(57), 7, GFLAGS), 2321 GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, 2322 RK3588_CLKGATE_CON(57), 2, GFLAGS), 2323 GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, 2324 RK3588_CLKGATE_CON(56), 14, GFLAGS), 2325 GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, 2326 RK3588_CLKGATE_CON(56), 10, GFLAGS), 2327 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, 2328 RK3588_CLKGATE_CON(55), 12, GFLAGS), 2329 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, 2330 RK3588_CLKGATE_CON(55), 13, GFLAGS), 2331 GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, 2332 RK3588_CLKGATE_CON(48), 4, GFLAGS), 2333 GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, 2334 RK3588_CLKGATE_CON(48), 5, GFLAGS), 2335 GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, 2336 RK3588_CLKGATE_CON(44), 8, GFLAGS), 2337 GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, 2338 RK3588_CLKGATE_CON(45), 5, GFLAGS), 2339 GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, 2340 RK3588_CLKGATE_CON(44), 10, GFLAGS), 2341 GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, 2342 RK3588_CLKGATE_CON(44), 12, GFLAGS), 2343 GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, 2344 RK3588_CLKGATE_CON(44), 14, GFLAGS), 2345 GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, 2346 RK3588_CLKGATE_CON(45), 0, GFLAGS), 2347 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, 2348 RK3588_CLKGATE_CON(45), 2, GFLAGS), 2349 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, 2350 RK3588_CLKGATE_CON(42), 7, GFLAGS), 2351 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, 2352 RK3588_CLKGATE_CON(42), 10, GFLAGS), 2353 GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, 2354 RK3588_CLKGATE_CON(42), 11, GFLAGS), 2355 GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, 2356 RK3588_CLKGATE_CON(42), 12, GFLAGS), 2357 GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, 2358 RK3588_CLKGATE_CON(42), 13, GFLAGS), 2359 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, 2360 RK3588_CLKGATE_CON(42), 4, GFLAGS), 2361 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), 2362 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), 2363 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, 2364 RK3588_CLKGATE_CON(75), 2, GFLAGS), 2365 GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, 2366 RK3588_CLKGATE_CON(41), 2, GFLAGS), 2367 GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, 2368 RK3588_CLKGATE_CON(41), 3, GFLAGS), 2369 GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, 2370 RK3588_CLKGATE_CON(40), 3, GFLAGS), 2371 GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, 2372 RK3588_CLKGATE_CON(40), 4, GFLAGS), 2373 GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, 2374 RK3588_CLKGATE_CON(39), 0, GFLAGS), 2375 GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, 2376 RK3588_CLKGATE_CON(39), 1, GFLAGS), 2377 GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, 2378 RK3588_CLKGATE_CON(38), 3, GFLAGS), 2379 GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, 2380 RK3588_CLKGATE_CON(38), 4, GFLAGS), 2381 GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, 2382 RK3588_CLKGATE_CON(38), 5, GFLAGS), 2383 GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, 2384 RK3588_CLKGATE_CON(38), 6, GFLAGS), 2385 GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, 2386 RK3588_CLKGATE_CON(38), 7, GFLAGS), 2387 GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, 2388 RK3588_CLKGATE_CON(38), 8, GFLAGS), 2389 GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, 2390 RK3588_CLKGATE_CON(38), 9, GFLAGS), 2391 GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, 2392 RK3588_CLKGATE_CON(38), 13, GFLAGS), 2393 GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, 2394 RK3588_CLKGATE_CON(38), 14, GFLAGS), 2395 GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, 2396 RK3588_CLKGATE_CON(38), 15, GFLAGS), 2397 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, 2398 RK3588_CLKGATE_CON(31), 10, GFLAGS), 2399 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, 2400 RK3588_CLKGATE_CON(31), 11, GFLAGS), 2401 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, 2402 RK3588_CLKGATE_CON(31), 4, GFLAGS), 2403 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, 2404 RK3588_CLKGATE_CON(26), 5, GFLAGS), 2405 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, 2406 RK3588_CLKGATE_CON(26), 7, GFLAGS), 2407 GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, 2408 RK3588_CLKGATE_CON(68), 5, GFLAGS), 2409 GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, 2410 RK3588_CLKGATE_CON(68), 2, GFLAGS), 2411 }; 2412 2413 static struct rockchip_clk_branch rk3588_clk_branches[] = { 2414 GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), 2415 GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), 2416 GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), 2417 GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), 2418 GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), 2419 GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), 2420 GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), 2421 GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), 2422 GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), 2423 GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), 2424 GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), 2425 GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), 2426 GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), 2427 GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), 2428 GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), 2429 GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), 2430 GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), 2431 GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), 2432 GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), 2433 GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), 2434 GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), 2435 GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), 2436 }; 2437 2438 static void __init rk3588_clk_early_init(struct device_node *np) 2439 { 2440 struct rockchip_clk_provider *ctx; 2441 unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; 2442 void __iomem *reg_base; 2443 2444 max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches, 2445 ARRAY_SIZE(rk3588_clk_branches)); 2446 max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches, 2447 ARRAY_SIZE(rk3588_early_clk_branches)); 2448 clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1; 2449 2450 reg_base = of_iomap(np, 0); 2451 if (!reg_base) { 2452 pr_err("%s: could not map cru region\n", __func__); 2453 return; 2454 } 2455 2456 ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks); 2457 if (IS_ERR(ctx)) { 2458 pr_err("%s: rockchip clk init failed\n", __func__); 2459 iounmap(reg_base); 2460 return; 2461 } 2462 early_ctx = ctx; 2463 2464 rockchip_clk_register_plls(ctx, rk3588_pll_clks, 2465 ARRAY_SIZE(rk3588_pll_clks), 2466 RK3588_GRF_SOC_STATUS0); 2467 2468 rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", 2469 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 2470 &rk3588_cpulclk_data, rk3588_cpulclk_rates, 2471 ARRAY_SIZE(rk3588_cpulclk_rates)); 2472 rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", 2473 mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), 2474 &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, 2475 ARRAY_SIZE(rk3588_cpub0clk_rates)); 2476 rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", 2477 mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), 2478 &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, 2479 ARRAY_SIZE(rk3588_cpub1clk_rates)); 2480 2481 rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, 2482 ARRAY_SIZE(rk3588_early_clk_branches)); 2483 2484 rockchip_clk_of_add_provider(np, ctx); 2485 } 2486 CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init); 2487 2488 static int clk_rk3588_probe(struct platform_device *pdev) 2489 { 2490 struct rockchip_clk_provider *ctx = early_ctx; 2491 struct device *dev = &pdev->dev; 2492 struct device_node *np = dev->of_node; 2493 2494 rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches, 2495 ARRAY_SIZE(rk3588_clk_branches)); 2496 2497 rockchip_clk_finalize(ctx); 2498 2499 rk3588_rst_init(np, ctx->reg_base); 2500 rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); 2501 2502 /* 2503 * Re-add clock provider, so that the newly added clocks are also 2504 * re-parented and get their defaults configured. 2505 */ 2506 of_clk_del_provider(np); 2507 rockchip_clk_of_add_provider(np, ctx); 2508 2509 return 0; 2510 } 2511 2512 static const struct of_device_id clk_rk3588_match_table[] = { 2513 { 2514 .compatible = "rockchip,rk3588-cru", 2515 }, 2516 { } 2517 }; 2518 2519 static struct platform_driver clk_rk3588_driver = { 2520 .probe = clk_rk3588_probe, 2521 .driver = { 2522 .name = "clk-rk3588", 2523 .of_match_table = clk_rk3588_match_table, 2524 .suppress_bind_attrs = true, 2525 }, 2526 }; 2527 2528 static int __init rockchip_clk_rk3588_drv_register(void) 2529 { 2530 return platform_driver_register(&clk_rk3588_driver); 2531 } 2532 core_initcall(rockchip_clk_rk3588_drv_register); 2533