1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/platform_device.h> 11 #include <linux/syscore_ops.h> 12 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 13 #include "clk.h" 14 15 /* 16 * Recent Rockchip SoCs have a new hardware block called Native Interface 17 * Unit (NIU), which gates clocks to devices behind them. These effectively 18 * need two parent clocks. 19 * 20 * Downstream enables the linked clock via runtime PM whenever the gate is 21 * enabled. This implementation uses separate clock nodes for each of the 22 * linked gate clocks, which leaks parts of the clock tree into DT. 23 * 24 * The GATE_LINK macro instead takes the second parent via 'linkname', but 25 * ignores the information. Once the clock framework is ready to handle it, the 26 * information should be passed on here. But since these clocks are required to 27 * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked 28 * clocks critical until a better solution is available. This will waste some 29 * power, but avoids leaking implementation details into DT or hanging the 30 * system. 31 */ 32 #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ 33 GATE(_id, cname, pname, f, o, b, gf) 34 #define RK3588_LINKED_CLK CLK_IS_CRITICAL 35 36 37 #define RK3588_GRF_SOC_STATUS0 0x600 38 #define RK3588_PHYREF_ALT_GATE 0xc38 39 40 enum rk3588_plls { 41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, 42 }; 43 44 static struct rockchip_pll_rate_table rk3588_pll_rates[] = { 45 /* _mhz, _p, _m, _s, _k */ 46 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), 47 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), 48 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), 49 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), 50 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), 51 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), 52 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), 53 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), 54 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), 55 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), 56 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), 57 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), 58 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), 59 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), 60 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), 61 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), 62 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), 63 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), 64 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), 65 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), 66 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), 67 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), 68 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), 69 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), 70 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), 71 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), 72 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), 73 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), 74 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), 75 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), 76 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), 77 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), 78 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), 79 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), 80 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), 81 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), 82 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), 83 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), 84 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), 85 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), 86 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), 87 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), 88 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), 89 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), 90 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), 91 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), 92 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), 93 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), 94 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), 95 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), 96 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), 97 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), 98 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), 99 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), 100 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), 101 RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), 102 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), 103 RK3588_PLL_RATE(900000000, 2, 300, 2, 0), 104 RK3588_PLL_RATE(850000000, 3, 425, 2, 0), 105 RK3588_PLL_RATE(816000000, 2, 272, 2, 0), 106 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), 107 RK3588_PLL_RATE(786000000, 1, 131, 2, 0), 108 RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), 109 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), 110 RK3588_PLL_RATE(600000000, 2, 200, 2, 0), 111 RK3588_PLL_RATE(594000000, 2, 198, 2, 0), 112 RK3588_PLL_RATE(408000000, 2, 272, 3, 0), 113 RK3588_PLL_RATE(312000000, 2, 208, 3, 0), 114 RK3588_PLL_RATE(216000000, 2, 288, 4, 0), 115 RK3588_PLL_RATE(100000000, 3, 400, 5, 0), 116 RK3588_PLL_RATE(96000000, 2, 256, 5, 0), 117 { /* sentinel */ }, 118 }; 119 120 #define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK 0x3 121 #define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT 13 122 #define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK 0x3 123 #define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT 5 124 #define RK3588_CLK_CORE_B0_GPLL_DIV_MASK 0x1f 125 #define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT 1 126 #define RK3588_CLK_CORE_L_SEL_CLEAN_MASK 0x3 127 #define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT 12 128 #define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT 5 129 #define RK3588_CLK_DSU_SEL_DF_MASK 0x1 130 #define RK3588_CLK_DSU_SEL_DF_SHIFT 15 131 #define RK3588_CLK_DSU_DF_SRC_MASK 0x3 132 #define RK3588_CLK_DSU_DF_SRC_SHIFT 12 133 #define RK3588_CLK_DSU_DF_DIV_MASK 0x1f 134 #define RK3588_CLK_DSU_DF_DIV_SHIFT 7 135 #define RK3588_ACLKM_DSU_DIV_MASK 0x1f 136 #define RK3588_ACLKM_DSU_DIV_SHIFT 1 137 #define RK3588_ACLKS_DSU_DIV_MASK 0x1f 138 #define RK3588_ACLKS_DSU_DIV_SHIFT 6 139 #define RK3588_ACLKMP_DSU_DIV_MASK 0x1f 140 #define RK3588_ACLKMP_DSU_DIV_SHIFT 11 141 #define RK3588_PERIPH_DSU_DIV_MASK 0x1f 142 #define RK3588_PERIPH_DSU_DIV_SHIFT 0 143 #define RK3588_ATCLK_DSU_DIV_MASK 0x1f 144 #define RK3588_ATCLK_DSU_DIV_SHIFT 0 145 #define RK3588_GICCLK_DSU_DIV_MASK 0x1f 146 #define RK3588_GICCLK_DSU_DIV_SHIFT 5 147 148 #define RK3588_CORE_B0_SEL(_apllcore) \ 149 { \ 150 .reg = RK3588_BIGCORE0_CLKSEL_CON(0), \ 151 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 152 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 153 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 154 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 155 } 156 157 #define RK3588_CORE_B1_SEL(_apllcore) \ 158 { \ 159 .reg = RK3588_BIGCORE0_CLKSEL_CON(1), \ 160 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 161 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 162 } 163 164 #define RK3588_CORE_B2_SEL(_apllcore) \ 165 { \ 166 .reg = RK3588_BIGCORE1_CLKSEL_CON(0), \ 167 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \ 168 RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) | \ 169 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \ 170 RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT), \ 171 } 172 173 #define RK3588_CORE_B3_SEL(_apllcore) \ 174 { \ 175 .reg = RK3588_BIGCORE1_CLKSEL_CON(1), \ 176 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \ 177 RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT), \ 178 } 179 180 #define RK3588_CORE_L_SEL0(_offs, _apllcore) \ 181 { \ 182 .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \ 183 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 184 RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) | \ 185 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \ 186 RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT), \ 187 } 188 189 #define RK3588_CORE_L_SEL1(_seldsu, _divdsu) \ 190 { \ 191 .reg = RK3588_DSU_CLKSEL_CON(0), \ 192 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \ 193 RK3588_CLK_DSU_DF_SRC_SHIFT) | \ 194 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \ 195 RK3588_CLK_DSU_DF_DIV_SHIFT), \ 196 } 197 198 #define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks) \ 199 { \ 200 .reg = RK3588_DSU_CLKSEL_CON(1), \ 201 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \ 202 RK3588_ACLKM_DSU_DIV_SHIFT) | \ 203 HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \ 204 RK3588_ACLKMP_DSU_DIV_SHIFT) | \ 205 HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \ 206 RK3588_ACLKS_DSU_DIV_SHIFT), \ 207 } 208 209 #define RK3588_CORE_L_SEL3(_periph) \ 210 { \ 211 .reg = RK3588_DSU_CLKSEL_CON(2), \ 212 .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \ 213 RK3588_PERIPH_DSU_DIV_SHIFT), \ 214 } 215 216 #define RK3588_CORE_L_SEL4(_gicclk, _atclk) \ 217 { \ 218 .reg = RK3588_DSU_CLKSEL_CON(3), \ 219 .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \ 220 RK3588_GICCLK_DSU_DIV_SHIFT) | \ 221 HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \ 222 RK3588_ATCLK_DSU_DIV_SHIFT), \ 223 } 224 225 #define RK3588_CPUB01CLK_RATE(_prate, _apllcore) \ 226 { \ 227 .prate = _prate##U, \ 228 .pre_muxs = { \ 229 RK3588_CORE_B0_SEL(0), \ 230 RK3588_CORE_B1_SEL(0), \ 231 }, \ 232 .post_muxs = { \ 233 RK3588_CORE_B0_SEL(_apllcore), \ 234 RK3588_CORE_B1_SEL(_apllcore), \ 235 }, \ 236 } 237 238 #define RK3588_CPUB23CLK_RATE(_prate, _apllcore) \ 239 { \ 240 .prate = _prate##U, \ 241 .pre_muxs = { \ 242 RK3588_CORE_B2_SEL(0), \ 243 RK3588_CORE_B3_SEL(0), \ 244 }, \ 245 .post_muxs = { \ 246 RK3588_CORE_B2_SEL(_apllcore), \ 247 RK3588_CORE_B3_SEL(_apllcore), \ 248 }, \ 249 } 250 251 #define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \ 252 { \ 253 .prate = _prate##U, \ 254 .pre_muxs = { \ 255 RK3588_CORE_L_SEL0(0, 0), \ 256 RK3588_CORE_L_SEL0(1, 0), \ 257 RK3588_CORE_L_SEL1(3, 2), \ 258 RK3588_CORE_L_SEL2(2, 3, 3), \ 259 RK3588_CORE_L_SEL3(4), \ 260 RK3588_CORE_L_SEL4(4, 4), \ 261 }, \ 262 .post_muxs = { \ 263 RK3588_CORE_L_SEL0(0, _apllcore), \ 264 RK3588_CORE_L_SEL0(1, _apllcore), \ 265 RK3588_CORE_L_SEL1(_seldsu, _divdsu), \ 266 }, \ 267 } 268 269 static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { 270 RK3588_CPUB01CLK_RATE(2496000000, 1), 271 RK3588_CPUB01CLK_RATE(2400000000, 1), 272 RK3588_CPUB01CLK_RATE(2304000000, 1), 273 RK3588_CPUB01CLK_RATE(2208000000, 1), 274 RK3588_CPUB01CLK_RATE(2184000000, 1), 275 RK3588_CPUB01CLK_RATE(2088000000, 1), 276 RK3588_CPUB01CLK_RATE(2040000000, 1), 277 RK3588_CPUB01CLK_RATE(2016000000, 1), 278 RK3588_CPUB01CLK_RATE(1992000000, 1), 279 RK3588_CPUB01CLK_RATE(1896000000, 1), 280 RK3588_CPUB01CLK_RATE(1800000000, 1), 281 RK3588_CPUB01CLK_RATE(1704000000, 0), 282 RK3588_CPUB01CLK_RATE(1608000000, 0), 283 RK3588_CPUB01CLK_RATE(1584000000, 0), 284 RK3588_CPUB01CLK_RATE(1560000000, 0), 285 RK3588_CPUB01CLK_RATE(1536000000, 0), 286 RK3588_CPUB01CLK_RATE(1512000000, 0), 287 RK3588_CPUB01CLK_RATE(1488000000, 0), 288 RK3588_CPUB01CLK_RATE(1464000000, 0), 289 RK3588_CPUB01CLK_RATE(1440000000, 0), 290 RK3588_CPUB01CLK_RATE(1416000000, 0), 291 RK3588_CPUB01CLK_RATE(1392000000, 0), 292 RK3588_CPUB01CLK_RATE(1368000000, 0), 293 RK3588_CPUB01CLK_RATE(1344000000, 0), 294 RK3588_CPUB01CLK_RATE(1320000000, 0), 295 RK3588_CPUB01CLK_RATE(1296000000, 0), 296 RK3588_CPUB01CLK_RATE(1272000000, 0), 297 RK3588_CPUB01CLK_RATE(1248000000, 0), 298 RK3588_CPUB01CLK_RATE(1224000000, 0), 299 RK3588_CPUB01CLK_RATE(1200000000, 0), 300 RK3588_CPUB01CLK_RATE(1104000000, 0), 301 RK3588_CPUB01CLK_RATE(1008000000, 0), 302 RK3588_CPUB01CLK_RATE(912000000, 0), 303 RK3588_CPUB01CLK_RATE(816000000, 0), 304 RK3588_CPUB01CLK_RATE(696000000, 0), 305 RK3588_CPUB01CLK_RATE(600000000, 0), 306 RK3588_CPUB01CLK_RATE(408000000, 0), 307 RK3588_CPUB01CLK_RATE(312000000, 0), 308 RK3588_CPUB01CLK_RATE(216000000, 0), 309 RK3588_CPUB01CLK_RATE(96000000, 0), 310 }; 311 312 static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = { 313 .core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0), 314 .div_core_shift[0] = 8, 315 .div_core_mask[0] = 0x1f, 316 .core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1), 317 .div_core_shift[1] = 0, 318 .div_core_mask[1] = 0x1f, 319 .num_cores = 2, 320 .mux_core_alt = 1, 321 .mux_core_main = 2, 322 .mux_core_shift = 6, 323 .mux_core_mask = 0x3, 324 }; 325 326 static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = { 327 RK3588_CPUB23CLK_RATE(2496000000, 1), 328 RK3588_CPUB23CLK_RATE(2400000000, 1), 329 RK3588_CPUB23CLK_RATE(2304000000, 1), 330 RK3588_CPUB23CLK_RATE(2208000000, 1), 331 RK3588_CPUB23CLK_RATE(2184000000, 1), 332 RK3588_CPUB23CLK_RATE(2088000000, 1), 333 RK3588_CPUB23CLK_RATE(2040000000, 1), 334 RK3588_CPUB23CLK_RATE(2016000000, 1), 335 RK3588_CPUB23CLK_RATE(1992000000, 1), 336 RK3588_CPUB23CLK_RATE(1896000000, 1), 337 RK3588_CPUB23CLK_RATE(1800000000, 1), 338 RK3588_CPUB23CLK_RATE(1704000000, 0), 339 RK3588_CPUB23CLK_RATE(1608000000, 0), 340 RK3588_CPUB23CLK_RATE(1584000000, 0), 341 RK3588_CPUB23CLK_RATE(1560000000, 0), 342 RK3588_CPUB23CLK_RATE(1536000000, 0), 343 RK3588_CPUB23CLK_RATE(1512000000, 0), 344 RK3588_CPUB23CLK_RATE(1488000000, 0), 345 RK3588_CPUB23CLK_RATE(1464000000, 0), 346 RK3588_CPUB23CLK_RATE(1440000000, 0), 347 RK3588_CPUB23CLK_RATE(1416000000, 0), 348 RK3588_CPUB23CLK_RATE(1392000000, 0), 349 RK3588_CPUB23CLK_RATE(1368000000, 0), 350 RK3588_CPUB23CLK_RATE(1344000000, 0), 351 RK3588_CPUB23CLK_RATE(1320000000, 0), 352 RK3588_CPUB23CLK_RATE(1296000000, 0), 353 RK3588_CPUB23CLK_RATE(1272000000, 0), 354 RK3588_CPUB23CLK_RATE(1248000000, 0), 355 RK3588_CPUB23CLK_RATE(1224000000, 0), 356 RK3588_CPUB23CLK_RATE(1200000000, 0), 357 RK3588_CPUB23CLK_RATE(1104000000, 0), 358 RK3588_CPUB23CLK_RATE(1008000000, 0), 359 RK3588_CPUB23CLK_RATE(912000000, 0), 360 RK3588_CPUB23CLK_RATE(816000000, 0), 361 RK3588_CPUB23CLK_RATE(696000000, 0), 362 RK3588_CPUB23CLK_RATE(600000000, 0), 363 RK3588_CPUB23CLK_RATE(408000000, 0), 364 RK3588_CPUB23CLK_RATE(312000000, 0), 365 RK3588_CPUB23CLK_RATE(216000000, 0), 366 RK3588_CPUB23CLK_RATE(96000000, 0), 367 }; 368 369 static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = { 370 .core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0), 371 .div_core_shift[0] = 8, 372 .div_core_mask[0] = 0x1f, 373 .core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1), 374 .div_core_shift[1] = 0, 375 .div_core_mask[1] = 0x1f, 376 .num_cores = 2, 377 .mux_core_alt = 1, 378 .mux_core_main = 2, 379 .mux_core_shift = 6, 380 .mux_core_mask = 0x3, 381 }; 382 383 static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = { 384 RK3588_CPULCLK_RATE(2208000000, 1, 3, 1), 385 RK3588_CPULCLK_RATE(2184000000, 1, 3, 1), 386 RK3588_CPULCLK_RATE(2088000000, 1, 3, 1), 387 RK3588_CPULCLK_RATE(2040000000, 1, 3, 1), 388 RK3588_CPULCLK_RATE(2016000000, 1, 3, 1), 389 RK3588_CPULCLK_RATE(1992000000, 1, 3, 1), 390 RK3588_CPULCLK_RATE(1896000000, 1, 3, 1), 391 RK3588_CPULCLK_RATE(1800000000, 1, 3, 1), 392 RK3588_CPULCLK_RATE(1704000000, 0, 3, 1), 393 RK3588_CPULCLK_RATE(1608000000, 0, 3, 1), 394 RK3588_CPULCLK_RATE(1584000000, 0, 2, 1), 395 RK3588_CPULCLK_RATE(1560000000, 0, 2, 1), 396 RK3588_CPULCLK_RATE(1536000000, 0, 2, 1), 397 RK3588_CPULCLK_RATE(1512000000, 0, 2, 1), 398 RK3588_CPULCLK_RATE(1488000000, 0, 2, 1), 399 RK3588_CPULCLK_RATE(1464000000, 0, 2, 1), 400 RK3588_CPULCLK_RATE(1440000000, 0, 2, 1), 401 RK3588_CPULCLK_RATE(1416000000, 0, 2, 1), 402 RK3588_CPULCLK_RATE(1392000000, 0, 2, 1), 403 RK3588_CPULCLK_RATE(1368000000, 0, 2, 1), 404 RK3588_CPULCLK_RATE(1344000000, 0, 2, 1), 405 RK3588_CPULCLK_RATE(1320000000, 0, 2, 1), 406 RK3588_CPULCLK_RATE(1296000000, 0, 2, 1), 407 RK3588_CPULCLK_RATE(1272000000, 0, 2, 1), 408 RK3588_CPULCLK_RATE(1248000000, 0, 2, 1), 409 RK3588_CPULCLK_RATE(1224000000, 0, 2, 1), 410 RK3588_CPULCLK_RATE(1200000000, 0, 2, 1), 411 RK3588_CPULCLK_RATE(1104000000, 0, 2, 1), 412 RK3588_CPULCLK_RATE(1008000000, 0, 2, 1), 413 RK3588_CPULCLK_RATE(912000000, 0, 2, 1), 414 RK3588_CPULCLK_RATE(816000000, 0, 2, 1), 415 RK3588_CPULCLK_RATE(696000000, 0, 2, 1), 416 RK3588_CPULCLK_RATE(600000000, 0, 2, 1), 417 RK3588_CPULCLK_RATE(408000000, 0, 2, 1), 418 RK3588_CPULCLK_RATE(312000000, 0, 2, 1), 419 RK3588_CPULCLK_RATE(216000000, 0, 2, 1), 420 RK3588_CPULCLK_RATE(96000000, 0, 2, 1), 421 }; 422 423 static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = { 424 .core_reg[0] = RK3588_DSU_CLKSEL_CON(6), 425 .div_core_shift[0] = 0, 426 .div_core_mask[0] = 0x1f, 427 .core_reg[1] = RK3588_DSU_CLKSEL_CON(6), 428 .div_core_shift[1] = 7, 429 .div_core_mask[1] = 0x1f, 430 .core_reg[2] = RK3588_DSU_CLKSEL_CON(7), 431 .div_core_shift[2] = 0, 432 .div_core_mask[2] = 0x1f, 433 .core_reg[3] = RK3588_DSU_CLKSEL_CON(7), 434 .div_core_shift[3] = 7, 435 .div_core_mask[3] = 0x1f, 436 .num_cores = 4, 437 .mux_core_reg = RK3588_DSU_CLKSEL_CON(5), 438 .mux_core_alt = 1, 439 .mux_core_main = 2, 440 .mux_core_shift = 14, 441 .mux_core_mask = 0x3, 442 }; 443 444 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 445 PNAME(mux_armclkl_p) = { "xin24m", "gpll", "lpll" }; 446 PNAME(mux_armclkb01_p) = { "xin24m", "gpll", "b0pll",}; 447 PNAME(mux_armclkb23_p) = { "xin24m", "gpll", "b1pll",}; 448 PNAME(b0pll_b1pll_lpll_gpll_p) = { "b0pll", "b1pll", "lpll", "gpll" }; 449 PNAME(gpll_24m_p) = { "gpll", "xin24m" }; 450 PNAME(gpll_aupll_p) = { "gpll", "aupll" }; 451 PNAME(gpll_lpll_p) = { "gpll", "lpll" }; 452 PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 453 PNAME(gpll_spll_p) = { "gpll", "spll" }; 454 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m"}; 455 PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll"}; 456 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll"}; 457 PNAME(gpll_cpll_npll_v0pll_p) = { "gpll", "cpll", "npll", "v0pll"}; 458 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; 459 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; 460 PNAME(gpll_cpll_aupll_npll_p) = { "gpll", "cpll", "aupll", "npll" }; 461 PNAME(gpll_cpll_v0pll_aupll_p) = { "gpll", "cpll", "v0pll", "aupll" }; 462 PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" }; 463 PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" }; 464 PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; 465 PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" }; 466 PNAME(gpll_cpll_npll_1000m_p) = { "gpll", "cpll", "npll", "clk_1000m_src" }; 467 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" }; 468 PNAME(mux_24m_32k_p) = { "xin24m", "xin32k" }; 469 PNAME(mux_24m_100m_p) = { "xin24m", "clk_100m_src" }; 470 PNAME(mux_200m_100m_p) = { "clk_200m_src", "clk_100m_src" }; 471 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", "xin24m" }; 472 PNAME(mux_150m_50m_24m_p) = { "clk_150m_src", "clk_50m_src", "xin24m" }; 473 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", "xin24m" }; 474 PNAME(mux_200m_150m_24m_p) = { "clk_200m_src", "clk_150m_src", "xin24m" }; 475 PNAME(mux_150m_100m_50m_24m_p) = { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 476 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 477 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 478 PNAME(mux_700m_400m_200m_24m_p) = { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" }; 479 PNAME(mux_500m_250m_100m_24m_p) = { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" }; 480 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" }; 481 PNAME(mux_400m_200m_100m_24m_p) = { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 482 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; 483 PNAME(i2s2_2ch_mclkout_p) = { "mclk_i2s2_2ch", "xin12m" }; 484 PNAME(clk_i2s3_2ch_p) = { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; 485 PNAME(i2s3_2ch_mclkout_p) = { "mclk_i2s3_2ch", "xin12m" }; 486 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; 487 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; 488 PNAME(i2s0_8ch_mclkout_p) = { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; 489 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; 490 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; 491 PNAME(i2s1_8ch_mclkout_p) = { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; 492 PNAME(clk_i2s4_8ch_tx_p) = { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; 493 PNAME(clk_i2s5_8ch_tx_p) = { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; 494 PNAME(clk_i2s6_8ch_tx_p) = { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; 495 PNAME(clk_i2s6_8ch_rx_p) = { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; 496 PNAME(i2s6_8ch_mclkout_p) = { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; 497 PNAME(clk_i2s7_8ch_rx_p) = { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; 498 PNAME(clk_i2s8_8ch_tx_p) = { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; 499 PNAME(clk_i2s9_8ch_rx_p) = { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; 500 PNAME(clk_i2s10_8ch_rx_p) = { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; 501 PNAME(clk_spdif0_p) = { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; 502 PNAME(clk_spdif1_p) = { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; 503 PNAME(clk_spdif2_dp0_p) = { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; 504 PNAME(clk_spdif3_p) = { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; 505 PNAME(clk_spdif4_p) = { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; 506 PNAME(clk_spdif5_dp1_p) = { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; 507 PNAME(clk_uart0_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" }; 508 PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 509 PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 510 PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 511 PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 512 PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 513 PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 514 PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 515 PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 516 PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 517 PNAME(clk_gmac0_ptp_ref_p) = { "cpll", "clk_gmac0_ptpref_io" }; 518 PNAME(clk_gmac1_ptp_ref_p) = { "cpll", "clk_gmac1_ptpref_io" }; 519 PNAME(clk_hdmirx_aud_p) = { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" }; 520 PNAME(aclk_hdcp1_root_p) = { "gpll", "cpll", "clk_hdmitrx_refsrc" }; 521 PNAME(aclk_vop_sub_src_p) = { "aclk_vop_root", "aclk_vop_div2_src" }; 522 PNAME(dclk_vop0_p) = { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 523 PNAME(dclk_vop1_p) = { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 524 PNAME(dclk_vop2_p) = { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 525 PNAME(pmu_200m_100m_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; 526 PNAME(pmu_300m_24m_p) = { "clk_300m_src", "xin24m" }; 527 PNAME(pmu_400m_24m_p) = { "clk_400m_src", "xin24m" }; 528 PNAME(pmu_100m_50m_24m_src_p) = { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 529 PNAME(pmu_24m_32k_100m_src_p) = { "xin24m", "32k", "clk_pmu1_100m_src" }; 530 PNAME(hclk_pmu1_root_p) = { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 531 PNAME(hclk_pmu_cm0_root_p) = { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; 532 PNAME(mclk_pdm0_p) = { "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; 533 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" }; 534 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 535 PNAME(clk_ref_pipe_phy0_p) = { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; 536 PNAME(clk_ref_pipe_phy1_p) = { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; 537 PNAME(clk_ref_pipe_phy2_p) = { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; 538 539 #define MFLAGS CLK_MUX_HIWORD_MASK 540 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 541 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 542 543 static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata = 544 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT, 545 RK3588_CLKSEL_CON(26), 0, 2, MFLAGS); 546 547 static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata = 548 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT, 549 RK3588_CLKSEL_CON(28), 0, 2, MFLAGS); 550 551 static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata = 552 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT, 553 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS); 554 555 static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata = 556 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT, 557 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS); 558 559 static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata = 560 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT, 561 RK3588_CLKSEL_CON(30), 0, 2, MFLAGS); 562 563 static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata = 564 MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT, 565 RK3588_CLKSEL_CON(32), 0, 2, MFLAGS); 566 567 static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata = 568 MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT, 569 RK3588_CLKSEL_CON(120), 0, 2, MFLAGS); 570 571 static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata = 572 MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT, 573 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS); 574 575 static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata = 576 MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT, 577 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS); 578 579 static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata = 580 MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT, 581 RK3588_CLKSEL_CON(148), 0, 2, MFLAGS); 582 583 static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata = 584 MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT, 585 RK3588_CLKSEL_CON(131), 0, 2, MFLAGS); 586 587 static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata = 588 MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT, 589 RK3588_CLKSEL_CON(122), 0, 2, MFLAGS); 590 591 static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata = 592 MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT, 593 RK3588_CLKSEL_CON(155), 0, 2, MFLAGS); 594 595 static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata = 596 MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT, 597 RK3588_CLKSEL_CON(157), 0, 2, MFLAGS); 598 599 static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata = 600 MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT, 601 RK3588_CLKSEL_CON(34), 0, 2, MFLAGS); 602 603 static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata = 604 MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT, 605 RK3588_CLKSEL_CON(36), 0, 2, MFLAGS); 606 607 static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata = 608 MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT, 609 RK3588_CLKSEL_CON(124), 0, 2, MFLAGS); 610 611 static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata = 612 MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT, 613 RK3588_CLKSEL_CON(150), 0, 2, MFLAGS); 614 615 static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata = 616 MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT, 617 RK3588_CLKSEL_CON(152), 0, 2, MFLAGS); 618 619 static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata = 620 MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT, 621 RK3588_CLKSEL_CON(126), 0, 2, MFLAGS); 622 623 static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata = 624 MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT, 625 RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS); 626 627 static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata = 628 MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, 629 RK3588_CLKSEL_CON(43), 0, 2, MFLAGS); 630 631 static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata = 632 MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, 633 RK3588_CLKSEL_CON(45), 0, 2, MFLAGS); 634 635 static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata = 636 MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, 637 RK3588_CLKSEL_CON(47), 0, 2, MFLAGS); 638 639 static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata = 640 MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, 641 RK3588_CLKSEL_CON(49), 0, 2, MFLAGS); 642 643 static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata = 644 MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, 645 RK3588_CLKSEL_CON(51), 0, 2, MFLAGS); 646 647 static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata = 648 MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, 649 RK3588_CLKSEL_CON(53), 0, 2, MFLAGS); 650 651 static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata = 652 MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, 653 RK3588_CLKSEL_CON(55), 0, 2, MFLAGS); 654 655 static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata = 656 MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, 657 RK3588_CLKSEL_CON(57), 0, 2, MFLAGS); 658 659 static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata = 660 MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, 661 RK3588_CLKSEL_CON(59), 0, 2, MFLAGS); 662 663 static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata = 664 MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT, 665 RK3588_CLKSEL_CON(140), 0, 1, MFLAGS); 666 667 static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { 668 [b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p, 669 CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0), 670 RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 671 [b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p, 672 CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8), 673 RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 674 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, 675 CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16), 676 RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 677 [v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p, 678 0, RK3588_PLL_CON(88), 679 RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates), 680 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, 681 0, RK3588_PLL_CON(96), 682 RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates), 683 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, 684 CLK_IGNORE_UNUSED, RK3588_PLL_CON(104), 685 RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates), 686 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, 687 CLK_IGNORE_UNUSED, RK3588_PLL_CON(112), 688 RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates), 689 [npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p, 690 0, RK3588_PLL_CON(120), 691 RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), 692 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p, 693 CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128), 694 RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), 695 }; 696 697 static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { 698 /* 699 * CRU Clock-Architecture 700 */ 701 /* fixed */ 702 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 703 704 /* top */ 705 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL, 706 RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, 707 RK3588_CLKGATE_CON(0), 0, GFLAGS), 708 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, 709 RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, 710 RK3588_CLKGATE_CON(0), 1, GFLAGS), 711 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL, 712 RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 713 RK3588_CLKGATE_CON(0), 2, GFLAGS), 714 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 715 RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, 716 RK3588_CLKGATE_CON(0), 3, GFLAGS), 717 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL, 718 RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 719 RK3588_CLKGATE_CON(0), 4, GFLAGS), 720 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, 721 RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, 722 RK3588_CLKGATE_CON(0), 5, GFLAGS), 723 COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL, 724 RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS, 725 RK3588_CLKGATE_CON(0), 6, GFLAGS), 726 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL, 727 RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, 728 RK3588_CLKGATE_CON(0), 7, GFLAGS), 729 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0, 730 RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS, 731 RK3588_CLKGATE_CON(0), 8, GFLAGS), 732 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL, 733 RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, 734 RK3588_CLKGATE_CON(0), 9, GFLAGS), 735 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL, 736 RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, 737 RK3588_CLKGATE_CON(0), 10, GFLAGS), 738 COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0, 739 RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS, 740 RK3588_CLKGATE_CON(0), 11, GFLAGS), 741 COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL, 742 RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS, 743 RK3588_CLKGATE_CON(0), 12, GFLAGS), 744 COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL, 745 RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS, 746 RK3588_CLKGATE_CON(0), 13, GFLAGS), 747 COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL, 748 RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS, 749 RK3588_CLKGATE_CON(0), 14, GFLAGS), 750 COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL, 751 RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS, 752 RK3588_CLKGATE_CON(0), 15, GFLAGS), 753 COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 754 RK3588_CLKSEL_CON(9), 0, 2, MFLAGS, 755 RK3588_CLKGATE_CON(1), 10, GFLAGS), 756 COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, 757 RK3588_CLKSEL_CON(9), 2, 2, MFLAGS, 758 RK3588_CLKGATE_CON(1), 11, GFLAGS), 759 COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 760 RK3588_CLKSEL_CON(9), 4, 2, MFLAGS, 761 RK3588_CLKGATE_CON(1), 12, GFLAGS), 762 COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 763 RK3588_CLKSEL_CON(9), 6, 2, MFLAGS, 764 RK3588_CLKGATE_CON(1), 13, GFLAGS), 765 COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL, 766 RK3588_CLKSEL_CON(9), 8, 2, MFLAGS, 767 RK3588_CLKGATE_CON(1), 14, GFLAGS), 768 COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL, 769 RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS, 770 RK3588_CLKGATE_CON(1), 0, GFLAGS), 771 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 772 RK3588_CLKSEL_CON(8), 7, 2, MFLAGS, 773 RK3588_CLKGATE_CON(1), 1, GFLAGS), 774 COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 775 RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS, 776 RK3588_CLKGATE_CON(1), 2, GFLAGS), 777 COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0, 778 RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS, 779 RK3588_CLKGATE_CON(5), 9, GFLAGS), 780 COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0, 781 RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS, 782 RK3588_CLKGATE_CON(5), 10, GFLAGS), 783 COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0, 784 RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, 785 RK3588_CLKGATE_CON(5), 11, GFLAGS), 786 COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0, 787 RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS, 788 RK3588_CLKGATE_CON(5), 12, GFLAGS), 789 COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0, 790 RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS, 791 RK3588_CLKGATE_CON(5), 13, GFLAGS), 792 COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0, 793 RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS, 794 RK3588_CLKGATE_CON(5), 3, GFLAGS), 795 COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0, 796 RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS, 797 RK3588_CLKGATE_CON(5), 4, GFLAGS), 798 COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0, 799 RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS, 800 RK3588_CLKGATE_CON(5), 5, GFLAGS), 801 COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, 802 RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS, 803 RK3588_CLKGATE_CON(5), 6, GFLAGS), 804 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0, 805 RK3588_CLKGATE_CON(3), 14, GFLAGS), 806 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0, 807 RK3588_CLKGATE_CON(4), 3, GFLAGS), 808 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0, 809 RK3588_CLKGATE_CON(1), 6, GFLAGS), 810 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0, 811 RK3588_CLKGATE_CON(1), 8, GFLAGS), 812 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL, 813 RK3588_CLKGATE_CON(5), 0, GFLAGS), 814 815 /* bigcore0 */ 816 COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p, 817 CLK_IS_CRITICAL, 818 RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS, 819 RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS), 820 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0, 821 RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS), 822 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0, 823 RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS), 824 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0, 825 RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS), 826 827 /* bigcore1 */ 828 COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p, 829 CLK_IS_CRITICAL, 830 RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS, 831 RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS), 832 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0, 833 RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS), 834 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0, 835 RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS), 836 GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0, 837 RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS), 838 839 /* dsu */ 840 COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 841 RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS, 842 RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS), 843 COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 844 RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 845 RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS), 846 COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL, 847 RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 848 RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS), 849 COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL, 850 RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 851 RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS), 852 COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL, 853 RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 854 RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS), 855 COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL, 856 RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 857 RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS), 858 COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL, 859 RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 860 RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS), 861 COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 862 RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 863 RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS), 864 COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL, 865 RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 866 RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS), 867 COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 868 RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS, 869 RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS), 870 COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL, 871 RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, 872 RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS), 873 COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 874 RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS, 875 RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS), 876 GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0, 877 RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS), 878 GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL, 879 RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS), 880 GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL, 881 RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS), 882 GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED, 883 RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS), 884 GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED, 885 RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS), 886 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0, 887 RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS), 888 GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0, 889 RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS), 890 891 /* audio */ 892 COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, 893 RK3588_CLKSEL_CON(24), 0, 2, MFLAGS, 894 RK3588_CLKGATE_CON(7), 0, GFLAGS), 895 COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0, 896 RK3588_CLKSEL_CON(24), 2, 2, MFLAGS, 897 RK3588_CLKGATE_CON(7), 1, GFLAGS), 898 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0, 899 RK3588_CLKGATE_CON(7), 12, GFLAGS), 900 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0, 901 RK3588_CLKGATE_CON(7), 13, GFLAGS), 902 COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0, 903 RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS, 904 RK3588_CLKGATE_CON(7), 14, GFLAGS), 905 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", 906 CLK_SET_RATE_PARENT, 907 RK3588_CLKSEL_CON(29), 0, 908 RK3588_CLKGATE_CON(7), 15, GFLAGS, 909 &rk3588_i2s2_2ch_fracmux), 910 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0, 911 RK3588_CLKGATE_CON(8), 0, GFLAGS), 912 MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT, 913 RK3588_CLKSEL_CON(30), 2, 1, MFLAGS), 914 915 COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0, 916 RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS, 917 RK3588_CLKGATE_CON(8), 1, GFLAGS), 918 COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src", 919 CLK_SET_RATE_PARENT, 920 RK3588_CLKSEL_CON(31), 0, 921 RK3588_CLKGATE_CON(8), 2, GFLAGS, 922 &rk3588_i2s3_2ch_fracmux), 923 GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0, 924 RK3588_CLKGATE_CON(8), 3, GFLAGS), 925 GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0, 926 RK3588_CLKGATE_CON(8), 4, GFLAGS), 927 MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT, 928 RK3588_CLKSEL_CON(32), 2, 1, MFLAGS), 929 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0, 930 RK3588_CLKGATE_CON(7), 11, GFLAGS), 931 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0, 932 RK3588_CLKGATE_CON(7), 4, GFLAGS), 933 934 COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0, 935 RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS, 936 RK3588_CLKGATE_CON(7), 5, GFLAGS), 937 COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", 938 CLK_SET_RATE_PARENT, 939 RK3588_CLKSEL_CON(25), 0, 940 RK3588_CLKGATE_CON(7), 6, GFLAGS, 941 &rk3588_i2s0_8ch_tx_fracmux), 942 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0, 943 RK3588_CLKGATE_CON(7), 7, GFLAGS), 944 945 COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0, 946 RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS, 947 RK3588_CLKGATE_CON(7), 8, GFLAGS), 948 COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", 949 CLK_SET_RATE_PARENT, 950 RK3588_CLKSEL_CON(27), 0, 951 RK3588_CLKGATE_CON(7), 9, GFLAGS, 952 &rk3588_i2s0_8ch_rx_fracmux), 953 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0, 954 RK3588_CLKGATE_CON(7), 10, GFLAGS), 955 MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT, 956 RK3588_CLKSEL_CON(28), 2, 2, MFLAGS), 957 958 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, 959 RK3588_CLKGATE_CON(9), 6, GFLAGS), 960 COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0, 961 RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS, 962 RK3588_CLKGATE_CON(9), 7, GFLAGS), 963 964 GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0, 965 RK3588_CLKGATE_CON(8), 14, GFLAGS), 966 COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0, 967 RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS, 968 RK3588_CLKGATE_CON(8), 15, GFLAGS), 969 COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src", 970 CLK_SET_RATE_PARENT, 971 RK3588_CLKSEL_CON(33), 0, 972 RK3588_CLKGATE_CON(9), 0, GFLAGS, 973 &rk3588_spdif0_fracmux), 974 GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0, 975 RK3588_CLKGATE_CON(9), 1, GFLAGS), 976 977 GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0, 978 RK3588_CLKGATE_CON(9), 2, GFLAGS), 979 COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0, 980 RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS, 981 RK3588_CLKGATE_CON(9), 3, GFLAGS), 982 COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src", 983 CLK_SET_RATE_PARENT, 984 RK3588_CLKSEL_CON(35), 0, 985 RK3588_CLKGATE_CON(9), 4, GFLAGS, 986 &rk3588_spdif1_fracmux), 987 GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0, 988 RK3588_CLKGATE_CON(9), 5, GFLAGS), 989 990 COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0, 991 RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS, 992 RK3588_CLKGATE_CON(68), 0, GFLAGS), 993 COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0, 994 RK3588_CLKSEL_CON(163), 7, 2, MFLAGS, 995 RK3588_CLKGATE_CON(68), 3, GFLAGS), 996 997 /* bus */ 998 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, 999 RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 1000 RK3588_CLKGATE_CON(10), 0, GFLAGS), 1001 1002 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0, 1003 RK3588_CLKGATE_CON(16), 11, GFLAGS), 1004 GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0, 1005 RK3588_CLKGATE_CON(16), 12, GFLAGS), 1006 GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0, 1007 RK3588_CLKGATE_CON(16), 13, GFLAGS), 1008 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL, 1009 RK3588_CLKGATE_CON(19), 3, GFLAGS), 1010 GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 1011 RK3588_CLKGATE_CON(19), 4, GFLAGS), 1012 GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL, 1013 RK3588_CLKGATE_CON(19), 5, GFLAGS), 1014 1015 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0, 1016 RK3588_CLKGATE_CON(15), 3, GFLAGS), 1017 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, 1018 RK3588_CLKSEL_CON(59), 12, 2, MFLAGS, 1019 RK3588_CLKGATE_CON(15), 4, GFLAGS), 1020 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, 1021 RK3588_CLKGATE_CON(15), 5, GFLAGS), 1022 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0, 1023 RK3588_CLKGATE_CON(15), 6, GFLAGS), 1024 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, 1025 RK3588_CLKSEL_CON(59), 14, 2, MFLAGS, 1026 RK3588_CLKGATE_CON(15), 7, GFLAGS), 1027 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, 1028 RK3588_CLKGATE_CON(15), 8, GFLAGS), 1029 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0, 1030 RK3588_CLKGATE_CON(15), 9, GFLAGS), 1031 COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0, 1032 RK3588_CLKSEL_CON(60), 0, 2, MFLAGS, 1033 RK3588_CLKGATE_CON(15), 10, GFLAGS), 1034 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, 1035 RK3588_CLKGATE_CON(15), 11, GFLAGS), 1036 1037 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0, 1038 RK3588_CLKGATE_CON(15), 12, GFLAGS), 1039 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0, 1040 RK3588_CLKGATE_CON(15), 13, GFLAGS), 1041 COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0, 1042 RK3588_CLKSEL_CON(60), 2, 1, MFLAGS, 1043 RK3588_CLKGATE_CON(15), 14, GFLAGS), 1044 GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0, 1045 RK3588_CLKGATE_CON(15), 15, GFLAGS), 1046 GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0, 1047 RK3588_CLKGATE_CON(16), 0, GFLAGS), 1048 GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0, 1049 RK3588_CLKGATE_CON(16), 1, GFLAGS), 1050 GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0, 1051 RK3588_CLKGATE_CON(16), 2, GFLAGS), 1052 GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0, 1053 RK3588_CLKGATE_CON(16), 3, GFLAGS), 1054 GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0, 1055 RK3588_CLKGATE_CON(16), 4, GFLAGS), 1056 GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0, 1057 RK3588_CLKGATE_CON(16), 5, GFLAGS), 1058 GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0, 1059 RK3588_CLKGATE_CON(16), 6, GFLAGS), 1060 GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0, 1061 RK3588_CLKGATE_CON(16), 7, GFLAGS), 1062 GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0, 1063 RK3588_CLKGATE_CON(16), 8, GFLAGS), 1064 GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0, 1065 RK3588_CLKGATE_CON(16), 9, GFLAGS), 1066 GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0, 1067 RK3588_CLKGATE_CON(16), 10, GFLAGS), 1068 1069 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0, 1070 RK3588_CLKGATE_CON(15), 0, GFLAGS), 1071 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, 1072 RK3588_CLKGATE_CON(15), 1, GFLAGS), 1073 1074 GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0, 1075 RK3588_CLKGATE_CON(11), 8, GFLAGS), 1076 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, 1077 RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS, 1078 RK3588_CLKGATE_CON(11), 9, GFLAGS), 1079 GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0, 1080 RK3588_CLKGATE_CON(11), 10, GFLAGS), 1081 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, 1082 RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS, 1083 RK3588_CLKGATE_CON(11), 11, GFLAGS), 1084 GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0, 1085 RK3588_CLKGATE_CON(11), 12, GFLAGS), 1086 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0, 1087 RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS, 1088 RK3588_CLKGATE_CON(11), 13, GFLAGS), 1089 1090 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, 1091 RK3588_CLKGATE_CON(17), 6, GFLAGS), 1092 GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0, 1093 RK3588_CLKGATE_CON(17), 7, GFLAGS), 1094 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, 1095 RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS, 1096 RK3588_CLKGATE_CON(17), 8, GFLAGS), 1097 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, 1098 RK3588_CLKGATE_CON(10), 5, GFLAGS), 1099 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, 1100 RK3588_CLKGATE_CON(10), 6, GFLAGS), 1101 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, 1102 RK3588_CLKGATE_CON(10), 7, GFLAGS), 1103 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, 1104 RK3588_CLKGATE_CON(10), 3, GFLAGS), 1105 1106 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0, 1107 RK3588_CLKGATE_CON(16), 14, GFLAGS), 1108 COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0, 1109 RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS, 1110 RK3588_CLKGATE_CON(16), 15, GFLAGS), 1111 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0, 1112 RK3588_CLKGATE_CON(17), 0, GFLAGS), 1113 COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0, 1114 RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS, 1115 RK3588_CLKGATE_CON(17), 1, GFLAGS), 1116 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0, 1117 RK3588_CLKGATE_CON(17), 2, GFLAGS), 1118 COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0, 1119 RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS, 1120 RK3588_CLKGATE_CON(17), 3, GFLAGS), 1121 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0, 1122 RK3588_CLKGATE_CON(17), 4, GFLAGS), 1123 COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0, 1124 RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS, 1125 RK3588_CLKGATE_CON(17), 5, GFLAGS), 1126 1127 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0, 1128 RK3588_CLKGATE_CON(10), 8, GFLAGS), 1129 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0, 1130 RK3588_CLKGATE_CON(10), 9, GFLAGS), 1131 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0, 1132 RK3588_CLKGATE_CON(10), 10, GFLAGS), 1133 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0, 1134 RK3588_CLKGATE_CON(10), 11, GFLAGS), 1135 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0, 1136 RK3588_CLKGATE_CON(10), 12, GFLAGS), 1137 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0, 1138 RK3588_CLKGATE_CON(10), 13, GFLAGS), 1139 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0, 1140 RK3588_CLKGATE_CON(10), 14, GFLAGS), 1141 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0, 1142 RK3588_CLKGATE_CON(10), 15, GFLAGS), 1143 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0, 1144 RK3588_CLKSEL_CON(38), 6, 1, MFLAGS, 1145 RK3588_CLKGATE_CON(11), 0, GFLAGS), 1146 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0, 1147 RK3588_CLKSEL_CON(38), 7, 1, MFLAGS, 1148 RK3588_CLKGATE_CON(11), 1, GFLAGS), 1149 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0, 1150 RK3588_CLKSEL_CON(38), 8, 1, MFLAGS, 1151 RK3588_CLKGATE_CON(11), 2, GFLAGS), 1152 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0, 1153 RK3588_CLKSEL_CON(38), 9, 1, MFLAGS, 1154 RK3588_CLKGATE_CON(11), 3, GFLAGS), 1155 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0, 1156 RK3588_CLKSEL_CON(38), 10, 1, MFLAGS, 1157 RK3588_CLKGATE_CON(11), 4, GFLAGS), 1158 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0, 1159 RK3588_CLKSEL_CON(38), 11, 1, MFLAGS, 1160 RK3588_CLKGATE_CON(11), 5, GFLAGS), 1161 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0, 1162 RK3588_CLKSEL_CON(38), 12, 1, MFLAGS, 1163 RK3588_CLKGATE_CON(11), 6, GFLAGS), 1164 COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0, 1165 RK3588_CLKSEL_CON(38), 13, 1, MFLAGS, 1166 RK3588_CLKGATE_CON(11), 7, GFLAGS), 1167 1168 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0, 1169 RK3588_CLKGATE_CON(18), 9, GFLAGS), 1170 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, 1171 RK3588_CLKGATE_CON(18), 10, GFLAGS), 1172 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, 1173 RK3588_CLKGATE_CON(18), 11, GFLAGS), 1174 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, 1175 RK3588_CLKGATE_CON(18), 13, GFLAGS), 1176 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, 1177 RK3588_CLKGATE_CON(18), 12, GFLAGS), 1178 1179 GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0, 1180 RK3588_CLKGATE_CON(11), 14, GFLAGS), 1181 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, 1182 RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS, 1183 RK3588_CLKGATE_CON(11), 15, GFLAGS), 1184 1185 GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0, 1186 RK3588_CLKGATE_CON(14), 6, GFLAGS), 1187 GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0, 1188 RK3588_CLKGATE_CON(14), 7, GFLAGS), 1189 GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0, 1190 RK3588_CLKGATE_CON(14), 8, GFLAGS), 1191 GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0, 1192 RK3588_CLKGATE_CON(14), 9, GFLAGS), 1193 GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0, 1194 RK3588_CLKGATE_CON(14), 10, GFLAGS), 1195 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0, 1196 RK3588_CLKSEL_CON(59), 2, 2, MFLAGS, 1197 RK3588_CLKGATE_CON(14), 11, GFLAGS), 1198 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0, 1199 RK3588_CLKSEL_CON(59), 4, 2, MFLAGS, 1200 RK3588_CLKGATE_CON(14), 12, GFLAGS), 1201 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0, 1202 RK3588_CLKSEL_CON(59), 6, 2, MFLAGS, 1203 RK3588_CLKGATE_CON(14), 13, GFLAGS), 1204 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0, 1205 RK3588_CLKSEL_CON(59), 8, 2, MFLAGS, 1206 RK3588_CLKGATE_CON(14), 14, GFLAGS), 1207 COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0, 1208 RK3588_CLKSEL_CON(59), 10, 2, MFLAGS, 1209 RK3588_CLKGATE_CON(14), 15, GFLAGS), 1210 1211 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED, 1212 RK3588_CLKGATE_CON(18), 6, GFLAGS), 1213 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0, 1214 RK3588_CLKGATE_CON(12), 0, GFLAGS), 1215 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0, 1216 RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS, 1217 RK3588_CLKGATE_CON(12), 1, GFLAGS), 1218 1219 GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0, 1220 RK3588_CLKGATE_CON(12), 2, GFLAGS), 1221 GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0, 1222 RK3588_CLKGATE_CON(12), 3, GFLAGS), 1223 GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0, 1224 RK3588_CLKGATE_CON(12), 4, GFLAGS), 1225 GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0, 1226 RK3588_CLKGATE_CON(12), 5, GFLAGS), 1227 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0, 1228 RK3588_CLKGATE_CON(12), 6, GFLAGS), 1229 GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0, 1230 RK3588_CLKGATE_CON(12), 7, GFLAGS), 1231 GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0, 1232 RK3588_CLKGATE_CON(12), 8, GFLAGS), 1233 GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0, 1234 RK3588_CLKGATE_CON(12), 9, GFLAGS), 1235 GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0, 1236 RK3588_CLKGATE_CON(12), 10, GFLAGS), 1237 1238 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, 1239 RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS, 1240 RK3588_CLKGATE_CON(12), 11, GFLAGS), 1241 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 1242 RK3588_CLKSEL_CON(42), 0, 1243 RK3588_CLKGATE_CON(12), 12, GFLAGS, 1244 &rk3588_uart1_fracmux), 1245 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, 1246 RK3588_CLKGATE_CON(12), 13, GFLAGS), 1247 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, 1248 RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS, 1249 RK3588_CLKGATE_CON(12), 14, GFLAGS), 1250 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 1251 RK3588_CLKSEL_CON(44), 0, 1252 RK3588_CLKGATE_CON(12), 15, GFLAGS, 1253 &rk3588_uart2_fracmux), 1254 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, 1255 RK3588_CLKGATE_CON(13), 0, GFLAGS), 1256 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, 1257 RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS, 1258 RK3588_CLKGATE_CON(13), 1, GFLAGS), 1259 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 1260 RK3588_CLKSEL_CON(46), 0, 1261 RK3588_CLKGATE_CON(13), 2, GFLAGS, 1262 &rk3588_uart3_fracmux), 1263 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, 1264 RK3588_CLKGATE_CON(13), 3, GFLAGS), 1265 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, 1266 RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS, 1267 RK3588_CLKGATE_CON(13), 4, GFLAGS), 1268 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 1269 RK3588_CLKSEL_CON(48), 0, 1270 RK3588_CLKGATE_CON(13), 5, GFLAGS, 1271 &rk3588_uart4_fracmux), 1272 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, 1273 RK3588_CLKGATE_CON(13), 6, GFLAGS), 1274 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, 1275 RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS, 1276 RK3588_CLKGATE_CON(13), 7, GFLAGS), 1277 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 1278 RK3588_CLKSEL_CON(50), 0, 1279 RK3588_CLKGATE_CON(13), 8, GFLAGS, 1280 &rk3588_uart5_fracmux), 1281 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, 1282 RK3588_CLKGATE_CON(13), 9, GFLAGS), 1283 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, 1284 RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS, 1285 RK3588_CLKGATE_CON(13), 10, GFLAGS), 1286 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 1287 RK3588_CLKSEL_CON(52), 0, 1288 RK3588_CLKGATE_CON(13), 11, GFLAGS, 1289 &rk3588_uart6_fracmux), 1290 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, 1291 RK3588_CLKGATE_CON(13), 12, GFLAGS), 1292 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, 1293 RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS, 1294 RK3588_CLKGATE_CON(13), 13, GFLAGS), 1295 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 1296 RK3588_CLKSEL_CON(54), 0, 1297 RK3588_CLKGATE_CON(13), 14, GFLAGS, 1298 &rk3588_uart7_fracmux), 1299 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, 1300 RK3588_CLKGATE_CON(13), 15, GFLAGS), 1301 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, 1302 RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS, 1303 RK3588_CLKGATE_CON(14), 0, GFLAGS), 1304 COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, 1305 RK3588_CLKSEL_CON(56), 0, 1306 RK3588_CLKGATE_CON(14), 1, GFLAGS, 1307 &rk3588_uart8_fracmux), 1308 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, 1309 RK3588_CLKGATE_CON(14), 2, GFLAGS), 1310 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, 1311 RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS, 1312 RK3588_CLKGATE_CON(14), 3, GFLAGS), 1313 COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, 1314 RK3588_CLKSEL_CON(58), 0, 1315 RK3588_CLKGATE_CON(14), 4, GFLAGS, 1316 &rk3588_uart9_fracmux), 1317 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, 1318 RK3588_CLKGATE_CON(14), 5, GFLAGS), 1319 1320 /* center */ 1321 COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p, 1322 CLK_IS_CRITICAL, 1323 RK3588_CLKSEL_CON(165), 0, 2, MFLAGS, 1324 RK3588_CLKGATE_CON(69), 0, GFLAGS), 1325 COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, 1326 CLK_IS_CRITICAL, 1327 RK3588_CLKSEL_CON(165), 2, 2, MFLAGS, 1328 RK3588_CLKGATE_CON(69), 1, GFLAGS), 1329 COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p, 1330 CLK_IS_CRITICAL, 1331 RK3588_CLKSEL_CON(165), 4, 2, MFLAGS, 1332 RK3588_CLKGATE_CON(69), 2, GFLAGS), 1333 COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, 1334 CLK_IS_CRITICAL, 1335 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 1336 RK3588_CLKGATE_CON(69), 3, GFLAGS), 1337 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL, 1338 RK3588_CLKGATE_CON(69), 5, GFLAGS), 1339 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL, 1340 RK3588_CLKGATE_CON(69), 6, GFLAGS), 1341 COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p, 1342 CLK_IS_CRITICAL, 1343 RK3588_CLKSEL_CON(165), 8, 2, MFLAGS, 1344 RK3588_CLKGATE_CON(69), 8, GFLAGS), 1345 COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p, 1346 CLK_IS_CRITICAL, 1347 RK3588_CLKSEL_CON(165), 10, 2, MFLAGS, 1348 RK3588_CLKGATE_CON(69), 9, GFLAGS), 1349 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL, 1350 RK3588_CLKGATE_CON(69), 14, GFLAGS), 1351 COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED, 1352 RK3588_CLKSEL_CON(165), 12, 1, MFLAGS, 1353 RK3588_CLKGATE_CON(69), 15, GFLAGS), 1354 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, 1355 RK3588_CLKGATE_CON(70), 0, GFLAGS), 1356 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, 1357 RK3588_CLKGATE_CON(70), 1, GFLAGS), 1358 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, 1359 RK3588_CLKGATE_CON(70), 2, GFLAGS), 1360 COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 1361 RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, 1362 RK3588_CLKGATE_CON(70), 4, GFLAGS), 1363 GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, 1364 RK3588_CLKGATE_CON(70), 7, GFLAGS), 1365 GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0, 1366 RK3588_CLKGATE_CON(70), 8, GFLAGS), 1367 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL, 1368 RK3588_CLKGATE_CON(70), 9, GFLAGS), 1369 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL, 1370 RK3588_CLKGATE_CON(70), 10, GFLAGS), 1371 1372 /* gpu */ 1373 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0, 1374 RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS, 1375 RK3588_CLKGATE_CON(66), 1, GFLAGS), 1376 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0, 1377 RK3588_CLKGATE_CON(66), 4, GFLAGS), 1378 GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0, 1379 RK3588_CLKGATE_CON(66), 6, GFLAGS), 1380 COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0, 1381 RK3588_CLKSEL_CON(159), 0, 5, DFLAGS, 1382 RK3588_CLKGATE_CON(66), 7, GFLAGS), 1383 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0, 1384 RK3588_CLKGATE_CON(67), 0, GFLAGS), 1385 GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0, 1386 RK3588_CLKGATE_CON(67), 1, GFLAGS), 1387 1388 /* isp1 */ 1389 COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0, 1390 RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS, 1391 RK3588_CLKGATE_CON(26), 0, GFLAGS), 1392 COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0, 1393 RK3588_CLKSEL_CON(67), 7, 2, MFLAGS, 1394 RK3588_CLKGATE_CON(26), 1, GFLAGS), 1395 COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0, 1396 RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS, 1397 RK3588_CLKGATE_CON(26), 2, GFLAGS), 1398 GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0, 1399 RK3588_CLKGATE_CON(26), 3, GFLAGS), 1400 GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0, 1401 RK3588_CLKGATE_CON(26), 4, GFLAGS), 1402 1403 /* npu */ 1404 COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0, 1405 RK3588_CLKSEL_CON(73), 0, 2, MFLAGS, 1406 RK3588_CLKGATE_CON(29), 0, GFLAGS), 1407 COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0, 1408 RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS, 1409 RK3588_CLKGATE_CON(29), 1, GFLAGS), 1410 COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0, 1411 RK3588_CLKSEL_CON(74), 1, 2, MFLAGS, 1412 RK3588_CLKGATE_CON(29), 4, GFLAGS), 1413 GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0, 1414 RK3588_CLKGATE_CON(27), 0, GFLAGS), 1415 GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0, 1416 RK3588_CLKGATE_CON(27), 2, GFLAGS), 1417 GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0, 1418 RK3588_CLKGATE_CON(28), 0, GFLAGS), 1419 GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0, 1420 RK3588_CLKGATE_CON(28), 2, GFLAGS), 1421 COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, 1422 RK3588_CLKSEL_CON(74), 5, 2, MFLAGS, 1423 RK3588_CLKGATE_CON(30), 1, GFLAGS), 1424 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, 1425 RK3588_CLKGATE_CON(30), 3, GFLAGS), 1426 COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, 1427 RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS, 1428 RK3588_CLKGATE_CON(30), 5, GFLAGS), 1429 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0, 1430 RK3588_CLKGATE_CON(29), 12, GFLAGS), 1431 GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED, 1432 RK3588_CLKGATE_CON(29), 13, GFLAGS), 1433 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0, 1434 RK3588_CLKGATE_CON(29), 14, GFLAGS), 1435 GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0, 1436 RK3588_CLKGATE_CON(29), 15, GFLAGS), 1437 GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0, 1438 RK3588_CLKGATE_CON(30), 6, GFLAGS), 1439 GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0, 1440 RK3588_CLKGATE_CON(30), 8, GFLAGS), 1441 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0, 1442 RK3588_CLKGATE_CON(29), 6, GFLAGS), 1443 COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0, 1444 RK3588_CLKSEL_CON(74), 3, 1, MFLAGS, 1445 RK3588_CLKGATE_CON(29), 7, GFLAGS), 1446 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, 1447 RK3588_CLKGATE_CON(29), 8, GFLAGS), 1448 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, 1449 RK3588_CLKGATE_CON(29), 9, GFLAGS), 1450 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0, 1451 RK3588_CLKGATE_CON(29), 10, GFLAGS), 1452 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, 1453 RK3588_CLKGATE_CON(29), 11, GFLAGS), 1454 1455 /* nvm */ 1456 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, 1457 RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, 1458 RK3588_CLKGATE_CON(31), 0, GFLAGS), 1459 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, 1460 RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, 1461 RK3588_CLKGATE_CON(31), 1, GFLAGS), 1462 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, 1463 RK3588_CLKGATE_CON(31), 5, GFLAGS), 1464 COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0, 1465 RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS, 1466 RK3588_CLKGATE_CON(31), 6, GFLAGS), 1467 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, 1468 RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS, 1469 RK3588_CLKGATE_CON(31), 7, GFLAGS), 1470 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, 1471 RK3588_CLKGATE_CON(31), 8, GFLAGS), 1472 1473 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0, 1474 RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS, 1475 RK3588_CLKGATE_CON(31), 9, GFLAGS), 1476 1477 /* php */ 1478 COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0, 1479 RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, 1480 RK3588_CLKGATE_CON(34), 10, GFLAGS), 1481 COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0, 1482 RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, 1483 RK3588_CLKGATE_CON(34), 11, GFLAGS), 1484 COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0, 1485 RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS, 1486 RK3588_CLKGATE_CON(35), 5, GFLAGS), 1487 COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0, 1488 RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS, 1489 RK3588_CLKGATE_CON(35), 6, GFLAGS), 1490 1491 COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL, 1492 RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS, 1493 RK3588_CLKGATE_CON(32), 6, GFLAGS), 1494 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL, 1495 RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS, 1496 RK3588_CLKGATE_CON(32), 7, GFLAGS), 1497 COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0, 1498 RK3588_CLKSEL_CON(80), 0, 2, MFLAGS, 1499 RK3588_CLKGATE_CON(32), 0, GFLAGS), 1500 GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL, 1501 RK3588_CLKGATE_CON(34), 6, GFLAGS), 1502 GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0, 1503 RK3588_CLKGATE_CON(32), 8, GFLAGS), 1504 GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0, 1505 RK3588_CLKGATE_CON(34), 7, GFLAGS), 1506 GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0, 1507 RK3588_CLKGATE_CON(34), 8, GFLAGS), 1508 GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0, 1509 RK3588_CLKGATE_CON(32), 13, GFLAGS), 1510 GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0, 1511 RK3588_CLKGATE_CON(32), 14, GFLAGS), 1512 GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0, 1513 RK3588_CLKGATE_CON(32), 15, GFLAGS), 1514 GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0, 1515 RK3588_CLKGATE_CON(33), 0, GFLAGS), 1516 GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0, 1517 RK3588_CLKGATE_CON(33), 1, GFLAGS), 1518 GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0, 1519 RK3588_CLKGATE_CON(33), 2, GFLAGS), 1520 GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0, 1521 RK3588_CLKGATE_CON(33), 3, GFLAGS), 1522 GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0, 1523 RK3588_CLKGATE_CON(33), 4, GFLAGS), 1524 GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0, 1525 RK3588_CLKGATE_CON(33), 5, GFLAGS), 1526 GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0, 1527 RK3588_CLKGATE_CON(33), 6, GFLAGS), 1528 GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0, 1529 RK3588_CLKGATE_CON(33), 7, GFLAGS), 1530 GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0, 1531 RK3588_CLKGATE_CON(33), 8, GFLAGS), 1532 GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0, 1533 RK3588_CLKGATE_CON(33), 9, GFLAGS), 1534 GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0, 1535 RK3588_CLKGATE_CON(33), 10, GFLAGS), 1536 GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0, 1537 RK3588_CLKGATE_CON(33), 11, GFLAGS), 1538 GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0, 1539 RK3588_CLKGATE_CON(33), 12, GFLAGS), 1540 GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0, 1541 RK3588_CLKGATE_CON(33), 13, GFLAGS), 1542 GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0, 1543 RK3588_CLKGATE_CON(33), 14, GFLAGS), 1544 GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0, 1545 RK3588_CLKGATE_CON(33), 15, GFLAGS), 1546 GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0, 1547 RK3588_CLKGATE_CON(34), 0, GFLAGS), 1548 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0, 1549 RK3588_CLKGATE_CON(34), 1, GFLAGS), 1550 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0, 1551 RK3588_CLKGATE_CON(34), 2, GFLAGS), 1552 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0, 1553 RK3588_CLKGATE_CON(34), 3, GFLAGS), 1554 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0, 1555 RK3588_CLKGATE_CON(34), 4, GFLAGS), 1556 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0, 1557 RK3588_CLKGATE_CON(34), 5, GFLAGS), 1558 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0, 1559 RK3588_CLKGATE_CON(37), 0, GFLAGS), 1560 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0, 1561 RK3588_CLKGATE_CON(37), 1, GFLAGS), 1562 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0, 1563 RK3588_CLKGATE_CON(37), 2, GFLAGS), 1564 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0, 1565 RK3588_CLKGATE_CON(32), 3, GFLAGS), 1566 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0, 1567 RK3588_CLKGATE_CON(32), 4, GFLAGS), 1568 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0, 1569 RK3588_CLKGATE_CON(32), 10, GFLAGS), 1570 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0, 1571 RK3588_CLKGATE_CON(32), 11, GFLAGS), 1572 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0, 1573 RK3588_CLKGATE_CON(37), 4, GFLAGS), 1574 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0, 1575 RK3588_CLKGATE_CON(37), 5, GFLAGS), 1576 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0, 1577 RK3588_CLKGATE_CON(37), 6, GFLAGS), 1578 GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0, 1579 RK3588_CLKGATE_CON(37), 7, GFLAGS), 1580 GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0, 1581 RK3588_CLKGATE_CON(37), 8, GFLAGS), 1582 GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0, 1583 RK3588_CLKGATE_CON(37), 9, GFLAGS), 1584 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, 1585 RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS, 1586 RK3588_CLKGATE_CON(37), 10, GFLAGS), 1587 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, 1588 RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS, 1589 RK3588_CLKGATE_CON(37), 11, GFLAGS), 1590 COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0, 1591 RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS, 1592 RK3588_CLKGATE_CON(37), 12, GFLAGS), 1593 GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0, 1594 RK3588_CLKGATE_CON(35), 7, GFLAGS), 1595 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0, 1596 RK3588_CLKGATE_CON(35), 8, GFLAGS), 1597 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0, 1598 RK3588_CLKGATE_CON(35), 9, GFLAGS), 1599 COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0, 1600 RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS, 1601 RK3588_CLKGATE_CON(35), 10, GFLAGS), 1602 GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0, 1603 RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS), 1604 GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0, 1605 RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS), 1606 GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0, 1607 RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS), 1608 GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0, 1609 RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS), 1610 1611 /* rga */ 1612 COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0, 1613 RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS, 1614 RK3588_CLKGATE_CON(76), 6, GFLAGS), 1615 COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0, 1616 RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS, 1617 RK3588_CLKGATE_CON(76), 0, GFLAGS), 1618 COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0, 1619 RK3588_CLKSEL_CON(174), 7, 2, MFLAGS, 1620 RK3588_CLKGATE_CON(76), 1, GFLAGS), 1621 GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0, 1622 RK3588_CLKGATE_CON(76), 4, GFLAGS), 1623 GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0, 1624 RK3588_CLKGATE_CON(76), 5, GFLAGS), 1625 1626 /* vdec */ 1627 COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0, 1628 RK3588_CLKSEL_CON(89), 0, 2, MFLAGS, 1629 RK3588_CLKGATE_CON(40), 0, GFLAGS), 1630 COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0, 1631 RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS, 1632 RK3588_CLKGATE_CON(40), 1, GFLAGS), 1633 COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0, 1634 RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS, 1635 RK3588_CLKGATE_CON(40), 2, GFLAGS), 1636 COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0, 1637 RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS, 1638 RK3588_CLKGATE_CON(40), 7, GFLAGS), 1639 COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1640 RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS, 1641 RK3588_CLKGATE_CON(40), 8, GFLAGS), 1642 COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0, 1643 RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS, 1644 RK3588_CLKGATE_CON(40), 9, GFLAGS), 1645 COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0, 1646 RK3588_CLKSEL_CON(93), 0, 2, MFLAGS, 1647 RK3588_CLKGATE_CON(41), 0, GFLAGS), 1648 COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0, 1649 RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS, 1650 RK3588_CLKGATE_CON(41), 1, GFLAGS), 1651 COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0, 1652 RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS, 1653 RK3588_CLKGATE_CON(41), 6, GFLAGS), 1654 COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0, 1655 RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS, 1656 RK3588_CLKGATE_CON(41), 7, GFLAGS), 1657 COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0, 1658 RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS, 1659 RK3588_CLKGATE_CON(41), 8, GFLAGS), 1660 1661 /* sdio */ 1662 COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0, 1663 RK3588_CLKSEL_CON(172), 0, 2, MFLAGS, 1664 RK3588_CLKGATE_CON(75), 0, GFLAGS), 1665 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, 1666 RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS, 1667 RK3588_CLKGATE_CON(75), 3, GFLAGS), 1668 MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1), 1669 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1), 1670 1671 /* usb */ 1672 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0, 1673 RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS, 1674 RK3588_CLKGATE_CON(42), 0, GFLAGS), 1675 COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0, 1676 RK3588_CLKSEL_CON(96), 6, 2, MFLAGS, 1677 RK3588_CLKGATE_CON(42), 1, GFLAGS), 1678 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0, 1679 RK3588_CLKGATE_CON(42), 5, GFLAGS), 1680 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0, 1681 RK3588_CLKGATE_CON(42), 6, GFLAGS), 1682 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0, 1683 RK3588_CLKGATE_CON(42), 8, GFLAGS), 1684 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0, 1685 RK3588_CLKGATE_CON(42), 9, GFLAGS), 1686 1687 /* vdpu */ 1688 COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, 1689 RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, 1690 RK3588_CLKGATE_CON(44), 0, GFLAGS), 1691 COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, 1692 RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, 1693 RK3588_CLKGATE_CON(44), 1, GFLAGS), 1694 COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1695 RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, 1696 RK3588_CLKGATE_CON(44), 2, GFLAGS), 1697 COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, 1698 RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS, 1699 RK3588_CLKGATE_CON(44), 3, GFLAGS), 1700 GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0, 1701 RK3588_CLKGATE_CON(45), 4, GFLAGS), 1702 COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0, 1703 RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS, 1704 RK3588_CLKGATE_CON(45), 6, GFLAGS), 1705 GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0, 1706 RK3588_CLKGATE_CON(44), 11, GFLAGS), 1707 GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0, 1708 RK3588_CLKGATE_CON(44), 13, GFLAGS), 1709 GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0, 1710 RK3588_CLKGATE_CON(44), 15, GFLAGS), 1711 GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0, 1712 RK3588_CLKGATE_CON(45), 1, GFLAGS), 1713 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0, 1714 RK3588_CLKGATE_CON(45), 3, GFLAGS), 1715 GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0, 1716 RK3588_CLKGATE_CON(45), 7, GFLAGS), 1717 GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0, 1718 RK3588_CLKGATE_CON(45), 8, GFLAGS), 1719 COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0, 1720 RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS, 1721 RK3588_CLKGATE_CON(45), 9, GFLAGS), 1722 GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0, 1723 RK3588_CLKGATE_CON(45), 10, GFLAGS), 1724 GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0, 1725 RK3588_CLKGATE_CON(45), 11, GFLAGS), 1726 COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0, 1727 RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS, 1728 RK3588_CLKGATE_CON(45), 12, GFLAGS), 1729 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0, 1730 RK3588_CLKGATE_CON(44), 9, GFLAGS), 1731 1732 /* venc */ 1733 COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0, 1734 RK3588_CLKSEL_CON(104), 0, 2, MFLAGS, 1735 RK3588_CLKGATE_CON(48), 0, GFLAGS), 1736 COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0, 1737 RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS, 1738 RK3588_CLKGATE_CON(48), 1, GFLAGS), 1739 COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0, 1740 RK3588_CLKSEL_CON(102), 0, 2, MFLAGS, 1741 RK3588_CLKGATE_CON(47), 0, GFLAGS), 1742 COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, 1743 RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, 1744 RK3588_CLKGATE_CON(47), 1, GFLAGS), 1745 GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, 1746 RK3588_CLKGATE_CON(47), 4, GFLAGS), 1747 GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, 1748 RK3588_CLKGATE_CON(47), 5, GFLAGS), 1749 COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, 1750 RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, 1751 RK3588_CLKGATE_CON(47), 6, GFLAGS), 1752 COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0, 1753 RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS, 1754 RK3588_CLKGATE_CON(48), 6, GFLAGS), 1755 1756 /* vi */ 1757 COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, 1758 RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, 1759 RK3588_CLKGATE_CON(49), 0, GFLAGS), 1760 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1761 RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, 1762 RK3588_CLKGATE_CON(49), 1, GFLAGS), 1763 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, 1764 RK3588_CLKSEL_CON(106), 10, 2, MFLAGS, 1765 RK3588_CLKGATE_CON(49), 2, GFLAGS), 1766 COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, 1767 RK3588_CLKSEL_CON(108), 14, 2, MFLAGS, 1768 RK3588_CLKGATE_CON(51), 10, GFLAGS), 1769 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, 1770 RK3588_CLKGATE_CON(51), 11, GFLAGS), 1771 GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0, 1772 RK3588_CLKGATE_CON(51), 12, GFLAGS), 1773 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, 1774 RK3588_CLKGATE_CON(50), 4, GFLAGS), 1775 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, 1776 RK3588_CLKGATE_CON(50), 5, GFLAGS), 1777 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, 1778 RK3588_CLKGATE_CON(50), 6, GFLAGS), 1779 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, 1780 RK3588_CLKGATE_CON(50), 7, GFLAGS), 1781 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, 1782 RK3588_CLKGATE_CON(50), 8, GFLAGS), 1783 GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0, 1784 RK3588_CLKGATE_CON(50), 9, GFLAGS), 1785 GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0, 1786 RK3588_CLKGATE_CON(49), 14, GFLAGS), 1787 GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0, 1788 RK3588_CLKGATE_CON(49), 15, GFLAGS), 1789 COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0, 1790 RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, 1791 RK3588_CLKGATE_CON(50), 0, GFLAGS), 1792 GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0, 1793 RK3588_CLKGATE_CON(50), 1, GFLAGS), 1794 GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0, 1795 RK3588_CLKGATE_CON(50), 2, GFLAGS), 1796 COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0, 1797 RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS, 1798 RK3588_CLKGATE_CON(50), 3, GFLAGS), 1799 COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0, 1800 RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, 1801 RK3588_CLKGATE_CON(49), 9, GFLAGS), 1802 GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0, 1803 RK3588_CLKGATE_CON(49), 10, GFLAGS), 1804 GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0, 1805 RK3588_CLKGATE_CON(49), 11, GFLAGS), 1806 GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0, 1807 RK3588_CLKGATE_CON(49), 12, GFLAGS), 1808 GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0, 1809 RK3588_CLKGATE_CON(49), 13, GFLAGS), 1810 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, 1811 RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, 1812 RK3588_CLKGATE_CON(49), 6, GFLAGS), 1813 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, 1814 RK3588_CLKGATE_CON(49), 7, GFLAGS), 1815 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, 1816 RK3588_CLKGATE_CON(49), 8, GFLAGS), 1817 1818 /* vo0 */ 1819 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0, 1820 RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS, 1821 RK3588_CLKGATE_CON(55), 0, GFLAGS), 1822 COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0, 1823 RK3588_CLKSEL_CON(116), 6, 2, MFLAGS, 1824 RK3588_CLKGATE_CON(55), 1, GFLAGS), 1825 COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0, 1826 RK3588_CLKSEL_CON(116), 8, 2, MFLAGS, 1827 RK3588_CLKGATE_CON(55), 2, GFLAGS), 1828 COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0, 1829 RK3588_CLKSEL_CON(116), 10, 2, MFLAGS, 1830 RK3588_CLKGATE_CON(55), 3, GFLAGS), 1831 COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0, 1832 RK3588_CLKSEL_CON(116), 12, 2, MFLAGS, 1833 RK3588_CLKGATE_CON(55), 4, GFLAGS), 1834 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0, 1835 RK3588_CLKGATE_CON(56), 4, GFLAGS), 1836 GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0, 1837 RK3588_CLKGATE_CON(56), 5, GFLAGS), 1838 GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0, 1839 RK3588_CLKGATE_CON(56), 6, GFLAGS), 1840 GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0, 1841 RK3588_CLKGATE_CON(56), 7, GFLAGS), 1842 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0, 1843 RK3588_CLKGATE_CON(56), 8, GFLAGS), 1844 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0, 1845 RK3588_CLKGATE_CON(56), 9, GFLAGS), 1846 GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0, 1847 RK3588_CLKGATE_CON(55), 11, GFLAGS), 1848 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, 1849 RK3588_CLKGATE_CON(55), 14, GFLAGS), 1850 GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0, 1851 RK3588_CLKGATE_CON(56), 0, GFLAGS), 1852 GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, 1853 RK3588_CLKGATE_CON(56), 1, GFLAGS), 1854 COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, 1855 RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, 1856 RK3588_CLKGATE_CON(56), 11, GFLAGS), 1857 COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src", 1858 CLK_SET_RATE_PARENT, 1859 RK3588_CLKSEL_CON(119), 0, 1860 RK3588_CLKGATE_CON(56), 12, GFLAGS, 1861 &rk3588_i2s4_8ch_tx_fracmux), 1862 GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0, 1863 RK3588_CLKGATE_CON(56), 13, GFLAGS), 1864 COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0, 1865 RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS, 1866 RK3588_CLKGATE_CON(56), 15, GFLAGS), 1867 COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src", 1868 CLK_SET_RATE_PARENT, 1869 RK3588_CLKSEL_CON(121), 0, 1870 RK3588_CLKGATE_CON(57), 0, GFLAGS, 1871 &rk3588_i2s8_8ch_tx_fracmux), 1872 GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0, 1873 RK3588_CLKGATE_CON(57), 1, GFLAGS), 1874 COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0, 1875 RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS, 1876 RK3588_CLKGATE_CON(57), 3, GFLAGS), 1877 COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src", 1878 CLK_SET_RATE_PARENT, 1879 RK3588_CLKSEL_CON(123), 0, 1880 RK3588_CLKGATE_CON(57), 4, GFLAGS, 1881 &rk3588_spdif2_dp0_fracmux), 1882 GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0, 1883 RK3588_CLKGATE_CON(57), 5, GFLAGS), 1884 GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0, 1885 RK3588_CLKGATE_CON(57), 6, GFLAGS), 1886 COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0, 1887 RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, 1888 RK3588_CLKGATE_CON(57), 8, GFLAGS), 1889 COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src", 1890 CLK_SET_RATE_PARENT, 1891 RK3588_CLKSEL_CON(125), 0, 1892 RK3588_CLKGATE_CON(57), 9, GFLAGS, 1893 &rk3588_spdif5_dp1_fracmux), 1894 GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0, 1895 RK3588_CLKGATE_CON(57), 10, GFLAGS), 1896 GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0, 1897 RK3588_CLKGATE_CON(57), 11, GFLAGS), 1898 COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0, 1899 RK3588_CLKSEL_CON(117), 0, 8, DFLAGS, 1900 RK3588_CLKGATE_CON(56), 2, GFLAGS), 1901 COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0, 1902 RK3588_CLKSEL_CON(117), 8, 8, DFLAGS, 1903 RK3588_CLKGATE_CON(56), 3, GFLAGS), 1904 1905 /* vo1 */ 1906 COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0, 1907 RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS, 1908 RK3588_CLKGATE_CON(65), 9, GFLAGS), 1909 COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0, 1910 RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS, 1911 RK3588_CLKGATE_CON(59), 0, GFLAGS), 1912 COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0, 1913 RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS, 1914 RK3588_CLKGATE_CON(59), 1, GFLAGS), 1915 COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0, 1916 RK3588_CLKSEL_CON(128), 13, 2, MFLAGS, 1917 RK3588_CLKGATE_CON(59), 2, GFLAGS), 1918 COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0, 1919 RK3588_CLKSEL_CON(129), 0, 2, MFLAGS, 1920 RK3588_CLKGATE_CON(59), 3, GFLAGS), 1921 COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0, 1922 RK3588_CLKSEL_CON(129), 2, 2, MFLAGS, 1923 RK3588_CLKGATE_CON(59), 4, GFLAGS), 1924 COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0, 1925 RK3588_CLKSEL_CON(129), 4, 2, MFLAGS, 1926 RK3588_CLKGATE_CON(59), 5, GFLAGS), 1927 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, 1928 RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, 1929 RK3588_CLKGATE_CON(52), 0, GFLAGS), 1930 COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, 1931 RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, 1932 RK3588_CLKGATE_CON(52), 1, GFLAGS), 1933 COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1934 RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, 1935 RK3588_CLKGATE_CON(52), 2, GFLAGS), 1936 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, 1937 RK3588_CLKSEL_CON(110), 12, 2, MFLAGS, 1938 RK3588_CLKGATE_CON(52), 3, GFLAGS), 1939 COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL, 1940 RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS, 1941 RK3588_CLKGATE_CON(74), 0, GFLAGS), 1942 COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 1943 RK3588_CLKSEL_CON(170), 6, 2, MFLAGS, 1944 RK3588_CLKGATE_CON(74), 2, GFLAGS), 1945 MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT, 1946 RK3588_CLKSEL_CON(115), 9, 1, MFLAGS), 1947 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0, 1948 RK3588_CLKGATE_CON(62), 0, GFLAGS), 1949 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, 1950 RK3588_CLKGATE_CON(62), 1, GFLAGS), 1951 COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, 1952 RK3588_CLKSEL_CON(140), 1, 2, MFLAGS, 1953 RK3588_CLKGATE_CON(62), 2, GFLAGS), 1954 GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0, 1955 RK3588_CLKGATE_CON(62), 3, GFLAGS), 1956 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0, 1957 RK3588_CLKGATE_CON(62), 4, GFLAGS), 1958 COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0, 1959 RK3588_CLKSEL_CON(140), 3, 2, MFLAGS, 1960 RK3588_CLKGATE_CON(62), 5, GFLAGS), 1961 GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0, 1962 RK3588_CLKGATE_CON(60), 4, GFLAGS), 1963 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, 1964 RK3588_CLKGATE_CON(60), 7, GFLAGS), 1965 GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0, 1966 RK3588_CLKGATE_CON(61), 9, GFLAGS), 1967 GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0, 1968 RK3588_CLKGATE_CON(61), 10, GFLAGS), 1969 GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0, 1970 RK3588_CLKGATE_CON(61), 11, GFLAGS), 1971 COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0, 1972 RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS, 1973 RK3588_CLKGATE_CON(61), 12, GFLAGS), 1974 COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src", 1975 CLK_SET_RATE_PARENT, 1976 RK3588_CLKSEL_CON(139), 0, 1977 RK3588_CLKGATE_CON(61), 13, GFLAGS, 1978 &rk3588_hdmirx_aud_fracmux), 1979 GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0, 1980 RK3588_CLKGATE_CON(61), 14, GFLAGS), 1981 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0, 1982 RK3588_CLKGATE_CON(60), 11, GFLAGS), 1983 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, 1984 RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS, 1985 RK3588_CLKGATE_CON(60), 15, GFLAGS), 1986 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0, 1987 RK3588_CLKGATE_CON(61), 0, GFLAGS), 1988 GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0, 1989 RK3588_CLKGATE_CON(61), 2, GFLAGS), 1990 COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0, 1991 RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS, 1992 RK3588_CLKGATE_CON(61), 6, GFLAGS), 1993 GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0, 1994 RK3588_CLKGATE_CON(61), 7, GFLAGS), 1995 GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0, 1996 RK3588_CLKGATE_CON(60), 9, GFLAGS), 1997 GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, 1998 RK3588_CLKGATE_CON(60), 10, GFLAGS), 1999 GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, 2000 RK3588_CLKGATE_CON(59), 14, GFLAGS), 2001 GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, 2002 RK3588_CLKGATE_CON(59), 15, GFLAGS), 2003 GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0, 2004 RK3588_CLKGATE_CON(65), 8, GFLAGS), 2005 COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0, 2006 RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS, 2007 RK3588_CLKGATE_CON(65), 5, GFLAGS), 2008 COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src", 2009 CLK_SET_RATE_PARENT, 2010 RK3588_CLKSEL_CON(156), 0, 2011 RK3588_CLKGATE_CON(65), 6, GFLAGS, 2012 &rk3588_i2s10_8ch_rx_fracmux), 2013 GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0, 2014 RK3588_CLKGATE_CON(65), 7, GFLAGS), 2015 COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0, 2016 RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS, 2017 RK3588_CLKGATE_CON(60), 1, GFLAGS), 2018 COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src", 2019 CLK_SET_RATE_PARENT, 2020 RK3588_CLKSEL_CON(130), 0, 2021 RK3588_CLKGATE_CON(60), 2, GFLAGS, 2022 &rk3588_i2s7_8ch_rx_fracmux), 2023 GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0, 2024 RK3588_CLKGATE_CON(60), 3, GFLAGS), 2025 COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0, 2026 RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS, 2027 RK3588_CLKGATE_CON(65), 1, GFLAGS), 2028 COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src", 2029 CLK_SET_RATE_PARENT, 2030 RK3588_CLKSEL_CON(154), 0, 2031 RK3588_CLKGATE_CON(65), 2, GFLAGS, 2032 &rk3588_i2s9_8ch_rx_fracmux), 2033 GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0, 2034 RK3588_CLKGATE_CON(65), 3, GFLAGS), 2035 COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0, 2036 RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS, 2037 RK3588_CLKGATE_CON(62), 6, GFLAGS), 2038 COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0, 2039 RK3588_CLKSEL_CON(141), 0, 2040 RK3588_CLKGATE_CON(62), 7, GFLAGS, 2041 &rk3588_i2s5_8ch_tx_fracmux), 2042 GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0, 2043 RK3588_CLKGATE_CON(62), 8, GFLAGS), 2044 COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0, 2045 RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS, 2046 RK3588_CLKGATE_CON(62), 13, GFLAGS), 2047 COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src", 2048 CLK_SET_RATE_PARENT, 2049 RK3588_CLKSEL_CON(145), 0, 2050 RK3588_CLKGATE_CON(62), 14, GFLAGS, 2051 &rk3588_i2s6_8ch_tx_fracmux), 2052 GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0, 2053 RK3588_CLKGATE_CON(62), 15, GFLAGS), 2054 COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0, 2055 RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS, 2056 RK3588_CLKGATE_CON(63), 0, GFLAGS), 2057 COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0, 2058 RK3588_CLKSEL_CON(147), 0, 2059 RK3588_CLKGATE_CON(63), 1, GFLAGS, 2060 &rk3588_i2s6_8ch_rx_fracmux), 2061 GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0, 2062 RK3588_CLKGATE_CON(63), 2, GFLAGS), 2063 MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2064 RK3588_CLKSEL_CON(148), 2, 2, MFLAGS), 2065 COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0, 2066 RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS, 2067 RK3588_CLKGATE_CON(63), 5, GFLAGS), 2068 COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src", 2069 CLK_SET_RATE_PARENT, 2070 RK3588_CLKSEL_CON(149), 0, 2071 RK3588_CLKGATE_CON(63), 6, GFLAGS, 2072 &rk3588_spdif3_fracmux), 2073 GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0, 2074 RK3588_CLKGATE_CON(63), 7, GFLAGS), 2075 COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0, 2076 RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS, 2077 RK3588_CLKGATE_CON(63), 9, GFLAGS), 2078 COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src", 2079 CLK_SET_RATE_PARENT, 2080 RK3588_CLKSEL_CON(151), 0, 2081 RK3588_CLKGATE_CON(63), 10, GFLAGS, 2082 &rk3588_spdif4_fracmux), 2083 GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0, 2084 RK3588_CLKGATE_CON(63), 11, GFLAGS), 2085 COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0, 2086 RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS, 2087 RK3588_CLKGATE_CON(63), 13, GFLAGS), 2088 COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0, 2089 RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS, 2090 RK3588_CLKGATE_CON(63), 15, GFLAGS), 2091 COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0, 2092 RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS, 2093 RK3588_CLKGATE_CON(64), 1, GFLAGS), 2094 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, 2095 RK3588_CLKGATE_CON(73), 12, GFLAGS), 2096 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0, 2097 RK3588_CLKGATE_CON(73), 13, GFLAGS), 2098 GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0, 2099 RK3588_CLKGATE_CON(72), 5, GFLAGS), 2100 GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0, 2101 RK3588_CLKGATE_CON(72), 6, GFLAGS), 2102 GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0, 2103 RK3588_CLKGATE_CON(72), 2, GFLAGS), 2104 GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0, 2105 RK3588_CLKGATE_CON(72), 4, GFLAGS), 2106 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, 2107 RK3588_CLKGATE_CON(52), 8, GFLAGS), 2108 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0, 2109 RK3588_CLKGATE_CON(52), 9, GFLAGS), 2110 COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0, 2111 RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS, 2112 RK3588_CLKGATE_CON(52), 10, GFLAGS), 2113 COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, 2114 RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, 2115 RK3588_CLKGATE_CON(52), 11, GFLAGS), 2116 COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2117 RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, 2118 RK3588_CLKGATE_CON(52), 12, GFLAGS), 2119 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 2120 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2121 RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, 2122 RK3588_CLKGATE_CON(52), 13, GFLAGS), 2123 COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 2124 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2125 RK3588_CLKSEL_CON(112), 9, 2, MFLAGS, 2126 RK3588_CLKGATE_CON(53), 0, GFLAGS), 2127 COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p, 2128 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2129 RK3588_CLKSEL_CON(112), 11, 2, MFLAGS, 2130 RK3588_CLKGATE_CON(53), 1, GFLAGS), 2131 COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0, 2132 RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS, 2133 RK3588_CLKGATE_CON(53), 2, GFLAGS), 2134 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0, 2135 RK3588_CLKGATE_CON(53), 4, GFLAGS), 2136 GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0, 2137 RK3588_CLKGATE_CON(53), 5, GFLAGS), 2138 COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0, 2139 RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS, 2140 RK3588_CLKGATE_CON(53), 6, GFLAGS), 2141 COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0, 2142 RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS, 2143 RK3588_CLKGATE_CON(53), 7, GFLAGS), 2144 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED, 2145 RK3588_CLKGATE_CON(53), 8, GFLAGS), 2146 GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0, 2147 RK3588_CLKGATE_CON(53), 10, GFLAGS), 2148 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED, 2149 RK3588_CLKGATE_CON(2), 8, GFLAGS), 2150 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED, 2151 RK3588_CLKGATE_CON(2), 15, GFLAGS), 2152 2153 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0, 2154 RK3588_CLKGATE_CON(77), 0, GFLAGS), 2155 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0, 2156 RK3588_CLKGATE_CON(77), 1, GFLAGS), 2157 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0, 2158 RK3588_CLKGATE_CON(77), 2, GFLAGS), 2159 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0, 2160 RK3588_CLKSEL_CON(176), 0, 6, DFLAGS, 2161 RK3588_CLKGATE_CON(77), 3, GFLAGS), 2162 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0, 2163 RK3588_CLKSEL_CON(176), 6, 6, DFLAGS, 2164 RK3588_CLKGATE_CON(77), 4, GFLAGS), 2165 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0, 2166 RK3588_CLKSEL_CON(177), 0, 6, DFLAGS, 2167 RK3588_CLKGATE_CON(77), 5, GFLAGS), 2168 MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT, 2169 RK3588_CLKSEL_CON(177), 6, 1, MFLAGS), 2170 MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT, 2171 RK3588_CLKSEL_CON(177), 7, 1, MFLAGS), 2172 MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT, 2173 RK3588_CLKSEL_CON(177), 8, 1, MFLAGS), 2174 2175 /* pmu */ 2176 COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0, 2177 RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS, 2178 RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS), 2179 COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0, 2180 RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, 2181 RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS), 2182 COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0, 2183 RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS, 2184 RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS), 2185 COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0, 2186 RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS, 2187 RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS), 2188 COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0, 2189 RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS, 2190 RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS), 2191 COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL, 2192 RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 2193 RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS), 2194 COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL, 2195 RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS, 2196 RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS), 2197 GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL, 2198 RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS), 2199 COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL, 2200 RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS, 2201 RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS), 2202 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL, 2203 RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS), 2204 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, 2205 RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS), 2206 GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL, 2207 RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS), 2208 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, 2209 RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS), 2210 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, 2211 RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS, 2212 RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS), 2213 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0, 2214 RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS), 2215 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0, 2216 RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS, 2217 RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS), 2218 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0, 2219 RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS), 2220 COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0, 2221 RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS, 2222 RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS), 2223 COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", 2224 CLK_SET_RATE_PARENT, 2225 RK3588_PMU_CLKSEL_CON(6), 0, 2226 RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS, 2227 &rk3588_i2s1_8ch_tx_fracmux), 2228 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0, 2229 RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS), 2230 COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0, 2231 RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS, 2232 RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS), 2233 COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", 2234 CLK_SET_RATE_PARENT, 2235 RK3588_PMU_CLKSEL_CON(8), 0, 2236 RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS, 2237 &rk3588_i2s1_8ch_rx_fracmux), 2238 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0, 2239 RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS), 2240 MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT, 2241 RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS), 2242 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL, 2243 RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS), 2244 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED, 2245 RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS), 2246 GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL, 2247 RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS), 2248 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, 2249 RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS), 2250 COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0, 2251 RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS, 2252 RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS), 2253 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, 2254 RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS), 2255 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL, 2256 RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS), 2257 COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, 2258 RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, 2259 RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS), 2260 GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED, 2261 RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS), 2262 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0, 2263 RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS), 2264 COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0, 2265 RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS, 2266 RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS), 2267 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0, 2268 RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS), 2269 GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0, 2270 RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS), 2271 COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0, 2272 RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS, 2273 RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS), 2274 GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0, 2275 RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS), 2276 GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0, 2277 RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS), 2278 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0, 2279 RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS, 2280 RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS), 2281 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, 2282 RK3588_PMU_CLKSEL_CON(4), 0, 2283 RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS, 2284 &rk3588_uart0_fracmux), 2285 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, 2286 RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS), 2287 GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0, 2288 RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS), 2289 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0, 2290 RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS), 2291 COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, 2292 RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 2293 RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS), 2294 COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0, 2295 RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS, 2296 RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS), 2297 COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, 2298 CLK_IS_CRITICAL, 2299 RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS, 2300 RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS), 2301 COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p, 2302 CLK_IS_CRITICAL, 2303 RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS, 2304 RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS), 2305 2306 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0, 2307 RK3588_PHYREF_ALT_GATE, 0, GFLAGS), 2308 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0, 2309 RK3588_PHYREF_ALT_GATE, 1, GFLAGS), 2310 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0, 2311 RK3588_PHYREF_ALT_GATE, 2, GFLAGS), 2312 GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0, 2313 RK3588_PHYREF_ALT_GATE, 3, GFLAGS), 2314 2315 GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0, 2316 RK3588_CLKGATE_CON(63), 12, GFLAGS), 2317 GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0, 2318 RK3588_CLKGATE_CON(63), 14, GFLAGS), 2319 GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0, 2320 RK3588_CLKGATE_CON(64), 0, GFLAGS), 2321 GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0, 2322 RK3588_CLKGATE_CON(63), 8, GFLAGS), 2323 GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0, 2324 RK3588_CLKGATE_CON(63), 4, GFLAGS), 2325 GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0, 2326 RK3588_CLKGATE_CON(63), 3, GFLAGS), 2327 GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0, 2328 RK3588_CLKGATE_CON(62), 12, GFLAGS), 2329 GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0, 2330 RK3588_CLKGATE_CON(65), 0, GFLAGS), 2331 GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0, 2332 RK3588_CLKGATE_CON(60), 0, GFLAGS), 2333 GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0, 2334 RK3588_CLKGATE_CON(65), 4, GFLAGS), 2335 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0, 2336 RK3588_CLKGATE_CON(60), 5, GFLAGS), 2337 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0, 2338 RK3588_CLKGATE_CON(60), 6, GFLAGS), 2339 GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0, 2340 RK3588_CLKGATE_CON(57), 7, GFLAGS), 2341 GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0, 2342 RK3588_CLKGATE_CON(57), 2, GFLAGS), 2343 GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0, 2344 RK3588_CLKGATE_CON(56), 14, GFLAGS), 2345 GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0, 2346 RK3588_CLKGATE_CON(56), 10, GFLAGS), 2347 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0, 2348 RK3588_CLKGATE_CON(55), 12, GFLAGS), 2349 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0, 2350 RK3588_CLKGATE_CON(55), 13, GFLAGS), 2351 GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0, 2352 RK3588_CLKGATE_CON(48), 4, GFLAGS), 2353 GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0, 2354 RK3588_CLKGATE_CON(48), 5, GFLAGS), 2355 GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0, 2356 RK3588_CLKGATE_CON(44), 8, GFLAGS), 2357 GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0, 2358 RK3588_CLKGATE_CON(45), 5, GFLAGS), 2359 GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0, 2360 RK3588_CLKGATE_CON(44), 10, GFLAGS), 2361 GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0, 2362 RK3588_CLKGATE_CON(44), 12, GFLAGS), 2363 GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0, 2364 RK3588_CLKGATE_CON(44), 14, GFLAGS), 2365 GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0, 2366 RK3588_CLKGATE_CON(45), 0, GFLAGS), 2367 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0, 2368 RK3588_CLKGATE_CON(45), 2, GFLAGS), 2369 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0, 2370 RK3588_CLKGATE_CON(42), 7, GFLAGS), 2371 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0, 2372 RK3588_CLKGATE_CON(42), 10, GFLAGS), 2373 GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0, 2374 RK3588_CLKGATE_CON(42), 11, GFLAGS), 2375 GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0, 2376 RK3588_CLKGATE_CON(42), 12, GFLAGS), 2377 GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0, 2378 RK3588_CLKGATE_CON(42), 13, GFLAGS), 2379 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0, 2380 RK3588_CLKGATE_CON(42), 4, GFLAGS), 2381 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1), 2382 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1), 2383 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0, 2384 RK3588_CLKGATE_CON(75), 2, GFLAGS), 2385 GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0, 2386 RK3588_CLKGATE_CON(41), 2, GFLAGS), 2387 GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0, 2388 RK3588_CLKGATE_CON(41), 3, GFLAGS), 2389 GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0, 2390 RK3588_CLKGATE_CON(40), 3, GFLAGS), 2391 GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0, 2392 RK3588_CLKGATE_CON(40), 4, GFLAGS), 2393 GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0, 2394 RK3588_CLKGATE_CON(39), 0, GFLAGS), 2395 GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0, 2396 RK3588_CLKGATE_CON(39), 1, GFLAGS), 2397 GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0, 2398 RK3588_CLKGATE_CON(38), 3, GFLAGS), 2399 GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0, 2400 RK3588_CLKGATE_CON(38), 4, GFLAGS), 2401 GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0, 2402 RK3588_CLKGATE_CON(38), 5, GFLAGS), 2403 GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0, 2404 RK3588_CLKGATE_CON(38), 6, GFLAGS), 2405 GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0, 2406 RK3588_CLKGATE_CON(38), 7, GFLAGS), 2407 GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0, 2408 RK3588_CLKGATE_CON(38), 8, GFLAGS), 2409 GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0, 2410 RK3588_CLKGATE_CON(38), 9, GFLAGS), 2411 GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0, 2412 RK3588_CLKGATE_CON(38), 13, GFLAGS), 2413 GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0, 2414 RK3588_CLKGATE_CON(38), 14, GFLAGS), 2415 GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0, 2416 RK3588_CLKGATE_CON(38), 15, GFLAGS), 2417 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0, 2418 RK3588_CLKGATE_CON(31), 10, GFLAGS), 2419 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0, 2420 RK3588_CLKGATE_CON(31), 11, GFLAGS), 2421 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0, 2422 RK3588_CLKGATE_CON(31), 4, GFLAGS), 2423 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0, 2424 RK3588_CLKGATE_CON(26), 5, GFLAGS), 2425 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0, 2426 RK3588_CLKGATE_CON(26), 7, GFLAGS), 2427 GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0, 2428 RK3588_CLKGATE_CON(68), 5, GFLAGS), 2429 GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, 2430 RK3588_CLKGATE_CON(68), 2, GFLAGS), 2431 2432 GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), 2433 GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), 2434 GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), 2435 GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), 2436 GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), 2437 GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), 2438 GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS), 2439 GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS), 2440 GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS), 2441 GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS), 2442 GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS), 2443 GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), 2444 GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), 2445 GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), 2446 GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), 2447 GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), 2448 GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), 2449 GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), 2450 GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), 2451 GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), 2452 GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), 2453 GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), 2454 }; 2455 2456 static void __init rk3588_clk_init(struct device_node *np) 2457 { 2458 struct rockchip_clk_provider *ctx; 2459 unsigned long clk_nr_clks; 2460 void __iomem *reg_base; 2461 2462 clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, 2463 ARRAY_SIZE(rk3588_clk_branches)) + 1; 2464 reg_base = of_iomap(np, 0); 2465 if (!reg_base) { 2466 pr_err("%s: could not map cru region\n", __func__); 2467 return; 2468 } 2469 2470 ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); 2471 if (IS_ERR(ctx)) { 2472 pr_err("%s: rockchip clk init failed\n", __func__); 2473 iounmap(reg_base); 2474 return; 2475 } 2476 2477 rockchip_clk_register_plls(ctx, rk3588_pll_clks, 2478 ARRAY_SIZE(rk3588_pll_clks), 2479 RK3588_GRF_SOC_STATUS0); 2480 2481 rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", 2482 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 2483 &rk3588_cpulclk_data, rk3588_cpulclk_rates, 2484 ARRAY_SIZE(rk3588_cpulclk_rates)); 2485 rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", 2486 mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), 2487 &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, 2488 ARRAY_SIZE(rk3588_cpub0clk_rates)); 2489 rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", 2490 mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), 2491 &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, 2492 ARRAY_SIZE(rk3588_cpub1clk_rates)); 2493 2494 rockchip_clk_register_branches(ctx, rk3588_clk_branches, 2495 ARRAY_SIZE(rk3588_clk_branches)); 2496 2497 rk3588_rst_init(np, reg_base); 2498 2499 rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); 2500 2501 rockchip_clk_of_add_provider(np, ctx); 2502 } 2503 2504 CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); 2505 2506 struct clk_rk3588_inits { 2507 void (*inits)(struct device_node *np); 2508 }; 2509 2510 static const struct clk_rk3588_inits clk_3588_cru_init = { 2511 .inits = rk3588_clk_init, 2512 }; 2513 2514 static const struct of_device_id clk_rk3588_match_table[] = { 2515 { 2516 .compatible = "rockchip,rk3588-cru", 2517 .data = &clk_3588_cru_init, 2518 }, 2519 { } 2520 }; 2521 2522 static int __init clk_rk3588_probe(struct platform_device *pdev) 2523 { 2524 const struct clk_rk3588_inits *init_data; 2525 struct device *dev = &pdev->dev; 2526 2527 init_data = device_get_match_data(dev); 2528 if (!init_data) 2529 return -EINVAL; 2530 2531 if (init_data->inits) 2532 init_data->inits(dev->of_node); 2533 2534 return 0; 2535 } 2536 2537 static struct platform_driver clk_rk3588_driver = { 2538 .driver = { 2539 .name = "clk-rk3588", 2540 .of_match_table = clk_rk3588_match_table, 2541 .suppress_bind_attrs = true, 2542 }, 2543 }; 2544 builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); 2545