111551005SXing Zheng /* 211551005SXing Zheng * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 311551005SXing Zheng * Author: Xing Zheng <zhengxing@rock-chips.com> 411551005SXing Zheng * 511551005SXing Zheng * This program is free software; you can redistribute it and/or modify 611551005SXing Zheng * it under the terms of the GNU General Public License as published by 711551005SXing Zheng * the Free Software Foundation; either version 2 of the License, or 811551005SXing Zheng * (at your option) any later version. 911551005SXing Zheng * 1011551005SXing Zheng * This program is distributed in the hope that it will be useful, 1111551005SXing Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 1211551005SXing Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1311551005SXing Zheng * GNU General Public License for more details. 1411551005SXing Zheng */ 1511551005SXing Zheng 1611551005SXing Zheng #include <linux/clk-provider.h> 1711551005SXing Zheng #include <linux/of.h> 1811551005SXing Zheng #include <linux/of_address.h> 1911551005SXing Zheng #include <linux/platform_device.h> 2011551005SXing Zheng #include <linux/regmap.h> 2111551005SXing Zheng #include <dt-bindings/clock/rk3399-cru.h> 2211551005SXing Zheng #include "clk.h" 2311551005SXing Zheng 2411551005SXing Zheng enum rk3399_plls { 2511551005SXing Zheng lpll, bpll, dpll, cpll, gpll, npll, vpll, 2611551005SXing Zheng }; 2711551005SXing Zheng 2811551005SXing Zheng enum rk3399_pmu_plls { 2911551005SXing Zheng ppll, 3011551005SXing Zheng }; 3111551005SXing Zheng 3211551005SXing Zheng static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 3311551005SXing Zheng /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 3411551005SXing Zheng RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 3511551005SXing Zheng RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 3611551005SXing Zheng RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 3711551005SXing Zheng RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 3811551005SXing Zheng RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 3911551005SXing Zheng RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 4011551005SXing Zheng RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 4111551005SXing Zheng RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 4211551005SXing Zheng RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 4311551005SXing Zheng RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 4411551005SXing Zheng RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 4511551005SXing Zheng RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 4611551005SXing Zheng RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 4711551005SXing Zheng RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 4811551005SXing Zheng RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 4911551005SXing Zheng RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 5011551005SXing Zheng RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 5111551005SXing Zheng RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 5211551005SXing Zheng RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 5311551005SXing Zheng RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 5411551005SXing Zheng RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 5511551005SXing Zheng RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 5611551005SXing Zheng RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 5711551005SXing Zheng RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 5811551005SXing Zheng RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 5911551005SXing Zheng RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 6011551005SXing Zheng RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 6111551005SXing Zheng RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 6211551005SXing Zheng RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 6311551005SXing Zheng RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 6411551005SXing Zheng RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 6511551005SXing Zheng RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 6611551005SXing Zheng RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 6711551005SXing Zheng RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 6811551005SXing Zheng RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 6911551005SXing Zheng RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 7011551005SXing Zheng RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 7111551005SXing Zheng RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 7211551005SXing Zheng RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 7311551005SXing Zheng RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 7411551005SXing Zheng RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 7511551005SXing Zheng RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 7611551005SXing Zheng RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 7711551005SXing Zheng RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 7811551005SXing Zheng RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 7911551005SXing Zheng RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 8011551005SXing Zheng RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 8111551005SXing Zheng RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 8211551005SXing Zheng RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 8311551005SXing Zheng RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 8411551005SXing Zheng RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 8511551005SXing Zheng RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 8611551005SXing Zheng RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 8711551005SXing Zheng RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 8811551005SXing Zheng RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 8911551005SXing Zheng RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 9011551005SXing Zheng RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 9111551005SXing Zheng RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 9211551005SXing Zheng RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 9311551005SXing Zheng RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 9411551005SXing Zheng RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 9511551005SXing Zheng RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 9611551005SXing Zheng RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 9711551005SXing Zheng RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 9811551005SXing Zheng RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 9911551005SXing Zheng RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 10011551005SXing Zheng RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 10111551005SXing Zheng RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 10211551005SXing Zheng { /* sentinel */ }, 10311551005SXing Zheng }; 10411551005SXing Zheng 10511551005SXing Zheng /* CRU parents */ 10611551005SXing Zheng PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 10711551005SXing Zheng 10811551005SXing Zheng PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", 10911551005SXing Zheng "clk_core_l_bpll_src", 11011551005SXing Zheng "clk_core_l_dpll_src", 11111551005SXing Zheng "clk_core_l_gpll_src" }; 11211551005SXing Zheng PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", 11311551005SXing Zheng "clk_core_b_bpll_src", 11411551005SXing Zheng "clk_core_b_dpll_src", 11511551005SXing Zheng "clk_core_b_gpll_src" }; 11611551005SXing Zheng PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", 11711551005SXing Zheng "gpll_aclk_cci_src", 11811551005SXing Zheng "npll_aclk_cci_src", 11911551005SXing Zheng "vpll_aclk_cci_src" }; 120995d3fdeSHeiko Stuebner PNAME(mux_cci_trace_p) = { "cpll_cci_trace", 121995d3fdeSHeiko Stuebner "gpll_cci_trace" }; 122995d3fdeSHeiko Stuebner PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", 123995d3fdeSHeiko Stuebner "npll_cs"}; 124995d3fdeSHeiko Stuebner PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", 125995d3fdeSHeiko Stuebner "gpll_aclk_perihp_src" }; 12611551005SXing Zheng 12711551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 12811551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 12911551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; 13011551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; 13111551005SXing Zheng PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 132995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", 133995d3fdeSHeiko Stuebner "ppll" }; 134995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", 135995d3fdeSHeiko Stuebner "xin24m" }; 136995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", 137995d3fdeSHeiko Stuebner "clk_usbphy_480m" }; 138995d3fdeSHeiko Stuebner PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", 139995d3fdeSHeiko Stuebner "npll", "upll" }; 140995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", 141995d3fdeSHeiko Stuebner "upll", "xin24m" }; 142995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", 143995d3fdeSHeiko Stuebner "ppll", "upll", "xin24m" }; 14411551005SXing Zheng 14511551005SXing Zheng PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; 146995d3fdeSHeiko Stuebner PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", 147995d3fdeSHeiko Stuebner "npll" }; 148995d3fdeSHeiko Stuebner PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", 149995d3fdeSHeiko Stuebner "xin24m" }; 15011551005SXing Zheng 151995d3fdeSHeiko Stuebner PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", 152995d3fdeSHeiko Stuebner "dclk_vop0_frac" }; 153995d3fdeSHeiko Stuebner PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", 154995d3fdeSHeiko Stuebner "dclk_vop1_frac" }; 15511551005SXing Zheng 15611551005SXing Zheng PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" }; 15711551005SXing Zheng 15811551005SXing Zheng PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 15911551005SXing Zheng PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 160995d3fdeSHeiko Stuebner PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", 161995d3fdeSHeiko Stuebner "cpll", "gpll" }; 162995d3fdeSHeiko Stuebner PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", 163995d3fdeSHeiko Stuebner "clk_pcie_core_phy" }; 16411551005SXing Zheng 165995d3fdeSHeiko Stuebner PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", 166995d3fdeSHeiko Stuebner "gpll_aclk_emmc_src" }; 16711551005SXing Zheng 168995d3fdeSHeiko Stuebner PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", 169995d3fdeSHeiko Stuebner "gpll_aclk_perilp0_src" }; 17011551005SXing Zheng 171995d3fdeSHeiko Stuebner PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", 172995d3fdeSHeiko Stuebner "gpll_fclk_cm0s_src" }; 17311551005SXing Zheng 174995d3fdeSHeiko Stuebner PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", 175995d3fdeSHeiko Stuebner "gpll_hclk_perilp1_src" }; 17611551005SXing Zheng 17711551005SXing Zheng PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 17811551005SXing Zheng PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 17911551005SXing Zheng 180995d3fdeSHeiko Stuebner PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", 181995d3fdeSHeiko Stuebner "clk_usbphy1_480m_src" }; 182995d3fdeSHeiko Stuebner PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", 183995d3fdeSHeiko Stuebner "gpll_aclk_gmac_src" }; 18411551005SXing Zheng PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 18511551005SXing Zheng PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 18611551005SXing Zheng "clkin_i2s", "xin12m" }; 18711551005SXing Zheng PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 18811551005SXing Zheng "clkin_i2s", "xin12m" }; 18911551005SXing Zheng PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 19011551005SXing Zheng "clkin_i2s", "xin12m" }; 19111551005SXing Zheng PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 19211551005SXing Zheng "clkin_i2s", "xin12m" }; 193995d3fdeSHeiko Stuebner PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", 194995d3fdeSHeiko Stuebner "clk_i2s2" }; 19511551005SXing Zheng PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 19611551005SXing Zheng 19711551005SXing Zheng PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 19811551005SXing Zheng PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 19911551005SXing Zheng PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 20011551005SXing Zheng PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 20111551005SXing Zheng 20211551005SXing Zheng /* PMU CRU parents */ 20311551005SXing Zheng PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 20411551005SXing Zheng PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 20511551005SXing Zheng PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 20611551005SXing Zheng PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 207995d3fdeSHeiko Stuebner PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", 208995d3fdeSHeiko Stuebner "xin24m" }; 20911551005SXing Zheng PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 21011551005SXing Zheng 21111551005SXing Zheng static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { 21211551005SXing Zheng [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), 21311551005SXing Zheng RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), 21411551005SXing Zheng [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), 21511551005SXing Zheng RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), 21611551005SXing Zheng [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), 21711551005SXing Zheng RK3399_PLL_CON(19), 8, 31, 0, NULL), 21811551005SXing Zheng [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), 21911551005SXing Zheng RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 22011551005SXing Zheng [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), 22111551005SXing Zheng RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 22211551005SXing Zheng [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), 22311551005SXing Zheng RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 22411551005SXing Zheng [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), 22511551005SXing Zheng RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 22611551005SXing Zheng }; 22711551005SXing Zheng 22811551005SXing Zheng static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { 22911551005SXing Zheng [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), 23011551005SXing Zheng RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 23111551005SXing Zheng }; 23211551005SXing Zheng 23311551005SXing Zheng #define MFLAGS CLK_MUX_HIWORD_MASK 23411551005SXing Zheng #define DFLAGS CLK_DIVIDER_HIWORD_MASK 23511551005SXing Zheng #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 23611551005SXing Zheng #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 23711551005SXing Zheng 23811551005SXing Zheng static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = 23911551005SXing Zheng MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, 24011551005SXing Zheng RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); 24111551005SXing Zheng 24211551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = 24311551005SXing Zheng MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, 24411551005SXing Zheng RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); 24511551005SXing Zheng 24611551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = 24711551005SXing Zheng MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 24811551005SXing Zheng RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); 24911551005SXing Zheng 25011551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = 25111551005SXing Zheng MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 25211551005SXing Zheng RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); 25311551005SXing Zheng 25411551005SXing Zheng static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = 25511551005SXing Zheng MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 25611551005SXing Zheng RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); 25711551005SXing Zheng 25811551005SXing Zheng static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = 25911551005SXing Zheng MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 26011551005SXing Zheng RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); 26111551005SXing Zheng 26211551005SXing Zheng static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = 26311551005SXing Zheng MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 26411551005SXing Zheng RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); 26511551005SXing Zheng 26611551005SXing Zheng static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = 26711551005SXing Zheng MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 26811551005SXing Zheng RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); 26911551005SXing Zheng 27011551005SXing Zheng static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = 27111551005SXing Zheng MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, 27211551005SXing Zheng RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); 27311551005SXing Zheng 27411551005SXing Zheng static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = 27511551005SXing Zheng MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, 27611551005SXing Zheng RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); 27711551005SXing Zheng 27811551005SXing Zheng static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = 27911551005SXing Zheng MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, 28011551005SXing Zheng RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); 28111551005SXing Zheng 28211551005SXing Zheng static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = 28311551005SXing Zheng MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 28411551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); 28511551005SXing Zheng 28611551005SXing Zheng static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { 28711551005SXing Zheng .core_reg = RK3399_CLKSEL_CON(0), 28811551005SXing Zheng .div_core_shift = 0, 28911551005SXing Zheng .div_core_mask = 0x1f, 29011551005SXing Zheng .mux_core_alt = 3, 29111551005SXing Zheng .mux_core_main = 0, 29211551005SXing Zheng .mux_core_shift = 6, 29311551005SXing Zheng .mux_core_mask = 0x3, 29411551005SXing Zheng }; 29511551005SXing Zheng 29611551005SXing Zheng static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { 29711551005SXing Zheng .core_reg = RK3399_CLKSEL_CON(2), 29811551005SXing Zheng .div_core_shift = 0, 29911551005SXing Zheng .div_core_mask = 0x1f, 30011551005SXing Zheng .mux_core_alt = 3, 30111551005SXing Zheng .mux_core_main = 1, 30211551005SXing Zheng .mux_core_shift = 6, 30311551005SXing Zheng .mux_core_mask = 0x3, 30411551005SXing Zheng }; 30511551005SXing Zheng 30611551005SXing Zheng #define RK3399_DIV_ACLKM_MASK 0x1f 30711551005SXing Zheng #define RK3399_DIV_ACLKM_SHIFT 8 30811551005SXing Zheng #define RK3399_DIV_ATCLK_MASK 0x1f 30911551005SXing Zheng #define RK3399_DIV_ATCLK_SHIFT 0 31011551005SXing Zheng #define RK3399_DIV_PCLK_DBG_MASK 0x1f 31111551005SXing Zheng #define RK3399_DIV_PCLK_DBG_SHIFT 8 31211551005SXing Zheng 31311551005SXing Zheng #define RK3399_CLKSEL0(_offs, _aclkm) \ 31411551005SXing Zheng { \ 31511551005SXing Zheng .reg = RK3399_CLKSEL_CON(0 + _offs), \ 31611551005SXing Zheng .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ 31711551005SXing Zheng RK3399_DIV_ACLKM_SHIFT), \ 31811551005SXing Zheng } 31911551005SXing Zheng #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ 32011551005SXing Zheng { \ 32111551005SXing Zheng .reg = RK3399_CLKSEL_CON(1 + _offs), \ 32211551005SXing Zheng .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ 32311551005SXing Zheng RK3399_DIV_ATCLK_SHIFT) | \ 32411551005SXing Zheng HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ 32511551005SXing Zheng RK3399_DIV_PCLK_DBG_SHIFT), \ 32611551005SXing Zheng } 32711551005SXing Zheng 32811551005SXing Zheng /* cluster_l: aclkm in clksel0, rest in clksel1 */ 32911551005SXing Zheng #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ 33011551005SXing Zheng { \ 33111551005SXing Zheng .prate = _prate##U, \ 33211551005SXing Zheng .divs = { \ 33311551005SXing Zheng RK3399_CLKSEL0(0, _aclkm), \ 33411551005SXing Zheng RK3399_CLKSEL1(0, _atclk, _pdbg), \ 33511551005SXing Zheng }, \ 33611551005SXing Zheng } 33711551005SXing Zheng 33811551005SXing Zheng /* cluster_b: aclkm in clksel2, rest in clksel3 */ 33911551005SXing Zheng #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ 34011551005SXing Zheng { \ 34111551005SXing Zheng .prate = _prate##U, \ 34211551005SXing Zheng .divs = { \ 34311551005SXing Zheng RK3399_CLKSEL0(2, _aclkm), \ 34411551005SXing Zheng RK3399_CLKSEL1(2, _atclk, _pdbg), \ 34511551005SXing Zheng }, \ 34611551005SXing Zheng } 34711551005SXing Zheng 34811551005SXing Zheng static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { 34911551005SXing Zheng RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), 35011551005SXing Zheng RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), 35111551005SXing Zheng RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), 35211551005SXing Zheng RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), 35311551005SXing Zheng RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), 35411551005SXing Zheng RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), 35511551005SXing Zheng RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), 35611551005SXing Zheng RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), 35711551005SXing Zheng RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), 35811551005SXing Zheng RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), 35911551005SXing Zheng RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), 36011551005SXing Zheng RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), 36111551005SXing Zheng RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), 36211551005SXing Zheng }; 36311551005SXing Zheng 36411551005SXing Zheng static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { 36511551005SXing Zheng RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), 36611551005SXing Zheng RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), 36711551005SXing Zheng RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), 36811551005SXing Zheng RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), 36911551005SXing Zheng RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), 37011551005SXing Zheng RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), 37111551005SXing Zheng RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), 37211551005SXing Zheng RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), 37311551005SXing Zheng RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), 37411551005SXing Zheng RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), 37511551005SXing Zheng RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), 37611551005SXing Zheng RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), 37711551005SXing Zheng RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), 37811551005SXing Zheng RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), 37911551005SXing Zheng RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), 38011551005SXing Zheng RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), 38111551005SXing Zheng RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), 38211551005SXing Zheng RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), 38311551005SXing Zheng RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), 38411551005SXing Zheng }; 38511551005SXing Zheng 38611551005SXing Zheng static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 38711551005SXing Zheng /* 38811551005SXing Zheng * CRU Clock-Architecture 38911551005SXing Zheng */ 39011551005SXing Zheng 39111551005SXing Zheng /* usbphy */ 39211551005SXing Zheng GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, 39311551005SXing Zheng RK3399_CLKGATE_CON(6), 5, GFLAGS), 39411551005SXing Zheng GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, 39511551005SXing Zheng RK3399_CLKGATE_CON(6), 6, GFLAGS), 39611551005SXing Zheng 39711551005SXing Zheng GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED, 39811551005SXing Zheng RK3399_CLKGATE_CON(13), 12, GFLAGS), 39911551005SXing Zheng GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED, 40011551005SXing Zheng RK3399_CLKGATE_CON(13), 12, GFLAGS), 40111551005SXing Zheng MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED, 40211551005SXing Zheng RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), 40311551005SXing Zheng 40411551005SXing Zheng MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, 40511551005SXing Zheng RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), 40611551005SXing Zheng 40711551005SXing Zheng COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, CLK_IGNORE_UNUSED, 40811551005SXing Zheng RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, 40911551005SXing Zheng RK3399_CLKGATE_CON(6), 4, GFLAGS), 41011551005SXing Zheng 41111551005SXing Zheng COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 41211551005SXing Zheng RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, 41311551005SXing Zheng RK3399_CLKGATE_CON(12), 0, GFLAGS), 41411551005SXing Zheng GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, 41511551005SXing Zheng RK3399_CLKGATE_CON(30), 0, GFLAGS), 41611551005SXing Zheng GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLK_IGNORE_UNUSED, 41711551005SXing Zheng RK3399_CLKGATE_CON(30), 1, GFLAGS), 41811551005SXing Zheng GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLK_IGNORE_UNUSED, 41911551005SXing Zheng RK3399_CLKGATE_CON(30), 2, GFLAGS), 42011551005SXing Zheng GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLK_IGNORE_UNUSED, 42111551005SXing Zheng RK3399_CLKGATE_CON(30), 3, GFLAGS), 42211551005SXing Zheng GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLK_IGNORE_UNUSED, 42311551005SXing Zheng RK3399_CLKGATE_CON(30), 4, GFLAGS), 42411551005SXing Zheng 42511551005SXing Zheng GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLK_IGNORE_UNUSED, 42611551005SXing Zheng RK3399_CLKGATE_CON(12), 1, GFLAGS), 42711551005SXing Zheng GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLK_IGNORE_UNUSED, 42811551005SXing Zheng RK3399_CLKGATE_CON(12), 2, GFLAGS), 42911551005SXing Zheng 43011551005SXing Zheng COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, CLK_IGNORE_UNUSED, 43111551005SXing Zheng RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, 43211551005SXing Zheng RK3399_CLKGATE_CON(12), 3, GFLAGS), 43311551005SXing Zheng 43411551005SXing Zheng COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, CLK_IGNORE_UNUSED, 43511551005SXing Zheng RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, 43611551005SXing Zheng RK3399_CLKGATE_CON(12), 4, GFLAGS), 43711551005SXing Zheng 43811551005SXing Zheng COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED, 43911551005SXing Zheng RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, 44011551005SXing Zheng RK3399_CLKGATE_CON(13), 4, GFLAGS), 44111551005SXing Zheng 44211551005SXing Zheng COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED, 44311551005SXing Zheng RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, 44411551005SXing Zheng RK3399_CLKGATE_CON(13), 5, GFLAGS), 44511551005SXing Zheng 44611551005SXing Zheng COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED, 44711551005SXing Zheng RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, 44811551005SXing Zheng RK3399_CLKGATE_CON(13), 6, GFLAGS), 44911551005SXing Zheng 45011551005SXing Zheng COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED, 45111551005SXing Zheng RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, 45211551005SXing Zheng RK3399_CLKGATE_CON(13), 7, GFLAGS), 45311551005SXing Zheng 45411551005SXing Zheng /* little core */ 45511551005SXing Zheng GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, 45611551005SXing Zheng RK3399_CLKGATE_CON(0), 0, GFLAGS), 45711551005SXing Zheng GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, 45811551005SXing Zheng RK3399_CLKGATE_CON(0), 1, GFLAGS), 45911551005SXing Zheng GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, 46011551005SXing Zheng RK3399_CLKGATE_CON(0), 2, GFLAGS), 46111551005SXing Zheng GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, 46211551005SXing Zheng RK3399_CLKGATE_CON(0), 3, GFLAGS), 46311551005SXing Zheng 46411551005SXing Zheng COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, 46511551005SXing Zheng RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 46611551005SXing Zheng RK3399_CLKGATE_CON(0), 4, GFLAGS), 46711551005SXing Zheng COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, 46811551005SXing Zheng RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 46911551005SXing Zheng RK3399_CLKGATE_CON(0), 5, GFLAGS), 47011551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, 47111551005SXing Zheng RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 47211551005SXing Zheng RK3399_CLKGATE_CON(0), 6, GFLAGS), 47311551005SXing Zheng 47411551005SXing Zheng GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, 47511551005SXing Zheng RK3399_CLKGATE_CON(14), 12, GFLAGS), 47611551005SXing Zheng GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, 47711551005SXing Zheng RK3399_CLKGATE_CON(14), 13, GFLAGS), 47811551005SXing Zheng 47911551005SXing Zheng GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, 48011551005SXing Zheng RK3399_CLKGATE_CON(14), 9, GFLAGS), 48111551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, 48211551005SXing Zheng RK3399_CLKGATE_CON(14), 10, GFLAGS), 48311551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, 48411551005SXing Zheng RK3399_CLKGATE_CON(14), 11, GFLAGS), 48511551005SXing Zheng GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED, 48611551005SXing Zheng RK3399_CLKGATE_CON(0), 7, GFLAGS), 48711551005SXing Zheng 48811551005SXing Zheng /* big core */ 48911551005SXing Zheng GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, 49011551005SXing Zheng RK3399_CLKGATE_CON(1), 0, GFLAGS), 49111551005SXing Zheng GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, 49211551005SXing Zheng RK3399_CLKGATE_CON(1), 1, GFLAGS), 49311551005SXing Zheng GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, 49411551005SXing Zheng RK3399_CLKGATE_CON(1), 2, GFLAGS), 49511551005SXing Zheng GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, 49611551005SXing Zheng RK3399_CLKGATE_CON(1), 3, GFLAGS), 49711551005SXing Zheng 49811551005SXing Zheng COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, 49911551005SXing Zheng RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 50011551005SXing Zheng RK3399_CLKGATE_CON(1), 4, GFLAGS), 50111551005SXing Zheng COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, 50211551005SXing Zheng RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 50311551005SXing Zheng RK3399_CLKGATE_CON(1), 5, GFLAGS), 50411551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, 50511551005SXing Zheng RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 50611551005SXing Zheng RK3399_CLKGATE_CON(1), 6, GFLAGS), 50711551005SXing Zheng 50811551005SXing Zheng GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, 50911551005SXing Zheng RK3399_CLKGATE_CON(14), 5, GFLAGS), 51011551005SXing Zheng GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, 51111551005SXing Zheng RK3399_CLKGATE_CON(14), 6, GFLAGS), 51211551005SXing Zheng 51311551005SXing Zheng GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, 51411551005SXing Zheng RK3399_CLKGATE_CON(14), 1, GFLAGS), 51511551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, 51611551005SXing Zheng RK3399_CLKGATE_CON(14), 3, GFLAGS), 51711551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, 51811551005SXing Zheng RK3399_CLKGATE_CON(14), 4, GFLAGS), 51911551005SXing Zheng 52011551005SXing Zheng DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 52111551005SXing Zheng RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), 52211551005SXing Zheng 52311551005SXing Zheng GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 52411551005SXing Zheng RK3399_CLKGATE_CON(14), 2, GFLAGS), 52511551005SXing Zheng 52611551005SXing Zheng GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED, 52711551005SXing Zheng RK3399_CLKGATE_CON(1), 7, GFLAGS), 52811551005SXing Zheng 52911551005SXing Zheng /* gmac */ 53011551005SXing Zheng GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, 53111551005SXing Zheng RK3399_CLKGATE_CON(6), 9, GFLAGS), 53211551005SXing Zheng GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, 53311551005SXing Zheng RK3399_CLKGATE_CON(6), 8, GFLAGS), 53411551005SXing Zheng COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, CLK_IGNORE_UNUSED, 53511551005SXing Zheng RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, 53611551005SXing Zheng RK3399_CLKGATE_CON(6), 10, GFLAGS), 53711551005SXing Zheng 53811551005SXing Zheng GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 53911551005SXing Zheng RK3399_CLKGATE_CON(32), 0, GFLAGS), 54011551005SXing Zheng GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 54111551005SXing Zheng RK3399_CLKGATE_CON(32), 1, GFLAGS), 54211551005SXing Zheng GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 54311551005SXing Zheng RK3399_CLKGATE_CON(32), 4, GFLAGS), 54411551005SXing Zheng 54511551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 54611551005SXing Zheng RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, 54711551005SXing Zheng RK3399_CLKGATE_CON(6), 11, GFLAGS), 54811551005SXing Zheng GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 54911551005SXing Zheng RK3399_CLKGATE_CON(32), 2, GFLAGS), 55011551005SXing Zheng GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 55111551005SXing Zheng RK3399_CLKGATE_CON(32), 3, GFLAGS), 55211551005SXing Zheng 55311551005SXing Zheng COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 55411551005SXing Zheng RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 55511551005SXing Zheng RK3399_CLKGATE_CON(5), 5, GFLAGS), 55611551005SXing Zheng 557*3f92a054SXing Zheng MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, 55811551005SXing Zheng RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), 55911551005SXing Zheng GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED, 56011551005SXing Zheng RK3399_CLKGATE_CON(5), 6, GFLAGS), 56111551005SXing Zheng GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLK_IGNORE_UNUSED, 56211551005SXing Zheng RK3399_CLKGATE_CON(5), 7, GFLAGS), 56311551005SXing Zheng GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLK_IGNORE_UNUSED, 56411551005SXing Zheng RK3399_CLKGATE_CON(5), 8, GFLAGS), 56511551005SXing Zheng GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLK_IGNORE_UNUSED, 56611551005SXing Zheng RK3399_CLKGATE_CON(5), 9, GFLAGS), 56711551005SXing Zheng 56811551005SXing Zheng /* spdif */ 56911551005SXing Zheng COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 57011551005SXing Zheng RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, 57111551005SXing Zheng RK3399_CLKGATE_CON(8), 13, GFLAGS), 57211551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, 57311551005SXing Zheng RK3399_CLKSEL_CON(99), 0, 57411551005SXing Zheng RK3399_CLKGATE_CON(8), 14, GFLAGS, 57511551005SXing Zheng &rk3399_spdif_fracmux), 57611551005SXing Zheng GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, 57711551005SXing Zheng RK3399_CLKGATE_CON(8), 15, GFLAGS), 57811551005SXing Zheng 57911551005SXing Zheng COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 58011551005SXing Zheng RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, 58111551005SXing Zheng RK3399_CLKGATE_CON(10), 6, GFLAGS), 58211551005SXing Zheng /* i2s */ 58311551005SXing Zheng COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 58411551005SXing Zheng RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, 58511551005SXing Zheng RK3399_CLKGATE_CON(8), 3, GFLAGS), 58611551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, 58711551005SXing Zheng RK3399_CLKSEL_CON(96), 0, 58811551005SXing Zheng RK3399_CLKGATE_CON(8), 4, GFLAGS, 58911551005SXing Zheng &rk3399_i2s0_fracmux), 59011551005SXing Zheng GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, 59111551005SXing Zheng RK3399_CLKGATE_CON(8), 5, GFLAGS), 59211551005SXing Zheng 59311551005SXing Zheng COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 59411551005SXing Zheng RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, 59511551005SXing Zheng RK3399_CLKGATE_CON(8), 6, GFLAGS), 59611551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, 59711551005SXing Zheng RK3399_CLKSEL_CON(97), 0, 59811551005SXing Zheng RK3399_CLKGATE_CON(8), 7, GFLAGS, 59911551005SXing Zheng &rk3399_i2s1_fracmux), 60011551005SXing Zheng GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 60111551005SXing Zheng RK3399_CLKGATE_CON(8), 8, GFLAGS), 60211551005SXing Zheng 60311551005SXing Zheng COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 60411551005SXing Zheng RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, 60511551005SXing Zheng RK3399_CLKGATE_CON(8), 9, GFLAGS), 60611551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, 60711551005SXing Zheng RK3399_CLKSEL_CON(98), 0, 60811551005SXing Zheng RK3399_CLKGATE_CON(8), 10, GFLAGS, 60911551005SXing Zheng &rk3399_i2s2_fracmux), 61011551005SXing Zheng GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 61111551005SXing Zheng RK3399_CLKGATE_CON(8), 11, GFLAGS), 61211551005SXing Zheng 61311551005SXing Zheng MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, 61411551005SXing Zheng RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), 61511551005SXing Zheng COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, 61611551005SXing Zheng RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, 61711551005SXing Zheng RK3399_CLKGATE_CON(8), 12, GFLAGS), 61811551005SXing Zheng 61911551005SXing Zheng /* uart */ 62011551005SXing Zheng MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, 62111551005SXing Zheng RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), 62211551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, 62311551005SXing Zheng RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, 62411551005SXing Zheng RK3399_CLKGATE_CON(9), 0, GFLAGS), 62511551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, 62611551005SXing Zheng RK3399_CLKSEL_CON(100), 0, 62711551005SXing Zheng RK3399_CLKGATE_CON(9), 1, GFLAGS, 62811551005SXing Zheng &rk3399_uart0_fracmux), 62911551005SXing Zheng 63011551005SXing Zheng MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, 63111551005SXing Zheng RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), 63211551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, 63311551005SXing Zheng RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, 63411551005SXing Zheng RK3399_CLKGATE_CON(9), 2, GFLAGS), 63511551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, 63611551005SXing Zheng RK3399_CLKSEL_CON(101), 0, 63711551005SXing Zheng RK3399_CLKGATE_CON(9), 3, GFLAGS, 63811551005SXing Zheng &rk3399_uart1_fracmux), 63911551005SXing Zheng 64011551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, 64111551005SXing Zheng RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, 64211551005SXing Zheng RK3399_CLKGATE_CON(9), 4, GFLAGS), 64311551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, 64411551005SXing Zheng RK3399_CLKSEL_CON(102), 0, 64511551005SXing Zheng RK3399_CLKGATE_CON(9), 5, GFLAGS, 64611551005SXing Zheng &rk3399_uart2_fracmux), 64711551005SXing Zheng 64811551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, 64911551005SXing Zheng RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, 65011551005SXing Zheng RK3399_CLKGATE_CON(9), 6, GFLAGS), 65111551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT, 65211551005SXing Zheng RK3399_CLKSEL_CON(103), 0, 65311551005SXing Zheng RK3399_CLKGATE_CON(9), 7, GFLAGS, 65411551005SXing Zheng &rk3399_uart3_fracmux), 65511551005SXing Zheng 65611551005SXing Zheng COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 65711551005SXing Zheng RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, 65811551005SXing Zheng RK3399_CLKGATE_CON(3), 4, GFLAGS), 65911551005SXing Zheng 66011551005SXing Zheng GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, 66111551005SXing Zheng RK3399_CLKGATE_CON(18), 10, GFLAGS), 66211551005SXing Zheng GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, 66311551005SXing Zheng RK3399_CLKGATE_CON(18), 12, GFLAGS), 66411551005SXing Zheng GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, 66511551005SXing Zheng RK3399_CLKGATE_CON(18), 15, GFLAGS), 66611551005SXing Zheng GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, 66711551005SXing Zheng RK3399_CLKGATE_CON(19), 2, GFLAGS), 66811551005SXing Zheng 66911551005SXing Zheng GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED, 67011551005SXing Zheng RK3399_CLKGATE_CON(4), 11, GFLAGS), 67111551005SXing Zheng GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED, 67211551005SXing Zheng RK3399_CLKGATE_CON(3), 5, GFLAGS), 67311551005SXing Zheng GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED, 67411551005SXing Zheng RK3399_CLKGATE_CON(3), 6, GFLAGS), 67511551005SXing Zheng 67611551005SXing Zheng /* cci */ 67711551005SXing Zheng GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, 67811551005SXing Zheng RK3399_CLKGATE_CON(2), 0, GFLAGS), 67911551005SXing Zheng GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, 68011551005SXing Zheng RK3399_CLKGATE_CON(2), 1, GFLAGS), 68111551005SXing Zheng GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, 68211551005SXing Zheng RK3399_CLKGATE_CON(2), 2, GFLAGS), 68311551005SXing Zheng GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, 68411551005SXing Zheng RK3399_CLKGATE_CON(2), 3, GFLAGS), 68511551005SXing Zheng 68611551005SXing Zheng COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, 68711551005SXing Zheng RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, 68811551005SXing Zheng RK3399_CLKGATE_CON(2), 4, GFLAGS), 68911551005SXing Zheng 69011551005SXing Zheng GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, 69111551005SXing Zheng RK3399_CLKGATE_CON(15), 0, GFLAGS), 69211551005SXing Zheng GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, 69311551005SXing Zheng RK3399_CLKGATE_CON(15), 1, GFLAGS), 69411551005SXing Zheng GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, 69511551005SXing Zheng RK3399_CLKGATE_CON(15), 2, GFLAGS), 69611551005SXing Zheng GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, 69711551005SXing Zheng RK3399_CLKGATE_CON(15), 3, GFLAGS), 69811551005SXing Zheng GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, 69911551005SXing Zheng RK3399_CLKGATE_CON(15), 4, GFLAGS), 70011551005SXing Zheng GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, 70111551005SXing Zheng RK3399_CLKGATE_CON(15), 7, GFLAGS), 70211551005SXing Zheng 70311551005SXing Zheng GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, 70411551005SXing Zheng RK3399_CLKGATE_CON(2), 5, GFLAGS), 70511551005SXing Zheng GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, 70611551005SXing Zheng RK3399_CLKGATE_CON(2), 6, GFLAGS), 70711551005SXing Zheng COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, 70811551005SXing Zheng RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, 70911551005SXing Zheng RK3399_CLKGATE_CON(2), 7, GFLAGS), 71011551005SXing Zheng 71111551005SXing Zheng GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, 71211551005SXing Zheng RK3399_CLKGATE_CON(2), 8, GFLAGS), 71311551005SXing Zheng GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, 71411551005SXing Zheng RK3399_CLKGATE_CON(2), 9, GFLAGS), 71511551005SXing Zheng GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, 71611551005SXing Zheng RK3399_CLKGATE_CON(2), 10, GFLAGS), 71711551005SXing Zheng COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, 71811551005SXing Zheng RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), 71911551005SXing Zheng GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, 72011551005SXing Zheng RK3399_CLKGATE_CON(15), 5, GFLAGS), 72111551005SXing Zheng GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, 72211551005SXing Zheng RK3399_CLKGATE_CON(15), 6, GFLAGS), 72311551005SXing Zheng 72411551005SXing Zheng /* vcodec */ 72511551005SXing Zheng COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 72611551005SXing Zheng RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, 72711551005SXing Zheng RK3399_CLKGATE_CON(4), 0, GFLAGS), 72811551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 72911551005SXing Zheng RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, 73011551005SXing Zheng RK3399_CLKGATE_CON(4), 1, GFLAGS), 73111551005SXing Zheng GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, 73211551005SXing Zheng RK3399_CLKGATE_CON(17), 2, GFLAGS), 73311551005SXing Zheng GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, 73411551005SXing Zheng RK3399_CLKGATE_CON(17), 3, GFLAGS), 73511551005SXing Zheng 73611551005SXing Zheng GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, 73711551005SXing Zheng RK3399_CLKGATE_CON(17), 0, GFLAGS), 73811551005SXing Zheng GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, 73911551005SXing Zheng RK3399_CLKGATE_CON(17), 1, GFLAGS), 74011551005SXing Zheng 74111551005SXing Zheng /* vdu */ 74211551005SXing Zheng COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 74311551005SXing Zheng RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 74411551005SXing Zheng RK3399_CLKGATE_CON(4), 4, GFLAGS), 74511551005SXing Zheng COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 74611551005SXing Zheng RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, 74711551005SXing Zheng RK3399_CLKGATE_CON(4), 5, GFLAGS), 74811551005SXing Zheng 74911551005SXing Zheng COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 75011551005SXing Zheng RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, 75111551005SXing Zheng RK3399_CLKGATE_CON(4), 2, GFLAGS), 75211551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, 75311551005SXing Zheng RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, 75411551005SXing Zheng RK3399_CLKGATE_CON(4), 3, GFLAGS), 75511551005SXing Zheng GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", CLK_IGNORE_UNUSED, 75611551005SXing Zheng RK3399_CLKGATE_CON(17), 10, GFLAGS), 75711551005SXing Zheng GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, 75811551005SXing Zheng RK3399_CLKGATE_CON(17), 11, GFLAGS), 75911551005SXing Zheng 76011551005SXing Zheng GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", CLK_IGNORE_UNUSED, 76111551005SXing Zheng RK3399_CLKGATE_CON(17), 8, GFLAGS), 76211551005SXing Zheng GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, 76311551005SXing Zheng RK3399_CLKGATE_CON(17), 9, GFLAGS), 76411551005SXing Zheng 76511551005SXing Zheng /* iep */ 76611551005SXing Zheng COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED, 76711551005SXing Zheng RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 76811551005SXing Zheng RK3399_CLKGATE_CON(4), 6, GFLAGS), 76911551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, 77011551005SXing Zheng RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, 77111551005SXing Zheng RK3399_CLKGATE_CON(4), 7, GFLAGS), 77211551005SXing Zheng GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", CLK_IGNORE_UNUSED, 77311551005SXing Zheng RK3399_CLKGATE_CON(16), 2, GFLAGS), 77411551005SXing Zheng GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, 77511551005SXing Zheng RK3399_CLKGATE_CON(16), 3, GFLAGS), 77611551005SXing Zheng 77711551005SXing Zheng GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", CLK_IGNORE_UNUSED, 77811551005SXing Zheng RK3399_CLKGATE_CON(16), 0, GFLAGS), 77911551005SXing Zheng GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, 78011551005SXing Zheng RK3399_CLKGATE_CON(16), 1, GFLAGS), 78111551005SXing Zheng 78211551005SXing Zheng /* rga */ 783*3f92a054SXing Zheng COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED, 78411551005SXing Zheng RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 78511551005SXing Zheng RK3399_CLKGATE_CON(4), 10, GFLAGS), 78611551005SXing Zheng 78711551005SXing Zheng COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED, 78811551005SXing Zheng RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 78911551005SXing Zheng RK3399_CLKGATE_CON(4), 8, GFLAGS), 79011551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, 79111551005SXing Zheng RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, 79211551005SXing Zheng RK3399_CLKGATE_CON(4), 9, GFLAGS), 79311551005SXing Zheng GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", CLK_IGNORE_UNUSED, 79411551005SXing Zheng RK3399_CLKGATE_CON(16), 10, GFLAGS), 79511551005SXing Zheng GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, 79611551005SXing Zheng RK3399_CLKGATE_CON(16), 11, GFLAGS), 79711551005SXing Zheng 79811551005SXing Zheng GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", CLK_IGNORE_UNUSED, 79911551005SXing Zheng RK3399_CLKGATE_CON(16), 8, GFLAGS), 80011551005SXing Zheng GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, 80111551005SXing Zheng RK3399_CLKGATE_CON(16), 9, GFLAGS), 80211551005SXing Zheng 80311551005SXing Zheng /* center */ 80411551005SXing Zheng COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 80511551005SXing Zheng RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 80611551005SXing Zheng RK3399_CLKGATE_CON(3), 7, GFLAGS), 80711551005SXing Zheng GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, 80811551005SXing Zheng RK3399_CLKGATE_CON(19), 0, GFLAGS), 80911551005SXing Zheng GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, 81011551005SXing Zheng RK3399_CLKGATE_CON(19), 1, GFLAGS), 81111551005SXing Zheng 81211551005SXing Zheng /* gpu */ 81311551005SXing Zheng COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 81411551005SXing Zheng RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, 81511551005SXing Zheng RK3399_CLKGATE_CON(13), 0, GFLAGS), 81611551005SXing Zheng GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED, 81711551005SXing Zheng RK3399_CLKGATE_CON(30), 8, GFLAGS), 81811551005SXing Zheng GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED, 81911551005SXing Zheng RK3399_CLKGATE_CON(30), 10, GFLAGS), 82011551005SXing Zheng GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLK_IGNORE_UNUSED, 82111551005SXing Zheng RK3399_CLKGATE_CON(30), 11, GFLAGS), 82211551005SXing Zheng GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", CLK_IGNORE_UNUSED, 82311551005SXing Zheng RK3399_CLKGATE_CON(13), 1, GFLAGS), 82411551005SXing Zheng 82511551005SXing Zheng /* perihp */ 82611551005SXing Zheng GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, 82711551005SXing Zheng RK3399_CLKGATE_CON(5), 0, GFLAGS), 82811551005SXing Zheng GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, 82911551005SXing Zheng RK3399_CLKGATE_CON(5), 1, GFLAGS), 83011551005SXing Zheng COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, 83111551005SXing Zheng RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, 83211551005SXing Zheng RK3399_CLKGATE_CON(5), 2, GFLAGS), 83311551005SXing Zheng COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 83411551005SXing Zheng RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, 83511551005SXing Zheng RK3399_CLKGATE_CON(5), 3, GFLAGS), 83611551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 83711551005SXing Zheng RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, 83811551005SXing Zheng RK3399_CLKGATE_CON(5), 4, GFLAGS), 83911551005SXing Zheng 84011551005SXing Zheng GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED, 84111551005SXing Zheng RK3399_CLKGATE_CON(20), 2, GFLAGS), 84211551005SXing Zheng GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED, 84311551005SXing Zheng RK3399_CLKGATE_CON(20), 10, GFLAGS), 84411551005SXing Zheng GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, 84511551005SXing Zheng RK3399_CLKGATE_CON(20), 12, GFLAGS), 84611551005SXing Zheng 84711551005SXing Zheng GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", CLK_IGNORE_UNUSED, 84811551005SXing Zheng RK3399_CLKGATE_CON(20), 5, GFLAGS), 84911551005SXing Zheng GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLK_IGNORE_UNUSED, 85011551005SXing Zheng RK3399_CLKGATE_CON(20), 6, GFLAGS), 85111551005SXing Zheng GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", CLK_IGNORE_UNUSED, 85211551005SXing Zheng RK3399_CLKGATE_CON(20), 7, GFLAGS), 85311551005SXing Zheng GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLK_IGNORE_UNUSED, 85411551005SXing Zheng RK3399_CLKGATE_CON(20), 8, GFLAGS), 85511551005SXing Zheng GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", CLK_IGNORE_UNUSED, 85611551005SXing Zheng RK3399_CLKGATE_CON(20), 9, GFLAGS), 85711551005SXing Zheng GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, 85811551005SXing Zheng RK3399_CLKGATE_CON(20), 13, GFLAGS), 85911551005SXing Zheng GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, 86011551005SXing Zheng RK3399_CLKGATE_CON(20), 15, GFLAGS), 86111551005SXing Zheng 86211551005SXing Zheng GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, 86311551005SXing Zheng RK3399_CLKGATE_CON(20), 4, GFLAGS), 86411551005SXing Zheng GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLK_IGNORE_UNUSED, 86511551005SXing Zheng RK3399_CLKGATE_CON(20), 11, GFLAGS), 86611551005SXing Zheng GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, 86711551005SXing Zheng RK3399_CLKGATE_CON(20), 14, GFLAGS), 86811551005SXing Zheng GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", CLK_IGNORE_UNUSED, 86911551005SXing Zheng RK3399_CLKGATE_CON(31), 8, GFLAGS), 87011551005SXing Zheng 87111551005SXing Zheng /* sdio & sdmmc */ 87211551005SXing Zheng COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 87311551005SXing Zheng RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, 87411551005SXing Zheng RK3399_CLKGATE_CON(12), 13, GFLAGS), 87511551005SXing Zheng GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLK_IGNORE_UNUSED, 87611551005SXing Zheng RK3399_CLKGATE_CON(33), 8, GFLAGS), 87711551005SXing Zheng GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, 87811551005SXing Zheng RK3399_CLKGATE_CON(33), 9, GFLAGS), 87911551005SXing Zheng 88011551005SXing Zheng COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED, 88111551005SXing Zheng RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, 88211551005SXing Zheng RK3399_CLKGATE_CON(6), 0, GFLAGS), 88311551005SXing Zheng 88411551005SXing Zheng COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED, 88511551005SXing Zheng RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, 88611551005SXing Zheng RK3399_CLKGATE_CON(6), 1, GFLAGS), 88711551005SXing Zheng 88811551005SXing Zheng MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), 88911551005SXing Zheng MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), 89011551005SXing Zheng 89111551005SXing Zheng MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), 89211551005SXing Zheng MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), 89311551005SXing Zheng 89411551005SXing Zheng /* pcie */ 89511551005SXing Zheng COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, CLK_IGNORE_UNUSED, 89611551005SXing Zheng RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, 89711551005SXing Zheng RK3399_CLKGATE_CON(6), 2, GFLAGS), 89811551005SXing Zheng 899*3f92a054SXing Zheng COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED, 90011551005SXing Zheng RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, 90111551005SXing Zheng RK3399_CLKGATE_CON(12), 6, GFLAGS), 90211551005SXing Zheng MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, 90311551005SXing Zheng RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), 90411551005SXing Zheng 90511551005SXing Zheng COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 90611551005SXing Zheng RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, 90711551005SXing Zheng RK3399_CLKGATE_CON(6), 3, GFLAGS), 90811551005SXing Zheng MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, 90911551005SXing Zheng RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), 91011551005SXing Zheng 91111551005SXing Zheng /* emmc */ 91211551005SXing Zheng COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, CLK_IGNORE_UNUSED, 91311551005SXing Zheng RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, 91411551005SXing Zheng RK3399_CLKGATE_CON(6), 14, GFLAGS), 91511551005SXing Zheng 91611551005SXing Zheng GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, 91711551005SXing Zheng RK3399_CLKGATE_CON(6), 12, GFLAGS), 91811551005SXing Zheng GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, 91911551005SXing Zheng RK3399_CLKGATE_CON(6), 13, GFLAGS), 92011551005SXing Zheng COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, 92111551005SXing Zheng RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), 92211551005SXing Zheng GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, 92311551005SXing Zheng RK3399_CLKGATE_CON(32), 8, GFLAGS), 92411551005SXing Zheng GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, 92511551005SXing Zheng RK3399_CLKGATE_CON(32), 9, GFLAGS), 92611551005SXing Zheng GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, 92711551005SXing Zheng RK3399_CLKGATE_CON(32), 10, GFLAGS), 92811551005SXing Zheng 92911551005SXing Zheng /* perilp0 */ 93011551005SXing Zheng GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, 93111551005SXing Zheng RK3399_CLKGATE_CON(7), 1, GFLAGS), 93211551005SXing Zheng GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, 93311551005SXing Zheng RK3399_CLKGATE_CON(7), 0, GFLAGS), 93411551005SXing Zheng COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, 93511551005SXing Zheng RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, 93611551005SXing Zheng RK3399_CLKGATE_CON(7), 2, GFLAGS), 93711551005SXing Zheng COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, 93811551005SXing Zheng RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, 93911551005SXing Zheng RK3399_CLKGATE_CON(7), 3, GFLAGS), 94011551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, 94111551005SXing Zheng RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, 94211551005SXing Zheng RK3399_CLKGATE_CON(7), 4, GFLAGS), 94311551005SXing Zheng 94411551005SXing Zheng /* aclk_perilp0 gates */ 94511551005SXing Zheng GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), 94611551005SXing Zheng GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), 94711551005SXing Zheng GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), 94811551005SXing Zheng GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), 94911551005SXing Zheng GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), 95011551005SXing Zheng GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), 95111551005SXing Zheng GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), 95211551005SXing Zheng GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), 95311551005SXing Zheng GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS), 95411551005SXing Zheng GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), 95511551005SXing Zheng GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), 95611551005SXing Zheng GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 7, GFLAGS), 95711551005SXing Zheng 95811551005SXing Zheng /* hclk_perilp0 gates */ 95911551005SXing Zheng GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), 96011551005SXing Zheng GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 5, GFLAGS), 96111551005SXing Zheng GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 6, GFLAGS), 96211551005SXing Zheng GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 14, GFLAGS), 96311551005SXing Zheng GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 15, GFLAGS), 96411551005SXing Zheng GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), 96511551005SXing Zheng 96611551005SXing Zheng /* pclk_perilp0 gates */ 96711551005SXing Zheng GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS), 96811551005SXing Zheng 96911551005SXing Zheng /* crypto */ 97011551005SXing Zheng COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 97111551005SXing Zheng RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, 97211551005SXing Zheng RK3399_CLKGATE_CON(7), 7, GFLAGS), 97311551005SXing Zheng 97411551005SXing Zheng COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 97511551005SXing Zheng RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, 97611551005SXing Zheng RK3399_CLKGATE_CON(7), 8, GFLAGS), 97711551005SXing Zheng 97811551005SXing Zheng /* cm0s_perilp */ 97911551005SXing Zheng GATE(0, "cpll_fclk_cm0s_src", "cpll", CLK_IGNORE_UNUSED, 98011551005SXing Zheng RK3399_CLKGATE_CON(7), 6, GFLAGS), 98111551005SXing Zheng GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED, 98211551005SXing Zheng RK3399_CLKGATE_CON(7), 5, GFLAGS), 98311551005SXing Zheng COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED, 98411551005SXing Zheng RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, 98511551005SXing Zheng RK3399_CLKGATE_CON(7), 9, GFLAGS), 98611551005SXing Zheng 98711551005SXing Zheng /* fclk_cm0s gates */ 98811551005SXing Zheng GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 8, GFLAGS), 98911551005SXing Zheng GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 9, GFLAGS), 99011551005SXing Zheng GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 10, GFLAGS), 99111551005SXing Zheng GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 11, GFLAGS), 99211551005SXing Zheng GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), 99311551005SXing Zheng 99411551005SXing Zheng /* perilp1 */ 99511551005SXing Zheng GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, 99611551005SXing Zheng RK3399_CLKGATE_CON(8), 1, GFLAGS), 99711551005SXing Zheng GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, 99811551005SXing Zheng RK3399_CLKGATE_CON(8), 0, GFLAGS), 99911551005SXing Zheng COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, 100011551005SXing Zheng RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), 100111551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, 100211551005SXing Zheng RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, 100311551005SXing Zheng RK3399_CLKGATE_CON(8), 2, GFLAGS), 100411551005SXing Zheng 100511551005SXing Zheng /* hclk_perilp1 gates */ 100611551005SXing Zheng GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), 100711551005SXing Zheng GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), 100811551005SXing Zheng GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 0, GFLAGS), 100911551005SXing Zheng GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 1, GFLAGS), 101011551005SXing Zheng GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 2, GFLAGS), 101111551005SXing Zheng GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 3, GFLAGS), 101211551005SXing Zheng GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 4, GFLAGS), 101311551005SXing Zheng GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 5, GFLAGS), 101411551005SXing Zheng GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), 101511551005SXing Zheng 101611551005SXing Zheng /* pclk_perilp1 gates */ 101711551005SXing Zheng GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), 101811551005SXing Zheng GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), 101911551005SXing Zheng GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), 102011551005SXing Zheng GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), 102111551005SXing Zheng GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), 102211551005SXing Zheng GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), 102311551005SXing Zheng GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), 102411551005SXing Zheng GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), 102511551005SXing Zheng GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), 102611551005SXing Zheng GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), 102711551005SXing Zheng GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), 102811551005SXing Zheng GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), 102911551005SXing Zheng GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), 103011551005SXing Zheng GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), 103111551005SXing Zheng GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), 103211551005SXing Zheng GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), 103311551005SXing Zheng GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), 103411551005SXing Zheng GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), 103511551005SXing Zheng GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), 103611551005SXing Zheng GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), 103711551005SXing Zheng GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), 103811551005SXing Zheng 103911551005SXing Zheng /* saradc */ 104011551005SXing Zheng COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 104111551005SXing Zheng RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, 104211551005SXing Zheng RK3399_CLKGATE_CON(9), 11, GFLAGS), 104311551005SXing Zheng 104411551005SXing Zheng /* tsadc */ 104511551005SXing Zheng COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, CLK_IGNORE_UNUSED, 104611551005SXing Zheng RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, 104711551005SXing Zheng RK3399_CLKGATE_CON(9), 10, GFLAGS), 104811551005SXing Zheng 104911551005SXing Zheng /* cif_testout */ 105011551005SXing Zheng MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 105111551005SXing Zheng RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), 105211551005SXing Zheng COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0, 105311551005SXing Zheng RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 105411551005SXing Zheng RK3399_CLKGATE_CON(13), 14, GFLAGS), 105511551005SXing Zheng 105611551005SXing Zheng MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 105711551005SXing Zheng RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), 105811551005SXing Zheng COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0, 105911551005SXing Zheng RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, 106011551005SXing Zheng RK3399_CLKGATE_CON(13), 15, GFLAGS), 106111551005SXing Zheng 106211551005SXing Zheng /* vio */ 106311551005SXing Zheng COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 106411551005SXing Zheng RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, 106511551005SXing Zheng RK3399_CLKGATE_CON(11), 10, GFLAGS), 106611551005SXing Zheng COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, 106711551005SXing Zheng RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, 106811551005SXing Zheng RK3399_CLKGATE_CON(11), 1, GFLAGS), 106911551005SXing Zheng 107011551005SXing Zheng GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, 107111551005SXing Zheng RK3399_CLKGATE_CON(29), 0, GFLAGS), 107211551005SXing Zheng 107311551005SXing Zheng GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", CLK_IGNORE_UNUSED, 107411551005SXing Zheng RK3399_CLKGATE_CON(29), 1, GFLAGS), 107511551005SXing Zheng GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", CLK_IGNORE_UNUSED, 107611551005SXing Zheng RK3399_CLKGATE_CON(29), 2, GFLAGS), 107711551005SXing Zheng GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, 107811551005SXing Zheng RK3399_CLKGATE_CON(29), 12, GFLAGS), 107911551005SXing Zheng 108011551005SXing Zheng /* hdcp */ 108111551005SXing Zheng COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 108211551005SXing Zheng RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, 108311551005SXing Zheng RK3399_CLKGATE_CON(11), 12, GFLAGS), 108411551005SXing Zheng COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED, 108511551005SXing Zheng RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, 108611551005SXing Zheng RK3399_CLKGATE_CON(11), 3, GFLAGS), 108711551005SXing Zheng COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED, 108811551005SXing Zheng RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, 108911551005SXing Zheng RK3399_CLKGATE_CON(11), 10, GFLAGS), 109011551005SXing Zheng 109111551005SXing Zheng GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, 109211551005SXing Zheng RK3399_CLKGATE_CON(29), 4, GFLAGS), 109311551005SXing Zheng GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", CLK_IGNORE_UNUSED, 109411551005SXing Zheng RK3399_CLKGATE_CON(29), 10, GFLAGS), 109511551005SXing Zheng 109611551005SXing Zheng GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, 109711551005SXing Zheng RK3399_CLKGATE_CON(29), 5, GFLAGS), 109811551005SXing Zheng GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", CLK_IGNORE_UNUSED, 109911551005SXing Zheng RK3399_CLKGATE_CON(29), 9, GFLAGS), 110011551005SXing Zheng 110111551005SXing Zheng GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, 110211551005SXing Zheng RK3399_CLKGATE_CON(29), 3, GFLAGS), 110311551005SXing Zheng GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED, 110411551005SXing Zheng RK3399_CLKGATE_CON(29), 6, GFLAGS), 110511551005SXing Zheng GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED, 110611551005SXing Zheng RK3399_CLKGATE_CON(29), 7, GFLAGS), 110711551005SXing Zheng GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", CLK_IGNORE_UNUSED, 110811551005SXing Zheng RK3399_CLKGATE_CON(29), 8, GFLAGS), 110911551005SXing Zheng GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", CLK_IGNORE_UNUSED, 111011551005SXing Zheng RK3399_CLKGATE_CON(29), 11, GFLAGS), 111111551005SXing Zheng 111211551005SXing Zheng /* edp */ 111311551005SXing Zheng COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, CLK_IGNORE_UNUSED, 111411551005SXing Zheng RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, 111511551005SXing Zheng RK3399_CLKGATE_CON(11), 8, GFLAGS), 111611551005SXing Zheng 111711551005SXing Zheng COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 111811551005SXing Zheng RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS, 111911551005SXing Zheng RK3399_CLKGATE_CON(11), 11, GFLAGS), 112011551005SXing Zheng GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, 112111551005SXing Zheng RK3399_CLKGATE_CON(32), 12, GFLAGS), 112211551005SXing Zheng GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLK_IGNORE_UNUSED, 112311551005SXing Zheng RK3399_CLKGATE_CON(32), 13, GFLAGS), 112411551005SXing Zheng 112511551005SXing Zheng /* hdmi */ 112611551005SXing Zheng GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLK_IGNORE_UNUSED, 112711551005SXing Zheng RK3399_CLKGATE_CON(11), 6, GFLAGS), 112811551005SXing Zheng 112911551005SXing Zheng COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, CLK_IGNORE_UNUSED, 113011551005SXing Zheng RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, 113111551005SXing Zheng RK3399_CLKGATE_CON(11), 7, GFLAGS), 113211551005SXing Zheng 113311551005SXing Zheng /* vop0 */ 113411551005SXing Zheng COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 113511551005SXing Zheng RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, 113611551005SXing Zheng RK3399_CLKGATE_CON(10), 8, GFLAGS), 113711551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, 113811551005SXing Zheng RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, 113911551005SXing Zheng RK3399_CLKGATE_CON(10), 9, GFLAGS), 114011551005SXing Zheng 114111551005SXing Zheng GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLK_IGNORE_UNUSED, 114211551005SXing Zheng RK3399_CLKGATE_CON(28), 3, GFLAGS), 114311551005SXing Zheng GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, 114411551005SXing Zheng RK3399_CLKGATE_CON(28), 1, GFLAGS), 114511551005SXing Zheng 114611551005SXing Zheng GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLK_IGNORE_UNUSED, 114711551005SXing Zheng RK3399_CLKGATE_CON(28), 2, GFLAGS), 114811551005SXing Zheng GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, 114911551005SXing Zheng RK3399_CLKGATE_CON(28), 0, GFLAGS), 115011551005SXing Zheng 115111551005SXing Zheng COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED, 115211551005SXing Zheng RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, 115311551005SXing Zheng RK3399_CLKGATE_CON(10), 12, GFLAGS), 115411551005SXing Zheng 115511551005SXing Zheng COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT, 115611551005SXing Zheng RK3399_CLKSEL_CON(106), 0, 115711551005SXing Zheng &rk3399_dclk_vop0_fracmux), 115811551005SXing Zheng 115911551005SXing Zheng COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, 116011551005SXing Zheng RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, 116111551005SXing Zheng RK3399_CLKGATE_CON(10), 14, GFLAGS), 116211551005SXing Zheng 116311551005SXing Zheng /* vop1 */ 116411551005SXing Zheng COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 116511551005SXing Zheng RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 116611551005SXing Zheng RK3399_CLKGATE_CON(10), 10, GFLAGS), 116711551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, 116811551005SXing Zheng RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, 116911551005SXing Zheng RK3399_CLKGATE_CON(10), 11, GFLAGS), 117011551005SXing Zheng 117111551005SXing Zheng GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLK_IGNORE_UNUSED, 117211551005SXing Zheng RK3399_CLKGATE_CON(28), 7, GFLAGS), 117311551005SXing Zheng GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, 117411551005SXing Zheng RK3399_CLKGATE_CON(28), 5, GFLAGS), 117511551005SXing Zheng 117611551005SXing Zheng GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLK_IGNORE_UNUSED, 117711551005SXing Zheng RK3399_CLKGATE_CON(28), 6, GFLAGS), 117811551005SXing Zheng GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, 117911551005SXing Zheng RK3399_CLKGATE_CON(28), 4, GFLAGS), 118011551005SXing Zheng 118111551005SXing Zheng COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED, 118211551005SXing Zheng RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, 118311551005SXing Zheng RK3399_CLKGATE_CON(10), 13, GFLAGS), 118411551005SXing Zheng 118511551005SXing Zheng COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT, 118611551005SXing Zheng RK3399_CLKSEL_CON(107), 0, 118711551005SXing Zheng &rk3399_dclk_vop1_fracmux), 118811551005SXing Zheng 118911551005SXing Zheng COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, 119011551005SXing Zheng RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, 119111551005SXing Zheng RK3399_CLKGATE_CON(10), 15, GFLAGS), 119211551005SXing Zheng 119311551005SXing Zheng /* isp */ 1194*3f92a054SXing Zheng COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 119511551005SXing Zheng RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, 119611551005SXing Zheng RK3399_CLKGATE_CON(12), 8, GFLAGS), 1197*3f92a054SXing Zheng COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, 119811551005SXing Zheng RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, 119911551005SXing Zheng RK3399_CLKGATE_CON(12), 9, GFLAGS), 120011551005SXing Zheng 120111551005SXing Zheng GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, 120211551005SXing Zheng RK3399_CLKGATE_CON(27), 1, GFLAGS), 120311551005SXing Zheng GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED, 120411551005SXing Zheng RK3399_CLKGATE_CON(27), 5, GFLAGS), 120511551005SXing Zheng GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED, 120611551005SXing Zheng RK3399_CLKGATE_CON(27), 7, GFLAGS), 120711551005SXing Zheng 120811551005SXing Zheng GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, 120911551005SXing Zheng RK3399_CLKGATE_CON(27), 0, GFLAGS), 121011551005SXing Zheng GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", CLK_IGNORE_UNUSED, 121111551005SXing Zheng RK3399_CLKGATE_CON(27), 4, GFLAGS), 121211551005SXing Zheng 121311551005SXing Zheng COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 121411551005SXing Zheng RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, 121511551005SXing Zheng RK3399_CLKGATE_CON(11), 4, GFLAGS), 121611551005SXing Zheng 121711551005SXing Zheng COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 121811551005SXing Zheng RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, 121911551005SXing Zheng RK3399_CLKGATE_CON(12), 10, GFLAGS), 1220*3f92a054SXing Zheng COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, 122111551005SXing Zheng RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, 122211551005SXing Zheng RK3399_CLKGATE_CON(12), 11, GFLAGS), 122311551005SXing Zheng 122411551005SXing Zheng GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, 122511551005SXing Zheng RK3399_CLKGATE_CON(27), 3, GFLAGS), 122611551005SXing Zheng 122711551005SXing Zheng GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, 122811551005SXing Zheng RK3399_CLKGATE_CON(27), 2, GFLAGS), 122911551005SXing Zheng GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", CLK_IGNORE_UNUSED, 123011551005SXing Zheng RK3399_CLKGATE_CON(27), 8, GFLAGS), 123111551005SXing Zheng 123211551005SXing Zheng COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 123311551005SXing Zheng RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, 123411551005SXing Zheng RK3399_CLKGATE_CON(11), 5, GFLAGS), 123511551005SXing Zheng 123611551005SXing Zheng /* 123711551005SXing Zheng * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, 123811551005SXing Zheng * so we ignore the mux and make clocks nodes as following, 123911551005SXing Zheng * 124011551005SXing Zheng * pclkin_cifinv --|-------\ 124111551005SXing Zheng * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper 124211551005SXing Zheng * pclkin_cif --|-------/ 124311551005SXing Zheng */ 124411551005SXing Zheng GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", CLK_IGNORE_UNUSED, 124511551005SXing Zheng RK3399_CLKGATE_CON(27), 6, GFLAGS), 124611551005SXing Zheng 124711551005SXing Zheng /* cif */ 124811551005SXing Zheng COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 124911551005SXing Zheng RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS, 125011551005SXing Zheng RK3399_CLKGATE_CON(10), 7, GFLAGS), 125111551005SXing Zheng MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT, 125211551005SXing Zheng RK3399_CLKSEL_CON(56), 5, 1, MFLAGS), 125311551005SXing Zheng 125411551005SXing Zheng /* gic */ 125511551005SXing Zheng COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 125611551005SXing Zheng RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, 125711551005SXing Zheng RK3399_CLKGATE_CON(12), 12, GFLAGS), 125811551005SXing Zheng 125911551005SXing Zheng GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), 126011551005SXing Zheng GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), 126111551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), 126211551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), 126311551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), 126411551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), 126511551005SXing Zheng 126611551005SXing Zheng /* alive */ 126711551005SXing Zheng /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ 126811551005SXing Zheng DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, 126911551005SXing Zheng RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), 127011551005SXing Zheng 127111551005SXing Zheng GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), 127211551005SXing Zheng GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), 127311551005SXing Zheng GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), 127411551005SXing Zheng GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), 127511551005SXing Zheng GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), 127611551005SXing Zheng 127711551005SXing Zheng GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), 127811551005SXing Zheng GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), 127911551005SXing Zheng GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 3, GFLAGS), 128011551005SXing Zheng GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 4, GFLAGS), 128111551005SXing Zheng GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 5, GFLAGS), 128211551005SXing Zheng GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 6, GFLAGS), 128311551005SXing Zheng GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 7, GFLAGS), 128411551005SXing Zheng GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), 128511551005SXing Zheng GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), 128611551005SXing Zheng 128711551005SXing Zheng GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 14, GFLAGS), 128811551005SXing Zheng GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), 128911551005SXing Zheng 129011551005SXing Zheng GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 15, GFLAGS), 129111551005SXing Zheng GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), 129211551005SXing Zheng GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), 129311551005SXing Zheng GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), 129411551005SXing Zheng 129511551005SXing Zheng /* testout */ 129611551005SXing Zheng MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, 129711551005SXing Zheng RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), 129811551005SXing Zheng COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT, 129911551005SXing Zheng RK3399_CLKSEL_CON(105), 0, 130011551005SXing Zheng RK3399_CLKGATE_CON(13), 9, GFLAGS), 130111551005SXing Zheng 130211551005SXing Zheng DIV(0, "clk_test_24m", "xin24m", 0, 130311551005SXing Zheng RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), 130411551005SXing Zheng 130511551005SXing Zheng /* spi */ 130611551005SXing Zheng COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, 130711551005SXing Zheng RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, 130811551005SXing Zheng RK3399_CLKGATE_CON(9), 12, GFLAGS), 130911551005SXing Zheng 131011551005SXing Zheng COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, 131111551005SXing Zheng RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, 131211551005SXing Zheng RK3399_CLKGATE_CON(9), 13, GFLAGS), 131311551005SXing Zheng 131411551005SXing Zheng COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, 131511551005SXing Zheng RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, 131611551005SXing Zheng RK3399_CLKGATE_CON(9), 14, GFLAGS), 131711551005SXing Zheng 131811551005SXing Zheng COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, 131911551005SXing Zheng RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, 132011551005SXing Zheng RK3399_CLKGATE_CON(9), 15, GFLAGS), 132111551005SXing Zheng 132211551005SXing Zheng COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, 132311551005SXing Zheng RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, 132411551005SXing Zheng RK3399_CLKGATE_CON(13), 13, GFLAGS), 132511551005SXing Zheng 132611551005SXing Zheng /* i2c */ 132711551005SXing Zheng COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, 132811551005SXing Zheng RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, 132911551005SXing Zheng RK3399_CLKGATE_CON(10), 0, GFLAGS), 133011551005SXing Zheng 133111551005SXing Zheng COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, 133211551005SXing Zheng RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, 133311551005SXing Zheng RK3399_CLKGATE_CON(10), 2, GFLAGS), 133411551005SXing Zheng 133511551005SXing Zheng COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, 133611551005SXing Zheng RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, 133711551005SXing Zheng RK3399_CLKGATE_CON(10), 4, GFLAGS), 133811551005SXing Zheng 133911551005SXing Zheng COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, 134011551005SXing Zheng RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, 134111551005SXing Zheng RK3399_CLKGATE_CON(10), 1, GFLAGS), 134211551005SXing Zheng 134311551005SXing Zheng COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, 134411551005SXing Zheng RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, 134511551005SXing Zheng RK3399_CLKGATE_CON(10), 3, GFLAGS), 134611551005SXing Zheng 134711551005SXing Zheng COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, 134811551005SXing Zheng RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, 134911551005SXing Zheng RK3399_CLKGATE_CON(10), 5, GFLAGS), 135011551005SXing Zheng 135111551005SXing Zheng /* timer */ 135211551005SXing Zheng GATE(SCLK_TIMER00, "clk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 0, GFLAGS), 135311551005SXing Zheng GATE(SCLK_TIMER01, "clk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 1, GFLAGS), 135411551005SXing Zheng GATE(SCLK_TIMER02, "clk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 2, GFLAGS), 135511551005SXing Zheng GATE(SCLK_TIMER03, "clk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 3, GFLAGS), 135611551005SXing Zheng GATE(SCLK_TIMER04, "clk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 4, GFLAGS), 135711551005SXing Zheng GATE(SCLK_TIMER05, "clk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 5, GFLAGS), 135811551005SXing Zheng GATE(SCLK_TIMER06, "clk_timer06", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 6, GFLAGS), 135911551005SXing Zheng GATE(SCLK_TIMER07, "clk_timer07", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 7, GFLAGS), 136011551005SXing Zheng GATE(SCLK_TIMER08, "clk_timer08", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 8, GFLAGS), 136111551005SXing Zheng GATE(SCLK_TIMER09, "clk_timer09", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 9, GFLAGS), 136211551005SXing Zheng GATE(SCLK_TIMER10, "clk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 10, GFLAGS), 136311551005SXing Zheng GATE(SCLK_TIMER11, "clk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 11, GFLAGS), 136411551005SXing Zheng 136511551005SXing Zheng /* clk_test */ 136611551005SXing Zheng /* clk_test_pre is controlled by CRU_MISC_CON[3] */ 136711551005SXing Zheng COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, 136811551005SXing Zheng RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, 136911551005SXing Zheng RK3368_CLKGATE_CON(13), 11, GFLAGS), 137011551005SXing Zheng }; 137111551005SXing Zheng 137211551005SXing Zheng static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { 137311551005SXing Zheng /* 137411551005SXing Zheng * PMU CRU Clock-Architecture 137511551005SXing Zheng */ 137611551005SXing Zheng 137711551005SXing Zheng GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED, 137811551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), 137911551005SXing Zheng 138011551005SXing Zheng COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED, 138111551005SXing Zheng RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), 138211551005SXing Zheng 138311551005SXing Zheng COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED, 138411551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, 138511551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), 138611551005SXing Zheng 138711551005SXing Zheng COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, 138811551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, 138911551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), 139011551005SXing Zheng 139111551005SXing Zheng COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT, 139211551005SXing Zheng RK3399_PMU_CLKSEL_CON(7), 0, 139311551005SXing Zheng &rk3399_pmuclk_wifi_fracmux), 139411551005SXing Zheng 139511551005SXing Zheng MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, 139611551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), 139711551005SXing Zheng 139811551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, 139911551005SXing Zheng RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, 140011551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), 140111551005SXing Zheng 140211551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, 140311551005SXing Zheng RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1404f3d40914SXing Zheng RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), 140511551005SXing Zheng 140611551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, 140711551005SXing Zheng RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, 1408f3d40914SXing Zheng RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), 140911551005SXing Zheng 141011551005SXing Zheng DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, 141111551005SXing Zheng RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), 141211551005SXing Zheng MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, 141311551005SXing Zheng RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), 141411551005SXing Zheng 141511551005SXing Zheng COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, CLK_IGNORE_UNUSED, 141611551005SXing Zheng RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, 141711551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), 141811551005SXing Zheng 141911551005SXing Zheng COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT, 142011551005SXing Zheng RK3399_PMU_CLKSEL_CON(6), 0, 142111551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, 142211551005SXing Zheng &rk3399_uart4_pmu_fracmux), 142311551005SXing Zheng 142411551005SXing Zheng DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, 142511551005SXing Zheng RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), 142611551005SXing Zheng 142711551005SXing Zheng /* pmu clock gates */ 142811551005SXing Zheng GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), 142911551005SXing Zheng GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), 143011551005SXing Zheng 143111551005SXing Zheng GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), 143211551005SXing Zheng 143311551005SXing Zheng GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), 143411551005SXing Zheng GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), 143511551005SXing Zheng GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), 143611551005SXing Zheng GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), 143711551005SXing Zheng GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), 143811551005SXing Zheng GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), 143911551005SXing Zheng GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), 144011551005SXing Zheng GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), 144111551005SXing Zheng GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), 144211551005SXing Zheng GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), 144311551005SXing Zheng GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), 144411551005SXing Zheng GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), 144511551005SXing Zheng GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), 144611551005SXing Zheng GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), 144711551005SXing Zheng GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 144811551005SXing Zheng GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 144911551005SXing Zheng 145011551005SXing Zheng GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 145111551005SXing Zheng GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 145211551005SXing Zheng GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 145311551005SXing Zheng GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 145411551005SXing Zheng GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 145511551005SXing Zheng }; 145611551005SXing Zheng 145711551005SXing Zheng static const char *const rk3399_cru_critical_clocks[] __initconst = { 145811551005SXing Zheng "aclk_cci_pre", 145911551005SXing Zheng "pclk_perilp0", 146011551005SXing Zheng "pclk_perilp0", 146111551005SXing Zheng "hclk_perilp0", 146211551005SXing Zheng "hclk_perilp0_noc", 146311551005SXing Zheng "pclk_perilp1", 146411551005SXing Zheng "pclk_perilp1_noc", 146511551005SXing Zheng "pclk_perihp", 146611551005SXing Zheng "pclk_perihp_noc", 146711551005SXing Zheng "hclk_perihp", 146811551005SXing Zheng "aclk_perihp", 146911551005SXing Zheng "aclk_perihp_noc", 147011551005SXing Zheng "aclk_perilp0", 147111551005SXing Zheng "aclk_perilp0_noc", 147211551005SXing Zheng "hclk_perilp1", 147311551005SXing Zheng "hclk_perilp1_noc", 147411551005SXing Zheng "aclk_dmac0_perilp", 147511551005SXing Zheng "gpll_hclk_perilp1_src", 147611551005SXing Zheng "gpll_aclk_perilp0_src", 147711551005SXing Zheng "gpll_aclk_perihp_src", 147811551005SXing Zheng }; 147911551005SXing Zheng 148011551005SXing Zheng static const char *const rk3399_pmucru_critical_clocks[] __initconst = { 148111551005SXing Zheng "ppll", 148211551005SXing Zheng "pclk_pmu_src", 148311551005SXing Zheng "fclk_cm0s_src_pmu", 148411551005SXing Zheng "clk_timer_src_pmu", 148511551005SXing Zheng }; 148611551005SXing Zheng 148711551005SXing Zheng static void __init rk3399_clk_init(struct device_node *np) 148811551005SXing Zheng { 148911551005SXing Zheng struct rockchip_clk_provider *ctx; 149011551005SXing Zheng void __iomem *reg_base; 149111551005SXing Zheng 149211551005SXing Zheng reg_base = of_iomap(np, 0); 149311551005SXing Zheng if (!reg_base) { 149411551005SXing Zheng pr_err("%s: could not map cru region\n", __func__); 149511551005SXing Zheng return; 149611551005SXing Zheng } 149711551005SXing Zheng 149811551005SXing Zheng ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 149911551005SXing Zheng if (IS_ERR(ctx)) { 150011551005SXing Zheng pr_err("%s: rockchip clk init failed\n", __func__); 150111551005SXing Zheng return; 150211551005SXing Zheng } 150311551005SXing Zheng 150411551005SXing Zheng rockchip_clk_register_plls(ctx, rk3399_pll_clks, 150511551005SXing Zheng ARRAY_SIZE(rk3399_pll_clks), -1); 150611551005SXing Zheng 150711551005SXing Zheng rockchip_clk_register_branches(ctx, rk3399_clk_branches, 150811551005SXing Zheng ARRAY_SIZE(rk3399_clk_branches)); 150911551005SXing Zheng 151011551005SXing Zheng rockchip_clk_protect_critical(rk3399_cru_critical_clocks, 151111551005SXing Zheng ARRAY_SIZE(rk3399_cru_critical_clocks)); 151211551005SXing Zheng 151311551005SXing Zheng rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 151411551005SXing Zheng mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 151511551005SXing Zheng &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, 151611551005SXing Zheng ARRAY_SIZE(rk3399_cpuclkl_rates)); 151711551005SXing Zheng 151811551005SXing Zheng rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 151911551005SXing Zheng mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), 152011551005SXing Zheng &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, 152111551005SXing Zheng ARRAY_SIZE(rk3399_cpuclkb_rates)); 152211551005SXing Zheng 152311551005SXing Zheng rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), 152411551005SXing Zheng ROCKCHIP_SOFTRST_HIWORD_MASK); 152511551005SXing Zheng 152611551005SXing Zheng rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); 152711551005SXing Zheng 152811551005SXing Zheng rockchip_clk_of_add_provider(np, ctx); 152911551005SXing Zheng } 153011551005SXing Zheng CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init); 153111551005SXing Zheng 153211551005SXing Zheng static void __init rk3399_pmu_clk_init(struct device_node *np) 153311551005SXing Zheng { 153411551005SXing Zheng struct rockchip_clk_provider *ctx; 153511551005SXing Zheng void __iomem *reg_base; 153611551005SXing Zheng 153711551005SXing Zheng reg_base = of_iomap(np, 0); 153811551005SXing Zheng if (!reg_base) { 153911551005SXing Zheng pr_err("%s: could not map cru pmu region\n", __func__); 154011551005SXing Zheng return; 154111551005SXing Zheng } 154211551005SXing Zheng 154311551005SXing Zheng ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 154411551005SXing Zheng if (IS_ERR(ctx)) { 154511551005SXing Zheng pr_err("%s: rockchip pmu clk init failed\n", __func__); 154611551005SXing Zheng return; 154711551005SXing Zheng } 154811551005SXing Zheng 154911551005SXing Zheng rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, 155011551005SXing Zheng ARRAY_SIZE(rk3399_pmu_pll_clks), -1); 155111551005SXing Zheng 155211551005SXing Zheng rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, 155311551005SXing Zheng ARRAY_SIZE(rk3399_clk_pmu_branches)); 155411551005SXing Zheng 155511551005SXing Zheng rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, 155611551005SXing Zheng ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 155711551005SXing Zheng 155811551005SXing Zheng rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), 155911551005SXing Zheng ROCKCHIP_SOFTRST_HIWORD_MASK); 156011551005SXing Zheng 156111551005SXing Zheng rockchip_clk_of_add_provider(np, ctx); 156211551005SXing Zheng } 156311551005SXing Zheng CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); 1564