1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <dt-bindings/clock/rk3188-cru-common.h> 20 #include "clk.h" 21 22 #define RK3188_GRF_SOC_STATUS 0xac 23 24 enum rk3188_plls { 25 apll, cpll, dpll, gpll, 26 }; 27 28 struct rockchip_pll_rate_table rk3188_pll_rates[] = { 29 RK3066_PLL_RATE(2208000000, 1, 92, 1), 30 RK3066_PLL_RATE(2184000000, 1, 91, 1), 31 RK3066_PLL_RATE(2160000000, 1, 90, 1), 32 RK3066_PLL_RATE(2136000000, 1, 89, 1), 33 RK3066_PLL_RATE(2112000000, 1, 88, 1), 34 RK3066_PLL_RATE(2088000000, 1, 87, 1), 35 RK3066_PLL_RATE(2064000000, 1, 86, 1), 36 RK3066_PLL_RATE(2040000000, 1, 85, 1), 37 RK3066_PLL_RATE(2016000000, 1, 84, 1), 38 RK3066_PLL_RATE(1992000000, 1, 83, 1), 39 RK3066_PLL_RATE(1968000000, 1, 82, 1), 40 RK3066_PLL_RATE(1944000000, 1, 81, 1), 41 RK3066_PLL_RATE(1920000000, 1, 80, 1), 42 RK3066_PLL_RATE(1896000000, 1, 79, 1), 43 RK3066_PLL_RATE(1872000000, 1, 78, 1), 44 RK3066_PLL_RATE(1848000000, 1, 77, 1), 45 RK3066_PLL_RATE(1824000000, 1, 76, 1), 46 RK3066_PLL_RATE(1800000000, 1, 75, 1), 47 RK3066_PLL_RATE(1776000000, 1, 74, 1), 48 RK3066_PLL_RATE(1752000000, 1, 73, 1), 49 RK3066_PLL_RATE(1728000000, 1, 72, 1), 50 RK3066_PLL_RATE(1704000000, 1, 71, 1), 51 RK3066_PLL_RATE(1680000000, 1, 70, 1), 52 RK3066_PLL_RATE(1656000000, 1, 69, 1), 53 RK3066_PLL_RATE(1632000000, 1, 68, 1), 54 RK3066_PLL_RATE(1608000000, 1, 67, 1), 55 RK3066_PLL_RATE(1560000000, 1, 65, 1), 56 RK3066_PLL_RATE(1512000000, 1, 63, 1), 57 RK3066_PLL_RATE(1488000000, 1, 62, 1), 58 RK3066_PLL_RATE(1464000000, 1, 61, 1), 59 RK3066_PLL_RATE(1440000000, 1, 60, 1), 60 RK3066_PLL_RATE(1416000000, 1, 59, 1), 61 RK3066_PLL_RATE(1392000000, 1, 58, 1), 62 RK3066_PLL_RATE(1368000000, 1, 57, 1), 63 RK3066_PLL_RATE(1344000000, 1, 56, 1), 64 RK3066_PLL_RATE(1320000000, 1, 55, 1), 65 RK3066_PLL_RATE(1296000000, 1, 54, 1), 66 RK3066_PLL_RATE(1272000000, 1, 53, 1), 67 RK3066_PLL_RATE(1248000000, 1, 52, 1), 68 RK3066_PLL_RATE(1224000000, 1, 51, 1), 69 RK3066_PLL_RATE(1200000000, 1, 50, 1), 70 RK3066_PLL_RATE(1188000000, 2, 99, 1), 71 RK3066_PLL_RATE(1176000000, 1, 49, 1), 72 RK3066_PLL_RATE(1128000000, 1, 47, 1), 73 RK3066_PLL_RATE(1104000000, 1, 46, 1), 74 RK3066_PLL_RATE(1008000000, 1, 84, 2), 75 RK3066_PLL_RATE( 912000000, 1, 76, 2), 76 RK3066_PLL_RATE( 891000000, 8, 594, 2), 77 RK3066_PLL_RATE( 888000000, 1, 74, 2), 78 RK3066_PLL_RATE( 816000000, 1, 68, 2), 79 RK3066_PLL_RATE( 798000000, 2, 133, 2), 80 RK3066_PLL_RATE( 792000000, 1, 66, 2), 81 RK3066_PLL_RATE( 768000000, 1, 64, 2), 82 RK3066_PLL_RATE( 742500000, 8, 495, 2), 83 RK3066_PLL_RATE( 696000000, 1, 58, 2), 84 RK3066_PLL_RATE( 600000000, 1, 50, 2), 85 RK3066_PLL_RATE( 594000000, 2, 198, 4), 86 RK3066_PLL_RATE( 552000000, 1, 46, 2), 87 RK3066_PLL_RATE( 504000000, 1, 84, 4), 88 RK3066_PLL_RATE( 456000000, 1, 76, 4), 89 RK3066_PLL_RATE( 408000000, 1, 68, 4), 90 RK3066_PLL_RATE( 384000000, 2, 128, 4), 91 RK3066_PLL_RATE( 360000000, 1, 60, 4), 92 RK3066_PLL_RATE( 312000000, 1, 52, 4), 93 RK3066_PLL_RATE( 300000000, 1, 50, 4), 94 RK3066_PLL_RATE( 297000000, 2, 198, 8), 95 RK3066_PLL_RATE( 252000000, 1, 84, 8), 96 RK3066_PLL_RATE( 216000000, 1, 72, 8), 97 RK3066_PLL_RATE( 148500000, 2, 99, 8), 98 RK3066_PLL_RATE( 126000000, 1, 84, 16), 99 RK3066_PLL_RATE( 48000000, 1, 64, 32), 100 { /* sentinel */ }, 101 }; 102 103 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 104 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; 105 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; 106 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" }; 107 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 108 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; 109 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; 110 PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; 111 PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; 112 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; 113 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; 114 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; 115 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" }; 116 PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" }; 117 PNAME(mux_mac_p) = { "gpll", "dpll" }; 118 PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" }; 119 120 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { 121 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 122 RK2928_MODE_CON, 0, 6, rk3188_pll_rates), 123 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 124 RK2928_MODE_CON, 4, 5, NULL), 125 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 126 RK2928_MODE_CON, 8, 7, rk3188_pll_rates), 127 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 128 RK2928_MODE_CON, 12, 8, rk3188_pll_rates), 129 }; 130 131 #define MFLAGS CLK_MUX_HIWORD_MASK 132 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 133 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 134 135 /* 2 ^ (val + 1) */ 136 static struct clk_div_table div_core_peri_t[] = { 137 { .val = 0, .div = 2 }, 138 { .val = 1, .div = 4 }, 139 { .val = 2, .div = 8 }, 140 { .val = 3, .div = 16 }, 141 { /* sentinel */ }, 142 }; 143 144 static struct rockchip_clk_branch common_clk_branches[] __initdata = { 145 /* 146 * Clock-Architecture Diagram 2 147 */ 148 149 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), 150 151 /* these two are set by the cpuclk and should not be changed */ 152 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0, 153 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, 154 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), 155 156 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, 157 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, 158 RK2928_CLKGATE_CON(3), 9, GFLAGS), 159 GATE(0, "hclk_vepu", "aclk_vepu", 0, 160 RK2928_CLKGATE_CON(3), 10, GFLAGS), 161 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, 162 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 163 RK2928_CLKGATE_CON(3), 11, GFLAGS), 164 GATE(0, "hclk_vdpu", "aclk_vdpu", 0, 165 RK2928_CLKGATE_CON(3), 12, GFLAGS), 166 167 GATE(0, "gpll_ddr", "gpll", 0, 168 RK2928_CLKGATE_CON(1), 7, GFLAGS), 169 COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0, 170 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 171 RK2928_CLKGATE_CON(0), 2, GFLAGS), 172 173 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, 174 RK2928_CLKGATE_CON(0), 3, GFLAGS), 175 176 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 177 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 178 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, 179 RK2928_CLKGATE_CON(0), 6, GFLAGS), 180 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, 181 RK2928_CLKGATE_CON(0), 5, GFLAGS), 182 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 183 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 184 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 185 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 186 RK2928_CLKGATE_CON(4), 9, GFLAGS), 187 GATE(0, "hclk_cpu", "hclk_cpu_pre", 0, 188 RK2928_CLKGATE_CON(0), 4, GFLAGS), 189 190 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0, 191 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, 192 RK2928_CLKGATE_CON(3), 0, GFLAGS), 193 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, 194 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, 195 RK2928_CLKGATE_CON(1), 4, GFLAGS), 196 197 GATE(0, "aclk_peri", "aclk_peri_pre", 0, 198 RK2928_CLKGATE_CON(2), 1, GFLAGS), 199 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, 200 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 201 RK2928_CLKGATE_CON(2), 2, GFLAGS), 202 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, 203 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 204 RK2928_CLKGATE_CON(2), 3, GFLAGS), 205 206 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, 207 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), 208 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, 209 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, 210 RK2928_CLKGATE_CON(3), 7, GFLAGS), 211 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, 212 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), 213 214 GATE(0, "pclkin_cif0", "ext_cif0", 0, 215 RK2928_CLKGATE_CON(3), 3, GFLAGS), 216 217 /* 218 * the 480m are generated inside the usb block from these clocks, 219 * but they are also a source for the hsicphy clock. 220 */ 221 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0, 222 RK2928_CLKGATE_CON(1), 5, GFLAGS), 223 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0, 224 RK2928_CLKGATE_CON(1), 6, GFLAGS), 225 226 COMPOSITE(0, "mac_src", mux_mac_p, 0, 227 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, 228 RK2928_CLKGATE_CON(2), 5, GFLAGS), 229 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, 230 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), 231 GATE(0, "sclk_mac_lbtest", "sclk_macref", 232 RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), 233 234 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, 235 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, 236 RK2928_CLKGATE_CON(2), 6, GFLAGS), 237 COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 238 RK2928_CLKSEL_CON(23), 0, 239 RK2928_CLKGATE_CON(2), 7, 0, GFLAGS), 240 MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0, 241 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), 242 243 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 244 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, 245 RK2928_CLKGATE_CON(2), 8, GFLAGS), 246 247 /* 248 * Clock-Architecture Diagram 4 249 */ 250 251 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 252 RK2928_CLKGATE_CON(2), 4, 0, GFLAGS), 253 254 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, 255 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, 256 RK2928_CLKGATE_CON(2), 9, GFLAGS), 257 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0, 258 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS, 259 RK2928_CLKGATE_CON(2), 10, GFLAGS), 260 261 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0, 262 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS, 263 RK2928_CLKGATE_CON(2), 11, GFLAGS), 264 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0, 265 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS, 266 RK2928_CLKGATE_CON(2), 13, GFLAGS), 267 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0, 268 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, 269 RK2928_CLKGATE_CON(2), 14, GFLAGS), 270 271 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0, 272 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS), 273 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, 274 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 275 RK2928_CLKGATE_CON(1), 8, GFLAGS), 276 COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0, 277 RK2928_CLKSEL_CON(17), 0, 278 RK2928_CLKGATE_CON(1), 9, GFLAGS), 279 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, 280 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), 281 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, 282 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 283 RK2928_CLKGATE_CON(1), 10, GFLAGS), 284 COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0, 285 RK2928_CLKSEL_CON(18), 0, 286 RK2928_CLKGATE_CON(1), 11, GFLAGS), 287 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, 288 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), 289 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, 290 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 291 RK2928_CLKGATE_CON(1), 12, GFLAGS), 292 COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0, 293 RK2928_CLKSEL_CON(19), 0, 294 RK2928_CLKGATE_CON(1), 13, GFLAGS), 295 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, 296 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), 297 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, 298 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, 299 RK2928_CLKGATE_CON(1), 14, GFLAGS), 300 COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0, 301 RK2928_CLKSEL_CON(20), 0, 302 RK2928_CLKGATE_CON(1), 15, GFLAGS), 303 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, 304 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS), 305 306 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), 307 308 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS), 309 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS), 310 311 /* clk_core_pre gates */ 312 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), 313 314 /* aclk_cpu gates */ 315 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), 316 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS), 317 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS), 318 319 /* hclk_cpu gates */ 320 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), 321 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), 322 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), 323 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), 324 /* hclk_ahb2apb is part of a clk branch */ 325 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), 326 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), 327 GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS), 328 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), 329 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS), 330 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), 331 332 /* hclk_peri gates */ 333 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS), 334 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS), 335 GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS), 336 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), 337 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), 338 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS), 339 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS), 340 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), 341 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), 342 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), 343 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), 344 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS), 345 346 /* aclk_lcdc0_pre gates */ 347 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS), 348 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), 349 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), 350 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS), 351 352 /* aclk_lcdc1_pre gates */ 353 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 354 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS), 355 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), 356 357 /* atclk_cpu gates */ 358 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS), 359 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), 360 361 /* pclk_cpu gates */ 362 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), 363 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), 364 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), 365 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), 366 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 367 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 368 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 369 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), 370 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), 371 GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), 372 GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 373 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), 374 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS), 375 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS), 376 377 /* aclk_peri */ 378 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 379 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS), 380 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS), 381 GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS), 382 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS), 383 384 /* pclk_peri gates */ 385 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS), 386 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS), 387 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), 388 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), 389 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS), 390 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), 391 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), 392 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), 393 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), 394 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), 395 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), 396 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), 397 }; 398 399 PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" }; 400 PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" }; 401 PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" }; 402 PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" }; 403 PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" }; 404 405 static struct clk_div_table div_aclk_cpu_t[] = { 406 { .val = 0, .div = 1 }, 407 { .val = 1, .div = 2 }, 408 { .val = 2, .div = 3 }, 409 { .val = 3, .div = 4 }, 410 { .val = 4, .div = 8 }, 411 { /* sentinel */ }, 412 }; 413 414 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 415 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0, 416 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 0, 5, DFLAGS), 417 DIVTBL(0, "aclk_cpu_pre", "armclk", 0, 418 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS, div_aclk_cpu_t), 419 420 GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0, 421 RK2928_CLKGATE_CON(9), 4, GFLAGS), 422 423 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0, 424 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 425 RK2928_CLKGATE_CON(2), 0, GFLAGS), 426 427 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, 428 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 429 RK2928_CLKGATE_CON(3), 1, GFLAGS), 430 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0, 431 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), 432 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, 433 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 434 RK2928_CLKGATE_CON(3), 2, GFLAGS), 435 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0, 436 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), 437 438 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, 439 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS, 440 RK2928_CLKGATE_CON(3), 8, GFLAGS), 441 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0, 442 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS), 443 444 GATE(0, "pclkin_cif1", "ext_cif1", 0, 445 RK2928_CLKGATE_CON(3), 4, GFLAGS), 446 447 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 448 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, 449 RK2928_CLKGATE_CON(3), 13, GFLAGS), 450 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 451 RK2928_CLKGATE_CON(5), 15, GFLAGS), 452 453 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, 454 RK2928_CLKGATE_CON(3), 2, GFLAGS), 455 456 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, 457 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, 458 RK2928_CLKGATE_CON(2), 15, GFLAGS), 459 460 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 461 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 462 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 463 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, 464 RK2928_CLKGATE_CON(0), 7, GFLAGS), 465 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, 466 RK2928_CLKSEL_CON(6), 0, 467 RK2928_CLKGATE_CON(0), 8, GFLAGS), 468 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, 469 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS), 470 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, 471 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 472 RK2928_CLKGATE_CON(0), 9, GFLAGS), 473 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0, 474 RK2928_CLKSEL_CON(7), 0, 475 RK2928_CLKGATE_CON(0), 10, GFLAGS), 476 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, 477 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), 478 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, 479 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, 480 RK2928_CLKGATE_CON(0), 11, GFLAGS), 481 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0, 482 RK2928_CLKSEL_CON(8), 0, 483 RK2928_CLKGATE_CON(0), 12, GFLAGS), 484 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, 485 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS), 486 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, 487 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, 488 RK2928_CLKGATE_CON(0), 13, GFLAGS), 489 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, 490 RK2928_CLKSEL_CON(9), 0, 491 RK2928_CLKGATE_CON(0), 14, GFLAGS), 492 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, 493 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), 494 495 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 496 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 497 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), 498 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 499 500 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), 501 502 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), 503 504 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), 505 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 506 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), 507 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 508 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 509 510 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 511 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), 512 }; 513 514 static struct clk_div_table div_rk3188_aclk_core_t[] = { 515 { .val = 0, .div = 1 }, 516 { .val = 1, .div = 2 }, 517 { .val = 2, .div = 3 }, 518 { .val = 3, .div = 4 }, 519 { .val = 4, .div = 8 }, 520 { /* sentinel */ }, 521 }; 522 523 PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", 524 "gpll", "cpll" }; 525 526 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 527 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0, 528 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 9, 5, DFLAGS), 529 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0, 530 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 531 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), 532 533 /* do not source aclk_cpu_pre from the apll, to keep complexity down */ 534 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, 535 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), 536 537 GATE(CORE_L2C, "core_l2c", "armclk", 0, 538 RK2928_CLKGATE_CON(9), 4, GFLAGS), 539 540 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0, 541 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 542 RK2928_CLKGATE_CON(2), 0, GFLAGS), 543 544 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0, 545 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 546 RK2928_CLKGATE_CON(3), 1, GFLAGS), 547 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0, 548 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 549 RK2928_CLKGATE_CON(3), 2, GFLAGS), 550 551 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 552 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, 553 RK2928_CLKGATE_CON(3), 15, GFLAGS), 554 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 555 RK2928_CLKGATE_CON(9), 7, GFLAGS), 556 557 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), 558 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), 559 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 560 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), 561 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), 562 563 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0, 564 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, 565 RK2928_CLKGATE_CON(3), 6, GFLAGS), 566 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, 567 RK2928_CLKGATE_CON(11), 8, 6, DFLAGS), 568 569 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 570 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 571 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 572 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 573 RK2928_CLKGATE_CON(0), 9, GFLAGS), 574 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, 575 RK2928_CLKSEL_CON(7), 0, 576 RK2928_CLKGATE_CON(0), 10, GFLAGS), 577 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, 578 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), 579 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, 580 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, 581 RK2928_CLKGATE_CON(13), 13, GFLAGS), 582 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0, 583 RK2928_CLKSEL_CON(9), 0, 584 RK2928_CLKGATE_CON(0), 14, GFLAGS), 585 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, 586 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), 587 588 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 589 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), 590 591 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 592 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 593 594 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 595 596 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 597 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 598 599 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 600 }; 601 602 static void __init rk3188_common_clk_init(struct device_node *np) 603 { 604 void __iomem *reg_base; 605 struct clk *clk; 606 607 reg_base = of_iomap(np, 0); 608 if (!reg_base) { 609 pr_err("%s: could not map cru region\n", __func__); 610 return; 611 } 612 613 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 614 615 /* xin12m is created by an cru-internal divider */ 616 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 617 if (IS_ERR(clk)) 618 pr_warn("%s: could not register clock xin12m: %ld\n", 619 __func__, PTR_ERR(clk)); 620 621 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); 622 if (IS_ERR(clk)) 623 pr_warn("%s: could not register clock usb480m: %ld\n", 624 __func__, PTR_ERR(clk)); 625 626 rockchip_clk_register_plls(rk3188_pll_clks, 627 ARRAY_SIZE(rk3188_pll_clks), 628 RK3188_GRF_SOC_STATUS); 629 rockchip_clk_register_branches(common_clk_branches, 630 ARRAY_SIZE(common_clk_branches)); 631 632 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 633 ROCKCHIP_SOFTRST_HIWORD_MASK); 634 } 635 636 static void __init rk3066a_clk_init(struct device_node *np) 637 { 638 rk3188_common_clk_init(np); 639 rockchip_clk_register_branches(rk3066a_clk_branches, 640 ARRAY_SIZE(rk3066a_clk_branches)); 641 } 642 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); 643 644 static void __init rk3188a_clk_init(struct device_node *np) 645 { 646 rk3188_common_clk_init(np); 647 rockchip_clk_register_branches(rk3188_clk_branches, 648 ARRAY_SIZE(rk3188_clk_branches)); 649 } 650 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); 651 652 static void __init rk3188_clk_init(struct device_node *np) 653 { 654 int i; 655 656 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) { 657 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; 658 struct rockchip_pll_rate_table *rate; 659 660 if (!pll->rate_table) 661 continue; 662 663 rate = pll->rate_table; 664 while (rate->rate > 0) { 665 rate->bwadj = 0; 666 rate++; 667 } 668 } 669 670 rk3188a_clk_init(np); 671 } 672 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init); 673