1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2014 Google, Inc 4 * Author: Alexandru M Stan <amstan@chromium.org> 5 */ 6 7 #include <linux/slab.h> 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/regmap.h> 13 #include "clk.h" 14 15 struct rockchip_mmc_clock { 16 struct clk_hw hw; 17 void __iomem *reg; 18 struct regmap *grf; 19 int grf_reg; 20 int shift; 21 int cached_phase; 22 struct notifier_block clk_rate_change_nb; 23 }; 24 25 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) 26 27 #define RK3288_MMC_CLKGEN_DIV 2 28 29 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, 30 unsigned long parent_rate) 31 { 32 return parent_rate / RK3288_MMC_CLKGEN_DIV; 33 } 34 35 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 36 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 37 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 38 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 39 40 #define PSECS_PER_SEC 1000000000000LL 41 42 /* 43 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 44 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 45 */ 46 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 47 48 static int rockchip_mmc_get_phase(struct clk_hw *hw) 49 { 50 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); 51 unsigned long rate = clk_hw_get_rate(hw); 52 u32 raw_value; 53 u16 degrees; 54 u32 delay_num = 0; 55 56 /* Constant signal, no measurable phase shift */ 57 if (!rate) 58 return 0; 59 60 if (mmc_clock->grf) 61 regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value); 62 else 63 raw_value = readl(mmc_clock->reg); 64 65 raw_value >>= mmc_clock->shift; 66 67 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 68 69 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 70 /* degrees/delaynum * 1000000 */ 71 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 72 36 * (rate / 10000); 73 74 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 75 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 76 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); 77 } 78 79 return degrees % 360; 80 } 81 82 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) 83 { 84 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); 85 unsigned long rate = clk_hw_get_rate(hw); 86 u8 nineties, remainder; 87 u8 delay_num; 88 u32 raw_value; 89 u32 delay; 90 91 /* 92 * The below calculation is based on the output clock from 93 * MMC host to the card, which expects the phase clock inherits 94 * the clock rate from its parent, namely the output clock 95 * provider of MMC host. However, things may go wrong if 96 * (1) It is orphan. 97 * (2) It is assigned to the wrong parent. 98 * 99 * This check help debug the case (1), which seems to be the 100 * most likely problem we often face and which makes it difficult 101 * for people to debug unstable mmc tuning results. 102 */ 103 if (!rate) { 104 pr_err("%s: invalid clk rate\n", __func__); 105 return -EINVAL; 106 } 107 108 nineties = degrees / 90; 109 remainder = (degrees % 90); 110 111 /* 112 * Due to the inexact nature of the "fine" delay, we might 113 * actually go non-monotonic. We don't go _too_ monotonic 114 * though, so we should be OK. Here are options of how we may 115 * work: 116 * 117 * Ideally we end up with: 118 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 119 * 120 * On one extreme (if delay is actually 44ps): 121 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 122 * The other (if delay is actually 77ps): 123 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 124 * 125 * It's possible we might make a delay that is up to 25 126 * degrees off from what we think we're making. That's OK 127 * though because we should be REALLY far from any bad range. 128 */ 129 130 /* 131 * Convert to delay; do a little extra work to make sure we 132 * don't overflow 32-bit / 64-bit numbers. 133 */ 134 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 135 delay *= remainder; 136 delay = DIV_ROUND_CLOSEST(delay, 137 (rate / 1000) * 36 * 138 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 139 140 delay_num = (u8) min_t(u32, delay, 255); 141 142 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 143 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 144 raw_value |= nineties; 145 raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift); 146 147 if (mmc_clock->grf) 148 regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value); 149 else 150 writel(raw_value, mmc_clock->reg); 151 152 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", 153 clk_hw_get_name(hw), degrees, delay_num, 154 mmc_clock->reg, raw_value>>(mmc_clock->shift), 155 rockchip_mmc_get_phase(hw) 156 ); 157 158 return 0; 159 } 160 161 static const struct clk_ops rockchip_mmc_clk_ops = { 162 .recalc_rate = rockchip_mmc_recalc, 163 .get_phase = rockchip_mmc_get_phase, 164 .set_phase = rockchip_mmc_set_phase, 165 }; 166 167 #define to_rockchip_mmc_clock(x) \ 168 container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb) 169 static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb, 170 unsigned long event, void *data) 171 { 172 struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb); 173 struct clk_notifier_data *ndata = data; 174 175 /* 176 * rockchip_mmc_clk is mostly used by mmc controllers to sample 177 * the intput data, which expects the fixed phase after the tuning 178 * process. However if the clock rate is changed, the phase is stale 179 * and may break the data sampling. So here we try to restore the phase 180 * for that case, except that 181 * (1) cached_phase is invaild since we inevitably cached it when the 182 * clock provider be reparented from orphan to its real parent in the 183 * first place. Otherwise we may mess up the initialization of MMC cards 184 * since we only set the default sample phase and drive phase later on. 185 * (2) the new coming rate is higher than the older one since mmc driver 186 * set the max-frequency to match the boards' ability but we can't go 187 * over the heads of that, otherwise the tests smoke out the issue. 188 */ 189 if (ndata->old_rate <= ndata->new_rate) 190 return NOTIFY_DONE; 191 192 if (event == PRE_RATE_CHANGE) 193 mmc_clock->cached_phase = 194 rockchip_mmc_get_phase(&mmc_clock->hw); 195 else if (mmc_clock->cached_phase != -EINVAL && 196 event == POST_RATE_CHANGE) 197 rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase); 198 199 return NOTIFY_DONE; 200 } 201 202 struct clk *rockchip_clk_register_mmc(const char *name, 203 const char *const *parent_names, u8 num_parents, 204 void __iomem *reg, 205 struct regmap *grf, int grf_reg, 206 int shift) 207 { 208 struct clk_init_data init; 209 struct rockchip_mmc_clock *mmc_clock; 210 struct clk *clk; 211 int ret; 212 213 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL); 214 if (!mmc_clock) 215 return ERR_PTR(-ENOMEM); 216 217 init.name = name; 218 init.flags = 0; 219 init.num_parents = num_parents; 220 init.parent_names = parent_names; 221 init.ops = &rockchip_mmc_clk_ops; 222 223 mmc_clock->hw.init = &init; 224 mmc_clock->reg = reg; 225 mmc_clock->grf = grf; 226 mmc_clock->grf_reg = grf_reg; 227 mmc_clock->shift = shift; 228 229 clk = clk_register(NULL, &mmc_clock->hw); 230 if (IS_ERR(clk)) { 231 ret = PTR_ERR(clk); 232 goto err_register; 233 } 234 235 mmc_clock->clk_rate_change_nb.notifier_call = 236 &rockchip_mmc_clk_rate_notify; 237 ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb); 238 if (ret) 239 goto err_notifier; 240 241 return clk; 242 err_notifier: 243 clk_unregister(clk); 244 err_register: 245 kfree(mmc_clock); 246 return ERR_PTR(ret); 247 } 248