xref: /linux/drivers/clk/rockchip/Makefile (revision 4d98ed1e126495016f2a3ef4db6379855c4aacf2) 
1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0
2646572c7SHeiko Stübner#
3646572c7SHeiko Stübner# Rockchip Clock specific Makefile
4646572c7SHeiko Stübner#
5646572c7SHeiko Stübner
6*4d98ed1eSElaine Zhangobj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
72c14736cSHeiko Stübner
8*4d98ed1eSElaine Zhangclk-rockchip-y += clk.o
9*4d98ed1eSElaine Zhangclk-rockchip-y += clk-pll.o
10*4d98ed1eSElaine Zhangclk-rockchip-y += clk-cpu.o
11*4d98ed1eSElaine Zhangclk-rockchip-y += clk-half-divider.o
12*4d98ed1eSElaine Zhangclk-rockchip-y += clk-inverter.o
13*4d98ed1eSElaine Zhangclk-rockchip-y += clk-mmc-phase.o
14*4d98ed1eSElaine Zhangclk-rockchip-y += clk-muxgrf.o
15*4d98ed1eSElaine Zhangclk-rockchip-y += clk-ddr.o
16*4d98ed1eSElaine Zhangclk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
17*4d98ed1eSElaine Zhang
18*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_PX30)          += clk-px30.o
19*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
20*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3036)        += clk-rk3036.o
21*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK312X)        += clk-rk3128.o
22*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3188)        += clk-rk3188.o
23*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK322X)        += clk-rk3228.o
24*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3288)        += clk-rk3288.o
25*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o
26*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o
27*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
28*4d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
29