1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 2646572c7SHeiko Stübner# 3646572c7SHeiko Stübner# Rockchip Clock specific Makefile 4646572c7SHeiko Stübner# 5646572c7SHeiko Stübner 64d98ed1eSElaine Zhangobj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o 72c14736cSHeiko Stübner 84d98ed1eSElaine Zhangclk-rockchip-y += clk.o 94d98ed1eSElaine Zhangclk-rockchip-y += clk-pll.o 104d98ed1eSElaine Zhangclk-rockchip-y += clk-cpu.o 114d98ed1eSElaine Zhangclk-rockchip-y += clk-half-divider.o 124d98ed1eSElaine Zhangclk-rockchip-y += clk-inverter.o 134d98ed1eSElaine Zhangclk-rockchip-y += clk-mmc-phase.o 144d98ed1eSElaine Zhangclk-rockchip-y += clk-muxgrf.o 154d98ed1eSElaine Zhangclk-rockchip-y += clk-ddr.o 164d98ed1eSElaine Zhangclk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o 174d98ed1eSElaine Zhang 184d98ed1eSElaine Zhangobj-$(CONFIG_CLK_PX30) += clk-px30.o 194d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RV110X) += clk-rv1108.o 20*2408ab5aSJagan Tekiobj-$(CONFIG_CLK_RV1126) += clk-rv1126.o 214d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3036) += clk-rk3036.o 224d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK312X) += clk-rk3128.o 234d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3188) += clk-rk3188.o 244d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK322X) += clk-rk3228.o 254d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3288) += clk-rk3288.o 264d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3308) += clk-rk3308.o 274d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3328) += clk-rk3328.o 284d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3368) += clk-rk3368.o 294d98ed1eSElaine Zhangobj-$(CONFIG_CLK_RK3399) += clk-rk3399.o 30cf911d89SElaine Zhangobj-$(CONFIG_CLK_RK3568) += clk-rk3568.o 31