1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/of_address.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_clock.h> 26 #include <linux/pm_domain.h> 27 #include <linux/psci.h> 28 #include <linux/reset-controller.h> 29 #include <linux/slab.h> 30 31 #include <dt-bindings/clock/renesas-cpg-mssr.h> 32 33 #include "renesas-cpg-mssr.h" 34 #include "clk-div6.h" 35 36 #ifdef DEBUG 37 #define WARN_DEBUG(x) WARN_ON(x) 38 #else 39 #define WARN_DEBUG(x) do { } while (0) 40 #endif 41 42 /* 43 * Module Standby and Software Reset register offets. 44 * 45 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 46 * R-Car Gen2, R-Car Gen3, and RZ/G1. 47 * These are NOT valid for R-Car Gen1 and RZ/A1! 48 */ 49 50 /* 51 * Module Stop Status Register offsets 52 */ 53 54 static const u16 mstpsr[] = { 55 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 56 0x9A0, 0x9A4, 0x9A8, 0x9AC, 57 }; 58 59 static const u16 mstpsr_for_gen4[] = { 60 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, 61 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, 62 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, 63 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74, 64 }; 65 66 /* 67 * System Module Stop Control Register offsets 68 */ 69 70 static const u16 smstpcr[] = { 71 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 72 0x990, 0x994, 0x998, 0x99C, 73 }; 74 75 static const u16 mstpcr_for_gen4[] = { 76 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, 77 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, 78 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, 79 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74, 80 }; 81 82 /* 83 * Standby Control Register offsets (RZ/A) 84 * Base address is FRQCR register 85 */ 86 87 static const u16 stbcr[] = { 88 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 89 0x424, 0x428, 0x42C, 90 }; 91 92 /* 93 * Software Reset Register offsets 94 */ 95 96 static const u16 srcr[] = { 97 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 98 0x920, 0x924, 0x928, 0x92C, 99 }; 100 101 static const u16 srcr_for_gen4[] = { 102 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, 103 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, 104 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, 105 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, 106 }; 107 108 /* 109 * Software Reset Clearing Register offsets 110 */ 111 112 static const u16 srstclr[] = { 113 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, 114 0x960, 0x964, 0x968, 0x96C, 115 }; 116 117 static const u16 srstclr_for_gen4[] = { 118 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, 119 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, 120 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, 121 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4, 122 }; 123 124 /** 125 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby 126 * and Software Reset Private Data 127 * 128 * @rcdev: Optional reset controller entity 129 * @dev: CPG/MSSR device 130 * @base: CPG/MSSR register block base address 131 * @reg_layout: CPG/MSSR register layout 132 * @rmw_lock: protects RMW register accesses 133 * @np: Device node in DT for this CPG/MSSR module 134 * @num_core_clks: Number of Core Clocks in clks[] 135 * @num_mod_clks: Number of Module Clocks in clks[] 136 * @last_dt_core_clk: ID of the last Core Clock exported to DT 137 * @notifiers: Notifier chain to save/restore clock state for system resume 138 * @status_regs: Pointer to status registers array 139 * @control_regs: Pointer to control registers array 140 * @reset_regs: Pointer to reset registers array 141 * @reset_clear_regs: Pointer to reset clearing registers array 142 * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control 143 * [].val: Saved values of SMSTPCR[] 144 * @reserved_ids: Temporary used, reserved id list 145 * @num_reserved_ids: Temporary used, number of reserved id list 146 * @clks: Array containing all Core and Module Clocks 147 */ 148 struct cpg_mssr_priv { 149 #ifdef CONFIG_RESET_CONTROLLER 150 struct reset_controller_dev rcdev; 151 #endif 152 struct device *dev; 153 void __iomem *base; 154 enum clk_reg_layout reg_layout; 155 spinlock_t rmw_lock; 156 struct device_node *np; 157 158 unsigned int num_core_clks; 159 unsigned int num_mod_clks; 160 unsigned int last_dt_core_clk; 161 162 struct raw_notifier_head notifiers; 163 const u16 *status_regs; 164 const u16 *control_regs; 165 const u16 *reset_regs; 166 const u16 *reset_clear_regs; 167 struct { 168 u32 mask; 169 u32 val; 170 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; 171 172 unsigned int *reserved_ids; 173 unsigned int num_reserved_ids; 174 175 struct clk *clks[]; 176 }; 177 178 static struct cpg_mssr_priv *cpg_mssr_priv; 179 180 /** 181 * struct mstp_clock - MSTP gating clock 182 * @hw: handle between common and hardware-specific interfaces 183 * @index: MSTP clock number 184 * @priv: CPG/MSSR private data 185 */ 186 struct mstp_clock { 187 struct clk_hw hw; 188 u32 index; 189 struct cpg_mssr_priv *priv; 190 }; 191 192 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 193 194 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 195 { 196 struct mstp_clock *clock = to_mstp_clock(hw); 197 struct cpg_mssr_priv *priv = clock->priv; 198 unsigned int reg = clock->index / 32; 199 unsigned int bit = clock->index % 32; 200 struct device *dev = priv->dev; 201 u32 bitmask = BIT(bit); 202 unsigned long flags; 203 u32 value; 204 int error; 205 206 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 207 enable ? "ON" : "OFF"); 208 spin_lock_irqsave(&priv->rmw_lock, flags); 209 210 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 211 value = readb(priv->base + priv->control_regs[reg]); 212 if (enable) 213 value &= ~bitmask; 214 else 215 value |= bitmask; 216 writeb(value, priv->base + priv->control_regs[reg]); 217 218 /* dummy read to ensure write has completed */ 219 readb(priv->base + priv->control_regs[reg]); 220 barrier_data(priv->base + priv->control_regs[reg]); 221 } else { 222 value = readl(priv->base + priv->control_regs[reg]); 223 if (enable) 224 value &= ~bitmask; 225 else 226 value |= bitmask; 227 writel(value, priv->base + priv->control_regs[reg]); 228 } 229 230 spin_unlock_irqrestore(&priv->rmw_lock, flags); 231 232 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 233 return 0; 234 235 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 236 value, !(value & bitmask), 0, 10); 237 if (error) 238 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 239 priv->base + priv->control_regs[reg], bit); 240 241 return error; 242 } 243 244 static int cpg_mstp_clock_enable(struct clk_hw *hw) 245 { 246 return cpg_mstp_clock_endisable(hw, true); 247 } 248 249 static void cpg_mstp_clock_disable(struct clk_hw *hw) 250 { 251 cpg_mstp_clock_endisable(hw, false); 252 } 253 254 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 255 { 256 struct mstp_clock *clock = to_mstp_clock(hw); 257 struct cpg_mssr_priv *priv = clock->priv; 258 u32 value; 259 260 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 261 value = readb(priv->base + priv->control_regs[clock->index / 32]); 262 else 263 value = readl(priv->base + priv->status_regs[clock->index / 32]); 264 265 return !(value & BIT(clock->index % 32)); 266 } 267 268 static const struct clk_ops cpg_mstp_clock_ops = { 269 .enable = cpg_mstp_clock_enable, 270 .disable = cpg_mstp_clock_disable, 271 .is_enabled = cpg_mstp_clock_is_enabled, 272 }; 273 274 static 275 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 276 void *data) 277 { 278 unsigned int clkidx = clkspec->args[1]; 279 struct cpg_mssr_priv *priv = data; 280 struct device *dev = priv->dev; 281 unsigned int idx; 282 const char *type; 283 struct clk *clk; 284 int range_check; 285 286 switch (clkspec->args[0]) { 287 case CPG_CORE: 288 type = "core"; 289 if (clkidx > priv->last_dt_core_clk) { 290 dev_err(dev, "Invalid %s clock index %u\n", type, 291 clkidx); 292 return ERR_PTR(-EINVAL); 293 } 294 clk = priv->clks[clkidx]; 295 break; 296 297 case CPG_MOD: 298 type = "module"; 299 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 300 idx = MOD_CLK_PACK_10(clkidx); 301 range_check = 7 - (clkidx % 10); 302 } else { 303 idx = MOD_CLK_PACK(clkidx); 304 range_check = 31 - (clkidx % 100); 305 } 306 if (range_check < 0 || idx >= priv->num_mod_clks) { 307 dev_err(dev, "Invalid %s clock index %u\n", type, 308 clkidx); 309 return ERR_PTR(-EINVAL); 310 } 311 clk = priv->clks[priv->num_core_clks + idx]; 312 break; 313 314 default: 315 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 316 return ERR_PTR(-EINVAL); 317 } 318 319 if (IS_ERR(clk)) 320 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 321 PTR_ERR(clk)); 322 else 323 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 324 clkspec->args[0], clkspec->args[1], clk, 325 clk_get_rate(clk)); 326 return clk; 327 } 328 329 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 330 const struct cpg_mssr_info *info, 331 struct cpg_mssr_priv *priv) 332 { 333 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 334 struct device *dev = priv->dev; 335 unsigned int id = core->id, div = core->div; 336 const char *parent_name; 337 338 WARN_DEBUG(id >= priv->num_core_clks); 339 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 340 341 if (!core->name) { 342 /* Skip NULLified clock */ 343 return; 344 } 345 346 switch (core->type) { 347 case CLK_TYPE_IN: 348 clk = of_clk_get_by_name(priv->np, core->name); 349 break; 350 351 case CLK_TYPE_FF: 352 case CLK_TYPE_DIV6P1: 353 case CLK_TYPE_DIV6_RO: 354 WARN_DEBUG(core->parent >= priv->num_core_clks); 355 parent = priv->clks[core->parent]; 356 if (IS_ERR(parent)) { 357 clk = parent; 358 goto fail; 359 } 360 361 parent_name = __clk_get_name(parent); 362 363 if (core->type == CLK_TYPE_DIV6_RO) 364 /* Multiply with the DIV6 register value */ 365 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 366 367 if (core->type == CLK_TYPE_DIV6P1) { 368 clk = cpg_div6_register(core->name, 1, &parent_name, 369 priv->base + core->offset, 370 &priv->notifiers); 371 } else { 372 clk = clk_register_fixed_factor(NULL, core->name, 373 parent_name, 0, 374 core->mult, div); 375 } 376 break; 377 378 case CLK_TYPE_FR: 379 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 380 core->mult); 381 break; 382 383 default: 384 if (info->cpg_clk_register) 385 clk = info->cpg_clk_register(dev, core, info, 386 priv->clks, priv->base, 387 &priv->notifiers); 388 else 389 dev_err(dev, "%s has unsupported core clock type %u\n", 390 core->name, core->type); 391 break; 392 } 393 394 if (IS_ERR_OR_NULL(clk)) 395 goto fail; 396 397 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 398 priv->clks[id] = clk; 399 return; 400 401 fail: 402 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 403 core->name, PTR_ERR(clk)); 404 } 405 406 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 407 const struct cpg_mssr_info *info, 408 struct cpg_mssr_priv *priv) 409 { 410 struct mstp_clock *clock = NULL; 411 struct device *dev = priv->dev; 412 unsigned int id = mod->id; 413 struct clk_init_data init = {}; 414 struct clk *parent, *clk; 415 const char *parent_name; 416 unsigned int i; 417 418 WARN_DEBUG(id < priv->num_core_clks); 419 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 420 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 421 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 422 423 if (!mod->name) { 424 /* Skip NULLified clock */ 425 return; 426 } 427 428 parent = priv->clks[mod->parent]; 429 if (IS_ERR(parent)) { 430 clk = parent; 431 goto fail; 432 } 433 434 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 435 if (!clock) { 436 clk = ERR_PTR(-ENOMEM); 437 goto fail; 438 } 439 440 init.name = mod->name; 441 init.ops = &cpg_mstp_clock_ops; 442 init.flags = CLK_SET_RATE_PARENT; 443 parent_name = __clk_get_name(parent); 444 init.parent_names = &parent_name; 445 init.num_parents = 1; 446 447 clock->index = id - priv->num_core_clks; 448 clock->priv = priv; 449 clock->hw.init = &init; 450 451 for (i = 0; i < info->num_crit_mod_clks; i++) 452 if (id == info->crit_mod_clks[i] && 453 cpg_mstp_clock_is_enabled(&clock->hw)) { 454 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 455 mod->name); 456 init.flags |= CLK_IS_CRITICAL; 457 break; 458 } 459 460 /* 461 * Ignore reserved device. 462 * see 463 * cpg_mssr_reserved_init() 464 */ 465 for (i = 0; i < priv->num_reserved_ids; i++) { 466 if (id == priv->reserved_ids[i]) { 467 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); 468 init.flags |= CLK_IGNORE_UNUSED; 469 break; 470 } 471 } 472 473 clk = clk_register(NULL, &clock->hw); 474 if (IS_ERR(clk)) 475 goto fail; 476 477 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 478 priv->clks[id] = clk; 479 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 480 return; 481 482 fail: 483 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 484 mod->name, PTR_ERR(clk)); 485 kfree(clock); 486 } 487 488 struct cpg_mssr_clk_domain { 489 struct generic_pm_domain genpd; 490 unsigned int num_core_pm_clks; 491 unsigned int core_pm_clks[]; 492 }; 493 494 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 495 496 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 497 struct cpg_mssr_clk_domain *pd) 498 { 499 unsigned int i; 500 501 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) 502 return false; 503 504 switch (clkspec->args[0]) { 505 case CPG_CORE: 506 for (i = 0; i < pd->num_core_pm_clks; i++) 507 if (clkspec->args[1] == pd->core_pm_clks[i]) 508 return true; 509 return false; 510 511 case CPG_MOD: 512 return true; 513 514 default: 515 return false; 516 } 517 } 518 519 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 520 { 521 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 522 struct device_node *np = dev->of_node; 523 struct of_phandle_args clkspec; 524 struct clk *clk; 525 int i = 0; 526 int error; 527 528 if (!pd) { 529 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 530 return -EPROBE_DEFER; 531 } 532 533 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 534 &clkspec)) { 535 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 536 goto found; 537 538 of_node_put(clkspec.np); 539 i++; 540 } 541 542 return 0; 543 544 found: 545 clk = of_clk_get_from_provider(&clkspec); 546 of_node_put(clkspec.np); 547 548 if (IS_ERR(clk)) 549 return PTR_ERR(clk); 550 551 error = pm_clk_create(dev); 552 if (error) 553 goto fail_put; 554 555 error = pm_clk_add_clk(dev, clk); 556 if (error) 557 goto fail_destroy; 558 559 return 0; 560 561 fail_destroy: 562 pm_clk_destroy(dev); 563 fail_put: 564 clk_put(clk); 565 return error; 566 } 567 568 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 569 { 570 if (!pm_clk_no_clocks(dev)) 571 pm_clk_destroy(dev); 572 } 573 574 static void cpg_mssr_genpd_remove(void *data) 575 { 576 pm_genpd_remove(data); 577 } 578 579 static int __init cpg_mssr_add_clk_domain(struct device *dev, 580 const unsigned int *core_pm_clks, 581 unsigned int num_core_pm_clks) 582 { 583 struct device_node *np = dev->of_node; 584 struct generic_pm_domain *genpd; 585 struct cpg_mssr_clk_domain *pd; 586 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 587 int ret; 588 589 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 590 if (!pd) 591 return -ENOMEM; 592 593 pd->num_core_pm_clks = num_core_pm_clks; 594 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 595 596 genpd = &pd->genpd; 597 genpd->name = np->name; 598 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 599 GENPD_FLAG_ACTIVE_WAKEUP; 600 genpd->attach_dev = cpg_mssr_attach_dev; 601 genpd->detach_dev = cpg_mssr_detach_dev; 602 ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 603 if (ret) 604 return ret; 605 606 ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd); 607 if (ret) 608 return ret; 609 610 cpg_mssr_clk_domain = pd; 611 612 return of_genpd_add_provider_simple(np, genpd); 613 } 614 615 #ifdef CONFIG_RESET_CONTROLLER 616 617 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 618 619 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 620 unsigned long id) 621 { 622 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 623 unsigned int reg = id / 32; 624 unsigned int bit = id % 32; 625 u32 bitmask = BIT(bit); 626 627 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 628 629 /* Reset module */ 630 writel(bitmask, priv->base + priv->reset_regs[reg]); 631 632 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 633 udelay(35); 634 635 /* Release module from reset state */ 636 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 637 638 return 0; 639 } 640 641 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 642 { 643 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 644 unsigned int reg = id / 32; 645 unsigned int bit = id % 32; 646 u32 bitmask = BIT(bit); 647 648 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 649 650 writel(bitmask, priv->base + priv->reset_regs[reg]); 651 return 0; 652 } 653 654 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 655 unsigned long id) 656 { 657 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 658 unsigned int reg = id / 32; 659 unsigned int bit = id % 32; 660 u32 bitmask = BIT(bit); 661 662 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 663 664 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 665 return 0; 666 } 667 668 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 669 unsigned long id) 670 { 671 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 672 unsigned int reg = id / 32; 673 unsigned int bit = id % 32; 674 u32 bitmask = BIT(bit); 675 676 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); 677 } 678 679 static const struct reset_control_ops cpg_mssr_reset_ops = { 680 .reset = cpg_mssr_reset, 681 .assert = cpg_mssr_assert, 682 .deassert = cpg_mssr_deassert, 683 .status = cpg_mssr_status, 684 }; 685 686 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 687 const struct of_phandle_args *reset_spec) 688 { 689 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 690 unsigned int unpacked = reset_spec->args[0]; 691 unsigned int idx = MOD_CLK_PACK(unpacked); 692 693 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 694 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 695 return -EINVAL; 696 } 697 698 return idx; 699 } 700 701 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 702 { 703 priv->rcdev.ops = &cpg_mssr_reset_ops; 704 priv->rcdev.of_node = priv->dev->of_node; 705 priv->rcdev.of_reset_n_cells = 1; 706 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 707 priv->rcdev.nr_resets = priv->num_mod_clks; 708 return devm_reset_controller_register(priv->dev, &priv->rcdev); 709 } 710 711 #else /* !CONFIG_RESET_CONTROLLER */ 712 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 713 { 714 return 0; 715 } 716 #endif /* !CONFIG_RESET_CONTROLLER */ 717 718 static const struct of_device_id cpg_mssr_match[] = { 719 #ifdef CONFIG_CLK_R7S9210 720 { 721 .compatible = "renesas,r7s9210-cpg-mssr", 722 .data = &r7s9210_cpg_mssr_info, 723 }, 724 #endif 725 #ifdef CONFIG_CLK_R8A7742 726 { 727 .compatible = "renesas,r8a7742-cpg-mssr", 728 .data = &r8a7742_cpg_mssr_info, 729 }, 730 #endif 731 #ifdef CONFIG_CLK_R8A7743 732 { 733 .compatible = "renesas,r8a7743-cpg-mssr", 734 .data = &r8a7743_cpg_mssr_info, 735 }, 736 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 737 { 738 .compatible = "renesas,r8a7744-cpg-mssr", 739 .data = &r8a7743_cpg_mssr_info, 740 }, 741 #endif 742 #ifdef CONFIG_CLK_R8A7745 743 { 744 .compatible = "renesas,r8a7745-cpg-mssr", 745 .data = &r8a7745_cpg_mssr_info, 746 }, 747 #endif 748 #ifdef CONFIG_CLK_R8A77470 749 { 750 .compatible = "renesas,r8a77470-cpg-mssr", 751 .data = &r8a77470_cpg_mssr_info, 752 }, 753 #endif 754 #ifdef CONFIG_CLK_R8A774A1 755 { 756 .compatible = "renesas,r8a774a1-cpg-mssr", 757 .data = &r8a774a1_cpg_mssr_info, 758 }, 759 #endif 760 #ifdef CONFIG_CLK_R8A774B1 761 { 762 .compatible = "renesas,r8a774b1-cpg-mssr", 763 .data = &r8a774b1_cpg_mssr_info, 764 }, 765 #endif 766 #ifdef CONFIG_CLK_R8A774C0 767 { 768 .compatible = "renesas,r8a774c0-cpg-mssr", 769 .data = &r8a774c0_cpg_mssr_info, 770 }, 771 #endif 772 #ifdef CONFIG_CLK_R8A774E1 773 { 774 .compatible = "renesas,r8a774e1-cpg-mssr", 775 .data = &r8a774e1_cpg_mssr_info, 776 }, 777 #endif 778 #ifdef CONFIG_CLK_R8A7790 779 { 780 .compatible = "renesas,r8a7790-cpg-mssr", 781 .data = &r8a7790_cpg_mssr_info, 782 }, 783 #endif 784 #ifdef CONFIG_CLK_R8A7791 785 { 786 .compatible = "renesas,r8a7791-cpg-mssr", 787 .data = &r8a7791_cpg_mssr_info, 788 }, 789 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 790 { 791 .compatible = "renesas,r8a7793-cpg-mssr", 792 .data = &r8a7791_cpg_mssr_info, 793 }, 794 #endif 795 #ifdef CONFIG_CLK_R8A7792 796 { 797 .compatible = "renesas,r8a7792-cpg-mssr", 798 .data = &r8a7792_cpg_mssr_info, 799 }, 800 #endif 801 #ifdef CONFIG_CLK_R8A7794 802 { 803 .compatible = "renesas,r8a7794-cpg-mssr", 804 .data = &r8a7794_cpg_mssr_info, 805 }, 806 #endif 807 #ifdef CONFIG_CLK_R8A7795 808 { 809 .compatible = "renesas,r8a7795-cpg-mssr", 810 .data = &r8a7795_cpg_mssr_info, 811 }, 812 #endif 813 #ifdef CONFIG_CLK_R8A77960 814 { 815 .compatible = "renesas,r8a7796-cpg-mssr", 816 .data = &r8a7796_cpg_mssr_info, 817 }, 818 #endif 819 #ifdef CONFIG_CLK_R8A77961 820 { 821 .compatible = "renesas,r8a77961-cpg-mssr", 822 .data = &r8a7796_cpg_mssr_info, 823 }, 824 #endif 825 #ifdef CONFIG_CLK_R8A77965 826 { 827 .compatible = "renesas,r8a77965-cpg-mssr", 828 .data = &r8a77965_cpg_mssr_info, 829 }, 830 #endif 831 #ifdef CONFIG_CLK_R8A77970 832 { 833 .compatible = "renesas,r8a77970-cpg-mssr", 834 .data = &r8a77970_cpg_mssr_info, 835 }, 836 #endif 837 #ifdef CONFIG_CLK_R8A77980 838 { 839 .compatible = "renesas,r8a77980-cpg-mssr", 840 .data = &r8a77980_cpg_mssr_info, 841 }, 842 #endif 843 #ifdef CONFIG_CLK_R8A77990 844 { 845 .compatible = "renesas,r8a77990-cpg-mssr", 846 .data = &r8a77990_cpg_mssr_info, 847 }, 848 #endif 849 #ifdef CONFIG_CLK_R8A77995 850 { 851 .compatible = "renesas,r8a77995-cpg-mssr", 852 .data = &r8a77995_cpg_mssr_info, 853 }, 854 #endif 855 #ifdef CONFIG_CLK_R8A779A0 856 { 857 .compatible = "renesas,r8a779a0-cpg-mssr", 858 .data = &r8a779a0_cpg_mssr_info, 859 }, 860 #endif 861 #ifdef CONFIG_CLK_R8A779F0 862 { 863 .compatible = "renesas,r8a779f0-cpg-mssr", 864 .data = &r8a779f0_cpg_mssr_info, 865 }, 866 #endif 867 #ifdef CONFIG_CLK_R8A779G0 868 { 869 .compatible = "renesas,r8a779g0-cpg-mssr", 870 .data = &r8a779g0_cpg_mssr_info, 871 }, 872 #endif 873 #ifdef CONFIG_CLK_R8A779H0 874 { 875 .compatible = "renesas,r8a779h0-cpg-mssr", 876 .data = &r8a779h0_cpg_mssr_info, 877 }, 878 #endif 879 { /* sentinel */ } 880 }; 881 882 static void cpg_mssr_del_clk_provider(void *data) 883 { 884 of_clk_del_provider(data); 885 } 886 887 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 888 static int cpg_mssr_suspend_noirq(struct device *dev) 889 { 890 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 891 unsigned int reg; 892 893 /* This is the best we can do to check for the presence of PSCI */ 894 if (!psci_ops.cpu_suspend) 895 return 0; 896 897 /* Save module registers with bits under our control */ 898 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 899 if (priv->smstpcr_saved[reg].mask) 900 priv->smstpcr_saved[reg].val = 901 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? 902 readb(priv->base + priv->control_regs[reg]) : 903 readl(priv->base + priv->control_regs[reg]); 904 } 905 906 /* Save core clocks */ 907 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 908 909 return 0; 910 } 911 912 static int cpg_mssr_resume_noirq(struct device *dev) 913 { 914 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 915 unsigned int reg; 916 u32 mask, oldval, newval; 917 int error; 918 919 /* This is the best we can do to check for the presence of PSCI */ 920 if (!psci_ops.cpu_suspend) 921 return 0; 922 923 /* Restore core clocks */ 924 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 925 926 /* Restore module clocks */ 927 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 928 mask = priv->smstpcr_saved[reg].mask; 929 if (!mask) 930 continue; 931 932 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 933 oldval = readb(priv->base + priv->control_regs[reg]); 934 else 935 oldval = readl(priv->base + priv->control_regs[reg]); 936 newval = oldval & ~mask; 937 newval |= priv->smstpcr_saved[reg].val & mask; 938 if (newval == oldval) 939 continue; 940 941 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 942 writeb(newval, priv->base + priv->control_regs[reg]); 943 /* dummy read to ensure write has completed */ 944 readb(priv->base + priv->control_regs[reg]); 945 barrier_data(priv->base + priv->control_regs[reg]); 946 continue; 947 } else 948 writel(newval, priv->base + priv->control_regs[reg]); 949 950 /* Wait until enabled clocks are really enabled */ 951 mask &= ~priv->smstpcr_saved[reg].val; 952 if (!mask) 953 continue; 954 955 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 956 oldval, !(oldval & mask), 0, 10); 957 if (error) 958 dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, 959 oldval & mask); 960 } 961 962 return 0; 963 } 964 965 static const struct dev_pm_ops cpg_mssr_pm = { 966 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 967 cpg_mssr_resume_noirq) 968 }; 969 #define DEV_PM_OPS &cpg_mssr_pm 970 #else 971 #define DEV_PM_OPS NULL 972 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 973 974 static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv) 975 { 976 kfree(priv->reserved_ids); 977 } 978 979 static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv, 980 const struct cpg_mssr_info *info) 981 { 982 struct device_node *soc = of_find_node_by_path("/soc"); 983 struct device_node *node; 984 uint32_t args[MAX_PHANDLE_ARGS]; 985 unsigned int *ids = NULL; 986 unsigned int num = 0; 987 988 /* 989 * Because clk_disable_unused() will disable all unused clocks, the device which is assigned 990 * to a non-Linux system will be disabled when Linux is booted. 991 * 992 * To avoid such situation, renesas-cpg-mssr assumes the device which has 993 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag 994 * to its CPG_MOD clocks. 995 * see also 996 * cpg_mssr_register_mod_clk() 997 * 998 * scif5: serial@e6f30000 { 999 * ... 1000 * => clocks = <&cpg CPG_MOD 202>, 1001 * <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1002 * <&scif_clk>; 1003 * ... 1004 * status = "reserved"; 1005 * }; 1006 */ 1007 for_each_reserved_child_of_node(soc, node) { 1008 struct of_phandle_iterator it; 1009 int rc; 1010 1011 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { 1012 int idx; 1013 1014 if (it.node != priv->np) 1015 continue; 1016 1017 if (of_phandle_iterator_args(&it, args, MAX_PHANDLE_ARGS) != 2) 1018 continue; 1019 1020 if (args[0] != CPG_MOD) 1021 continue; 1022 1023 ids = krealloc_array(ids, (num + 1), sizeof(*ids), GFP_KERNEL); 1024 if (!ids) { 1025 of_node_put(it.node); 1026 return -ENOMEM; 1027 } 1028 1029 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 1030 idx = MOD_CLK_PACK_10(args[1]); /* for DEF_MOD_STB() */ 1031 else 1032 idx = MOD_CLK_PACK(args[1]); /* for DEF_MOD() */ 1033 1034 ids[num] = info->num_total_core_clks + idx; 1035 1036 num++; 1037 } 1038 } 1039 1040 priv->num_reserved_ids = num; 1041 priv->reserved_ids = ids; 1042 1043 return 0; 1044 } 1045 1046 static int __init cpg_mssr_common_init(struct device *dev, 1047 struct device_node *np, 1048 const struct cpg_mssr_info *info) 1049 { 1050 struct cpg_mssr_priv *priv; 1051 unsigned int nclks, i; 1052 int error; 1053 1054 if (info->init) { 1055 error = info->init(dev); 1056 if (error) 1057 return error; 1058 } 1059 1060 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 1061 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL); 1062 if (!priv) 1063 return -ENOMEM; 1064 1065 priv->np = np; 1066 priv->dev = dev; 1067 spin_lock_init(&priv->rmw_lock); 1068 1069 priv->base = of_iomap(np, 0); 1070 if (!priv->base) { 1071 error = -ENOMEM; 1072 goto out_err; 1073 } 1074 1075 priv->num_core_clks = info->num_total_core_clks; 1076 priv->num_mod_clks = info->num_hw_mod_clks; 1077 priv->last_dt_core_clk = info->last_dt_core_clk; 1078 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 1079 priv->reg_layout = info->reg_layout; 1080 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { 1081 priv->status_regs = mstpsr; 1082 priv->control_regs = smstpcr; 1083 priv->reset_regs = srcr; 1084 priv->reset_clear_regs = srstclr; 1085 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 1086 priv->control_regs = stbcr; 1087 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { 1088 priv->status_regs = mstpsr_for_gen4; 1089 priv->control_regs = mstpcr_for_gen4; 1090 priv->reset_regs = srcr_for_gen4; 1091 priv->reset_clear_regs = srstclr_for_gen4; 1092 } else { 1093 error = -EINVAL; 1094 goto out_err; 1095 } 1096 1097 for (i = 0; i < nclks; i++) 1098 priv->clks[i] = ERR_PTR(-ENOENT); 1099 1100 error = cpg_mssr_reserved_init(priv, info); 1101 if (error) 1102 goto out_err; 1103 1104 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 1105 if (error) 1106 goto reserve_err; 1107 1108 cpg_mssr_priv = priv; 1109 1110 return 0; 1111 1112 reserve_err: 1113 cpg_mssr_reserved_exit(priv); 1114 out_err: 1115 if (priv->base) 1116 iounmap(priv->base); 1117 kfree(priv); 1118 1119 return error; 1120 } 1121 1122 void __init cpg_mssr_early_init(struct device_node *np, 1123 const struct cpg_mssr_info *info) 1124 { 1125 int error; 1126 int i; 1127 1128 error = cpg_mssr_common_init(NULL, np, info); 1129 if (error) 1130 return; 1131 1132 for (i = 0; i < info->num_early_core_clks; i++) 1133 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 1134 cpg_mssr_priv); 1135 1136 for (i = 0; i < info->num_early_mod_clks; i++) 1137 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 1138 cpg_mssr_priv); 1139 1140 } 1141 1142 static int __init cpg_mssr_probe(struct platform_device *pdev) 1143 { 1144 struct device *dev = &pdev->dev; 1145 struct device_node *np = dev->of_node; 1146 const struct cpg_mssr_info *info; 1147 struct cpg_mssr_priv *priv; 1148 unsigned int i; 1149 int error; 1150 1151 info = of_device_get_match_data(dev); 1152 1153 if (!cpg_mssr_priv) { 1154 error = cpg_mssr_common_init(dev, dev->of_node, info); 1155 if (error) 1156 return error; 1157 } 1158 1159 priv = cpg_mssr_priv; 1160 priv->dev = dev; 1161 dev_set_drvdata(dev, priv); 1162 1163 for (i = 0; i < info->num_core_clks; i++) 1164 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 1165 1166 for (i = 0; i < info->num_mod_clks; i++) 1167 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1168 1169 error = devm_add_action_or_reset(dev, 1170 cpg_mssr_del_clk_provider, 1171 np); 1172 if (error) 1173 goto reserve_exit; 1174 1175 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1176 info->num_core_pm_clks); 1177 if (error) 1178 goto reserve_exit; 1179 1180 /* Reset Controller not supported for Standby Control SoCs */ 1181 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 1182 goto reserve_exit; 1183 1184 error = cpg_mssr_reset_controller_register(priv); 1185 1186 reserve_exit: 1187 cpg_mssr_reserved_exit(priv); 1188 1189 return error; 1190 } 1191 1192 static struct platform_driver cpg_mssr_driver = { 1193 .driver = { 1194 .name = "renesas-cpg-mssr", 1195 .of_match_table = cpg_mssr_match, 1196 .pm = DEV_PM_OPS, 1197 }, 1198 }; 1199 1200 static int __init cpg_mssr_init(void) 1201 { 1202 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1203 } 1204 1205 subsys_initcall(cpg_mssr_init); 1206 1207 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1208 unsigned int num_mod_clks, 1209 const unsigned int *clks, unsigned int n) 1210 { 1211 unsigned int i, j; 1212 1213 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1214 if (mod_clks[i].id == clks[j]) { 1215 mod_clks[i].name = NULL; 1216 j++; 1217 } 1218 } 1219 1220 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1221