1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/of_address.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_clock.h> 26 #include <linux/pm_domain.h> 27 #include <linux/psci.h> 28 #include <linux/reset-controller.h> 29 #include <linux/slab.h> 30 31 #include <dt-bindings/clock/renesas-cpg-mssr.h> 32 33 #include "renesas-cpg-mssr.h" 34 #include "clk-div6.h" 35 36 #ifdef DEBUG 37 #define WARN_DEBUG(x) WARN_ON(x) 38 #else 39 #define WARN_DEBUG(x) do { } while (0) 40 #endif 41 42 43 /* 44 * Module Standby and Software Reset register offets. 45 * 46 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 47 * R-Car Gen2, R-Car Gen3, and RZ/G1. 48 * These are NOT valid for R-Car Gen1 and RZ/A1! 49 */ 50 51 /* 52 * Module Stop Status Register offsets 53 */ 54 55 static const u16 mstpsr[] = { 56 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 57 0x9A0, 0x9A4, 0x9A8, 0x9AC, 58 }; 59 60 static const u16 mstpsr_for_gen4[] = { 61 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, 62 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, 63 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, 64 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74, 65 }; 66 67 /* 68 * System Module Stop Control Register offsets 69 */ 70 71 static const u16 smstpcr[] = { 72 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 73 0x990, 0x994, 0x998, 0x99C, 74 }; 75 76 static const u16 mstpcr_for_gen4[] = { 77 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, 78 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, 79 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, 80 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74, 81 }; 82 83 /* 84 * Standby Control Register offsets (RZ/A) 85 * Base address is FRQCR register 86 */ 87 88 static const u16 stbcr[] = { 89 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 90 0x424, 0x428, 0x42C, 91 }; 92 93 /* 94 * Software Reset Register offsets 95 */ 96 97 static const u16 srcr[] = { 98 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 99 0x920, 0x924, 0x928, 0x92C, 100 }; 101 102 static const u16 srcr_for_gen4[] = { 103 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, 104 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, 105 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, 106 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, 107 }; 108 109 /* 110 * Software Reset Clearing Register offsets 111 */ 112 113 static const u16 srstclr[] = { 114 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, 115 0x960, 0x964, 0x968, 0x96C, 116 }; 117 118 static const u16 srstclr_for_gen4[] = { 119 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, 120 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, 121 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, 122 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4, 123 }; 124 125 /** 126 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby 127 * and Software Reset Private Data 128 * 129 * @rcdev: Optional reset controller entity 130 * @dev: CPG/MSSR device 131 * @base: CPG/MSSR register block base address 132 * @reg_layout: CPG/MSSR register layout 133 * @rmw_lock: protects RMW register accesses 134 * @np: Device node in DT for this CPG/MSSR module 135 * @num_core_clks: Number of Core Clocks in clks[] 136 * @num_mod_clks: Number of Module Clocks in clks[] 137 * @last_dt_core_clk: ID of the last Core Clock exported to DT 138 * @notifiers: Notifier chain to save/restore clock state for system resume 139 * @status_regs: Pointer to status registers array 140 * @control_regs: Pointer to control registers array 141 * @reset_regs: Pointer to reset registers array 142 * @reset_clear_regs: Pointer to reset clearing registers array 143 * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control 144 * [].val: Saved values of SMSTPCR[] 145 * @reserved_ids: Temporary used, reserved id list 146 * @num_reserved_ids: Temporary used, number of reserved id list 147 * @clks: Array containing all Core and Module Clocks 148 */ 149 struct cpg_mssr_priv { 150 #ifdef CONFIG_RESET_CONTROLLER 151 struct reset_controller_dev rcdev; 152 #endif 153 struct device *dev; 154 void __iomem *base; 155 enum clk_reg_layout reg_layout; 156 spinlock_t rmw_lock; 157 struct device_node *np; 158 159 unsigned int num_core_clks; 160 unsigned int num_mod_clks; 161 unsigned int last_dt_core_clk; 162 163 struct raw_notifier_head notifiers; 164 const u16 *status_regs; 165 const u16 *control_regs; 166 const u16 *reset_regs; 167 const u16 *reset_clear_regs; 168 struct { 169 u32 mask; 170 u32 val; 171 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; 172 173 unsigned int *reserved_ids; 174 unsigned int num_reserved_ids; 175 176 struct clk *clks[]; 177 }; 178 179 static struct cpg_mssr_priv *cpg_mssr_priv; 180 181 /** 182 * struct mstp_clock - MSTP gating clock 183 * @hw: handle between common and hardware-specific interfaces 184 * @index: MSTP clock number 185 * @priv: CPG/MSSR private data 186 */ 187 struct mstp_clock { 188 struct clk_hw hw; 189 u32 index; 190 struct cpg_mssr_priv *priv; 191 }; 192 193 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 194 195 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 196 { 197 struct mstp_clock *clock = to_mstp_clock(hw); 198 struct cpg_mssr_priv *priv = clock->priv; 199 unsigned int reg = clock->index / 32; 200 unsigned int bit = clock->index % 32; 201 struct device *dev = priv->dev; 202 u32 bitmask = BIT(bit); 203 unsigned long flags; 204 u32 value; 205 int error; 206 207 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 208 enable ? "ON" : "OFF"); 209 spin_lock_irqsave(&priv->rmw_lock, flags); 210 211 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 212 value = readb(priv->base + priv->control_regs[reg]); 213 if (enable) 214 value &= ~bitmask; 215 else 216 value |= bitmask; 217 writeb(value, priv->base + priv->control_regs[reg]); 218 219 /* dummy read to ensure write has completed */ 220 readb(priv->base + priv->control_regs[reg]); 221 barrier_data(priv->base + priv->control_regs[reg]); 222 } else { 223 value = readl(priv->base + priv->control_regs[reg]); 224 if (enable) 225 value &= ~bitmask; 226 else 227 value |= bitmask; 228 writel(value, priv->base + priv->control_regs[reg]); 229 } 230 231 spin_unlock_irqrestore(&priv->rmw_lock, flags); 232 233 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 234 return 0; 235 236 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 237 value, !(value & bitmask), 0, 10); 238 if (error) 239 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 240 priv->base + priv->control_regs[reg], bit); 241 242 return error; 243 } 244 245 static int cpg_mstp_clock_enable(struct clk_hw *hw) 246 { 247 return cpg_mstp_clock_endisable(hw, true); 248 } 249 250 static void cpg_mstp_clock_disable(struct clk_hw *hw) 251 { 252 cpg_mstp_clock_endisable(hw, false); 253 } 254 255 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 256 { 257 struct mstp_clock *clock = to_mstp_clock(hw); 258 struct cpg_mssr_priv *priv = clock->priv; 259 u32 value; 260 261 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 262 value = readb(priv->base + priv->control_regs[clock->index / 32]); 263 else 264 value = readl(priv->base + priv->status_regs[clock->index / 32]); 265 266 return !(value & BIT(clock->index % 32)); 267 } 268 269 static const struct clk_ops cpg_mstp_clock_ops = { 270 .enable = cpg_mstp_clock_enable, 271 .disable = cpg_mstp_clock_disable, 272 .is_enabled = cpg_mstp_clock_is_enabled, 273 }; 274 275 static 276 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 277 void *data) 278 { 279 unsigned int clkidx = clkspec->args[1]; 280 struct cpg_mssr_priv *priv = data; 281 struct device *dev = priv->dev; 282 unsigned int idx; 283 const char *type; 284 struct clk *clk; 285 int range_check; 286 287 switch (clkspec->args[0]) { 288 case CPG_CORE: 289 type = "core"; 290 if (clkidx > priv->last_dt_core_clk) { 291 dev_err(dev, "Invalid %s clock index %u\n", type, 292 clkidx); 293 return ERR_PTR(-EINVAL); 294 } 295 clk = priv->clks[clkidx]; 296 break; 297 298 case CPG_MOD: 299 type = "module"; 300 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 301 idx = MOD_CLK_PACK_10(clkidx); 302 range_check = 7 - (clkidx % 10); 303 } else { 304 idx = MOD_CLK_PACK(clkidx); 305 range_check = 31 - (clkidx % 100); 306 } 307 if (range_check < 0 || idx >= priv->num_mod_clks) { 308 dev_err(dev, "Invalid %s clock index %u\n", type, 309 clkidx); 310 return ERR_PTR(-EINVAL); 311 } 312 clk = priv->clks[priv->num_core_clks + idx]; 313 break; 314 315 default: 316 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 317 return ERR_PTR(-EINVAL); 318 } 319 320 if (IS_ERR(clk)) 321 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 322 PTR_ERR(clk)); 323 else 324 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 325 clkspec->args[0], clkspec->args[1], clk, 326 clk_get_rate(clk)); 327 return clk; 328 } 329 330 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 331 const struct cpg_mssr_info *info, 332 struct cpg_mssr_priv *priv) 333 { 334 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 335 struct device *dev = priv->dev; 336 unsigned int id = core->id, div = core->div; 337 const char *parent_name; 338 339 WARN_DEBUG(id >= priv->num_core_clks); 340 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 341 342 if (!core->name) { 343 /* Skip NULLified clock */ 344 return; 345 } 346 347 switch (core->type) { 348 case CLK_TYPE_IN: 349 clk = of_clk_get_by_name(priv->np, core->name); 350 break; 351 352 case CLK_TYPE_FF: 353 case CLK_TYPE_DIV6P1: 354 case CLK_TYPE_DIV6_RO: 355 WARN_DEBUG(core->parent >= priv->num_core_clks); 356 parent = priv->clks[core->parent]; 357 if (IS_ERR(parent)) { 358 clk = parent; 359 goto fail; 360 } 361 362 parent_name = __clk_get_name(parent); 363 364 if (core->type == CLK_TYPE_DIV6_RO) 365 /* Multiply with the DIV6 register value */ 366 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 367 368 if (core->type == CLK_TYPE_DIV6P1) { 369 clk = cpg_div6_register(core->name, 1, &parent_name, 370 priv->base + core->offset, 371 &priv->notifiers); 372 } else { 373 clk = clk_register_fixed_factor(NULL, core->name, 374 parent_name, 0, 375 core->mult, div); 376 } 377 break; 378 379 case CLK_TYPE_FR: 380 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 381 core->mult); 382 break; 383 384 default: 385 if (info->cpg_clk_register) 386 clk = info->cpg_clk_register(dev, core, info, 387 priv->clks, priv->base, 388 &priv->notifiers); 389 else 390 dev_err(dev, "%s has unsupported core clock type %u\n", 391 core->name, core->type); 392 break; 393 } 394 395 if (IS_ERR_OR_NULL(clk)) 396 goto fail; 397 398 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 399 priv->clks[id] = clk; 400 return; 401 402 fail: 403 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 404 core->name, PTR_ERR(clk)); 405 } 406 407 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 408 const struct cpg_mssr_info *info, 409 struct cpg_mssr_priv *priv) 410 { 411 struct mstp_clock *clock = NULL; 412 struct device *dev = priv->dev; 413 unsigned int id = mod->id; 414 struct clk_init_data init = {}; 415 struct clk *parent, *clk; 416 const char *parent_name; 417 unsigned int i; 418 419 WARN_DEBUG(id < priv->num_core_clks); 420 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 421 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 422 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 423 424 if (!mod->name) { 425 /* Skip NULLified clock */ 426 return; 427 } 428 429 parent = priv->clks[mod->parent]; 430 if (IS_ERR(parent)) { 431 clk = parent; 432 goto fail; 433 } 434 435 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 436 if (!clock) { 437 clk = ERR_PTR(-ENOMEM); 438 goto fail; 439 } 440 441 init.name = mod->name; 442 init.ops = &cpg_mstp_clock_ops; 443 init.flags = CLK_SET_RATE_PARENT; 444 parent_name = __clk_get_name(parent); 445 init.parent_names = &parent_name; 446 init.num_parents = 1; 447 448 clock->index = id - priv->num_core_clks; 449 clock->priv = priv; 450 clock->hw.init = &init; 451 452 for (i = 0; i < info->num_crit_mod_clks; i++) 453 if (id == info->crit_mod_clks[i] && 454 cpg_mstp_clock_is_enabled(&clock->hw)) { 455 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 456 mod->name); 457 init.flags |= CLK_IS_CRITICAL; 458 break; 459 } 460 461 /* 462 * Ignore reserved device. 463 * see 464 * cpg_mssr_reserved_init() 465 */ 466 for (i = 0; i < priv->num_reserved_ids; i++) { 467 if (id == priv->reserved_ids[i]) { 468 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); 469 init.flags |= CLK_IGNORE_UNUSED; 470 break; 471 } 472 } 473 474 clk = clk_register(NULL, &clock->hw); 475 if (IS_ERR(clk)) 476 goto fail; 477 478 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 479 priv->clks[id] = clk; 480 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 481 return; 482 483 fail: 484 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 485 mod->name, PTR_ERR(clk)); 486 kfree(clock); 487 } 488 489 struct cpg_mssr_clk_domain { 490 struct generic_pm_domain genpd; 491 unsigned int num_core_pm_clks; 492 unsigned int core_pm_clks[]; 493 }; 494 495 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 496 497 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 498 struct cpg_mssr_clk_domain *pd) 499 { 500 unsigned int i; 501 502 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) 503 return false; 504 505 switch (clkspec->args[0]) { 506 case CPG_CORE: 507 for (i = 0; i < pd->num_core_pm_clks; i++) 508 if (clkspec->args[1] == pd->core_pm_clks[i]) 509 return true; 510 return false; 511 512 case CPG_MOD: 513 return true; 514 515 default: 516 return false; 517 } 518 } 519 520 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 521 { 522 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 523 struct device_node *np = dev->of_node; 524 struct of_phandle_args clkspec; 525 struct clk *clk; 526 int i = 0; 527 int error; 528 529 if (!pd) { 530 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 531 return -EPROBE_DEFER; 532 } 533 534 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 535 &clkspec)) { 536 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 537 goto found; 538 539 of_node_put(clkspec.np); 540 i++; 541 } 542 543 return 0; 544 545 found: 546 clk = of_clk_get_from_provider(&clkspec); 547 of_node_put(clkspec.np); 548 549 if (IS_ERR(clk)) 550 return PTR_ERR(clk); 551 552 error = pm_clk_create(dev); 553 if (error) 554 goto fail_put; 555 556 error = pm_clk_add_clk(dev, clk); 557 if (error) 558 goto fail_destroy; 559 560 return 0; 561 562 fail_destroy: 563 pm_clk_destroy(dev); 564 fail_put: 565 clk_put(clk); 566 return error; 567 } 568 569 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 570 { 571 if (!pm_clk_no_clocks(dev)) 572 pm_clk_destroy(dev); 573 } 574 575 static void cpg_mssr_genpd_remove(void *data) 576 { 577 pm_genpd_remove(data); 578 } 579 580 static int __init cpg_mssr_add_clk_domain(struct device *dev, 581 const unsigned int *core_pm_clks, 582 unsigned int num_core_pm_clks) 583 { 584 struct device_node *np = dev->of_node; 585 struct generic_pm_domain *genpd; 586 struct cpg_mssr_clk_domain *pd; 587 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 588 int ret; 589 590 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 591 if (!pd) 592 return -ENOMEM; 593 594 pd->num_core_pm_clks = num_core_pm_clks; 595 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 596 597 genpd = &pd->genpd; 598 genpd->name = np->name; 599 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 600 GENPD_FLAG_ACTIVE_WAKEUP; 601 genpd->attach_dev = cpg_mssr_attach_dev; 602 genpd->detach_dev = cpg_mssr_detach_dev; 603 ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 604 if (ret) 605 return ret; 606 607 ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd); 608 if (ret) 609 return ret; 610 611 cpg_mssr_clk_domain = pd; 612 613 return of_genpd_add_provider_simple(np, genpd); 614 } 615 616 #ifdef CONFIG_RESET_CONTROLLER 617 618 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 619 620 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 621 unsigned long id) 622 { 623 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 624 unsigned int reg = id / 32; 625 unsigned int bit = id % 32; 626 u32 bitmask = BIT(bit); 627 628 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 629 630 /* Reset module */ 631 writel(bitmask, priv->base + priv->reset_regs[reg]); 632 633 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 634 udelay(35); 635 636 /* Release module from reset state */ 637 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 638 639 return 0; 640 } 641 642 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 643 { 644 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 645 unsigned int reg = id / 32; 646 unsigned int bit = id % 32; 647 u32 bitmask = BIT(bit); 648 649 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 650 651 writel(bitmask, priv->base + priv->reset_regs[reg]); 652 return 0; 653 } 654 655 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 656 unsigned long id) 657 { 658 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 659 unsigned int reg = id / 32; 660 unsigned int bit = id % 32; 661 u32 bitmask = BIT(bit); 662 663 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 664 665 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 666 return 0; 667 } 668 669 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 670 unsigned long id) 671 { 672 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 673 unsigned int reg = id / 32; 674 unsigned int bit = id % 32; 675 u32 bitmask = BIT(bit); 676 677 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); 678 } 679 680 static const struct reset_control_ops cpg_mssr_reset_ops = { 681 .reset = cpg_mssr_reset, 682 .assert = cpg_mssr_assert, 683 .deassert = cpg_mssr_deassert, 684 .status = cpg_mssr_status, 685 }; 686 687 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 688 const struct of_phandle_args *reset_spec) 689 { 690 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 691 unsigned int unpacked = reset_spec->args[0]; 692 unsigned int idx = MOD_CLK_PACK(unpacked); 693 694 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 695 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 696 return -EINVAL; 697 } 698 699 return idx; 700 } 701 702 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 703 { 704 priv->rcdev.ops = &cpg_mssr_reset_ops; 705 priv->rcdev.of_node = priv->dev->of_node; 706 priv->rcdev.of_reset_n_cells = 1; 707 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 708 priv->rcdev.nr_resets = priv->num_mod_clks; 709 return devm_reset_controller_register(priv->dev, &priv->rcdev); 710 } 711 712 #else /* !CONFIG_RESET_CONTROLLER */ 713 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 714 { 715 return 0; 716 } 717 #endif /* !CONFIG_RESET_CONTROLLER */ 718 719 720 static const struct of_device_id cpg_mssr_match[] = { 721 #ifdef CONFIG_CLK_R7S9210 722 { 723 .compatible = "renesas,r7s9210-cpg-mssr", 724 .data = &r7s9210_cpg_mssr_info, 725 }, 726 #endif 727 #ifdef CONFIG_CLK_R8A7742 728 { 729 .compatible = "renesas,r8a7742-cpg-mssr", 730 .data = &r8a7742_cpg_mssr_info, 731 }, 732 #endif 733 #ifdef CONFIG_CLK_R8A7743 734 { 735 .compatible = "renesas,r8a7743-cpg-mssr", 736 .data = &r8a7743_cpg_mssr_info, 737 }, 738 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 739 { 740 .compatible = "renesas,r8a7744-cpg-mssr", 741 .data = &r8a7743_cpg_mssr_info, 742 }, 743 #endif 744 #ifdef CONFIG_CLK_R8A7745 745 { 746 .compatible = "renesas,r8a7745-cpg-mssr", 747 .data = &r8a7745_cpg_mssr_info, 748 }, 749 #endif 750 #ifdef CONFIG_CLK_R8A77470 751 { 752 .compatible = "renesas,r8a77470-cpg-mssr", 753 .data = &r8a77470_cpg_mssr_info, 754 }, 755 #endif 756 #ifdef CONFIG_CLK_R8A774A1 757 { 758 .compatible = "renesas,r8a774a1-cpg-mssr", 759 .data = &r8a774a1_cpg_mssr_info, 760 }, 761 #endif 762 #ifdef CONFIG_CLK_R8A774B1 763 { 764 .compatible = "renesas,r8a774b1-cpg-mssr", 765 .data = &r8a774b1_cpg_mssr_info, 766 }, 767 #endif 768 #ifdef CONFIG_CLK_R8A774C0 769 { 770 .compatible = "renesas,r8a774c0-cpg-mssr", 771 .data = &r8a774c0_cpg_mssr_info, 772 }, 773 #endif 774 #ifdef CONFIG_CLK_R8A774E1 775 { 776 .compatible = "renesas,r8a774e1-cpg-mssr", 777 .data = &r8a774e1_cpg_mssr_info, 778 }, 779 #endif 780 #ifdef CONFIG_CLK_R8A7790 781 { 782 .compatible = "renesas,r8a7790-cpg-mssr", 783 .data = &r8a7790_cpg_mssr_info, 784 }, 785 #endif 786 #ifdef CONFIG_CLK_R8A7791 787 { 788 .compatible = "renesas,r8a7791-cpg-mssr", 789 .data = &r8a7791_cpg_mssr_info, 790 }, 791 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 792 { 793 .compatible = "renesas,r8a7793-cpg-mssr", 794 .data = &r8a7791_cpg_mssr_info, 795 }, 796 #endif 797 #ifdef CONFIG_CLK_R8A7792 798 { 799 .compatible = "renesas,r8a7792-cpg-mssr", 800 .data = &r8a7792_cpg_mssr_info, 801 }, 802 #endif 803 #ifdef CONFIG_CLK_R8A7794 804 { 805 .compatible = "renesas,r8a7794-cpg-mssr", 806 .data = &r8a7794_cpg_mssr_info, 807 }, 808 #endif 809 #ifdef CONFIG_CLK_R8A7795 810 { 811 .compatible = "renesas,r8a7795-cpg-mssr", 812 .data = &r8a7795_cpg_mssr_info, 813 }, 814 #endif 815 #ifdef CONFIG_CLK_R8A77960 816 { 817 .compatible = "renesas,r8a7796-cpg-mssr", 818 .data = &r8a7796_cpg_mssr_info, 819 }, 820 #endif 821 #ifdef CONFIG_CLK_R8A77961 822 { 823 .compatible = "renesas,r8a77961-cpg-mssr", 824 .data = &r8a7796_cpg_mssr_info, 825 }, 826 #endif 827 #ifdef CONFIG_CLK_R8A77965 828 { 829 .compatible = "renesas,r8a77965-cpg-mssr", 830 .data = &r8a77965_cpg_mssr_info, 831 }, 832 #endif 833 #ifdef CONFIG_CLK_R8A77970 834 { 835 .compatible = "renesas,r8a77970-cpg-mssr", 836 .data = &r8a77970_cpg_mssr_info, 837 }, 838 #endif 839 #ifdef CONFIG_CLK_R8A77980 840 { 841 .compatible = "renesas,r8a77980-cpg-mssr", 842 .data = &r8a77980_cpg_mssr_info, 843 }, 844 #endif 845 #ifdef CONFIG_CLK_R8A77990 846 { 847 .compatible = "renesas,r8a77990-cpg-mssr", 848 .data = &r8a77990_cpg_mssr_info, 849 }, 850 #endif 851 #ifdef CONFIG_CLK_R8A77995 852 { 853 .compatible = "renesas,r8a77995-cpg-mssr", 854 .data = &r8a77995_cpg_mssr_info, 855 }, 856 #endif 857 #ifdef CONFIG_CLK_R8A779A0 858 { 859 .compatible = "renesas,r8a779a0-cpg-mssr", 860 .data = &r8a779a0_cpg_mssr_info, 861 }, 862 #endif 863 #ifdef CONFIG_CLK_R8A779F0 864 { 865 .compatible = "renesas,r8a779f0-cpg-mssr", 866 .data = &r8a779f0_cpg_mssr_info, 867 }, 868 #endif 869 #ifdef CONFIG_CLK_R8A779G0 870 { 871 .compatible = "renesas,r8a779g0-cpg-mssr", 872 .data = &r8a779g0_cpg_mssr_info, 873 }, 874 #endif 875 #ifdef CONFIG_CLK_R8A779H0 876 { 877 .compatible = "renesas,r8a779h0-cpg-mssr", 878 .data = &r8a779h0_cpg_mssr_info, 879 }, 880 #endif 881 { /* sentinel */ } 882 }; 883 884 static void cpg_mssr_del_clk_provider(void *data) 885 { 886 of_clk_del_provider(data); 887 } 888 889 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 890 static int cpg_mssr_suspend_noirq(struct device *dev) 891 { 892 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 893 unsigned int reg; 894 895 /* This is the best we can do to check for the presence of PSCI */ 896 if (!psci_ops.cpu_suspend) 897 return 0; 898 899 /* Save module registers with bits under our control */ 900 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 901 if (priv->smstpcr_saved[reg].mask) 902 priv->smstpcr_saved[reg].val = 903 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? 904 readb(priv->base + priv->control_regs[reg]) : 905 readl(priv->base + priv->control_regs[reg]); 906 } 907 908 /* Save core clocks */ 909 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 910 911 return 0; 912 } 913 914 static int cpg_mssr_resume_noirq(struct device *dev) 915 { 916 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 917 unsigned int reg; 918 u32 mask, oldval, newval; 919 int error; 920 921 /* This is the best we can do to check for the presence of PSCI */ 922 if (!psci_ops.cpu_suspend) 923 return 0; 924 925 /* Restore core clocks */ 926 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 927 928 /* Restore module clocks */ 929 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 930 mask = priv->smstpcr_saved[reg].mask; 931 if (!mask) 932 continue; 933 934 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 935 oldval = readb(priv->base + priv->control_regs[reg]); 936 else 937 oldval = readl(priv->base + priv->control_regs[reg]); 938 newval = oldval & ~mask; 939 newval |= priv->smstpcr_saved[reg].val & mask; 940 if (newval == oldval) 941 continue; 942 943 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 944 writeb(newval, priv->base + priv->control_regs[reg]); 945 /* dummy read to ensure write has completed */ 946 readb(priv->base + priv->control_regs[reg]); 947 barrier_data(priv->base + priv->control_regs[reg]); 948 continue; 949 } else 950 writel(newval, priv->base + priv->control_regs[reg]); 951 952 /* Wait until enabled clocks are really enabled */ 953 mask &= ~priv->smstpcr_saved[reg].val; 954 if (!mask) 955 continue; 956 957 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 958 oldval, !(oldval & mask), 0, 10); 959 if (error) 960 dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, 961 oldval & mask); 962 } 963 964 return 0; 965 } 966 967 static const struct dev_pm_ops cpg_mssr_pm = { 968 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 969 cpg_mssr_resume_noirq) 970 }; 971 #define DEV_PM_OPS &cpg_mssr_pm 972 #else 973 #define DEV_PM_OPS NULL 974 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 975 976 static void __init cpg_mssr_reserved_exit(struct cpg_mssr_priv *priv) 977 { 978 kfree(priv->reserved_ids); 979 } 980 981 static int __init cpg_mssr_reserved_init(struct cpg_mssr_priv *priv, 982 const struct cpg_mssr_info *info) 983 { 984 struct device_node *soc = of_find_node_by_path("/soc"); 985 struct device_node *node; 986 uint32_t args[MAX_PHANDLE_ARGS]; 987 unsigned int *ids = NULL; 988 unsigned int num = 0; 989 990 /* 991 * Because clk_disable_unused() will disable all unused clocks, the device which is assigned 992 * to a non-Linux system will be disabled when Linux is booted. 993 * 994 * To avoid such situation, renesas-cpg-mssr assumes the device which has 995 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag 996 * to its CPG_MOD clocks. 997 * see also 998 * cpg_mssr_register_mod_clk() 999 * 1000 * scif5: serial@e6f30000 { 1001 * ... 1002 * => clocks = <&cpg CPG_MOD 202>, 1003 * <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1004 * <&scif_clk>; 1005 * ... 1006 * status = "reserved"; 1007 * }; 1008 */ 1009 for_each_reserved_child_of_node(soc, node) { 1010 struct of_phandle_iterator it; 1011 int rc; 1012 1013 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { 1014 int idx; 1015 1016 if (it.node != priv->np) 1017 continue; 1018 1019 if (of_phandle_iterator_args(&it, args, MAX_PHANDLE_ARGS) != 2) 1020 continue; 1021 1022 if (args[0] != CPG_MOD) 1023 continue; 1024 1025 ids = krealloc_array(ids, (num + 1), sizeof(*ids), GFP_KERNEL); 1026 if (!ids) { 1027 of_node_put(it.node); 1028 return -ENOMEM; 1029 } 1030 1031 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 1032 idx = MOD_CLK_PACK_10(args[1]); /* for DEF_MOD_STB() */ 1033 else 1034 idx = MOD_CLK_PACK(args[1]); /* for DEF_MOD() */ 1035 1036 ids[num] = info->num_total_core_clks + idx; 1037 1038 num++; 1039 } 1040 } 1041 1042 priv->num_reserved_ids = num; 1043 priv->reserved_ids = ids; 1044 1045 return 0; 1046 } 1047 1048 static int __init cpg_mssr_common_init(struct device *dev, 1049 struct device_node *np, 1050 const struct cpg_mssr_info *info) 1051 { 1052 struct cpg_mssr_priv *priv; 1053 unsigned int nclks, i; 1054 int error; 1055 1056 if (info->init) { 1057 error = info->init(dev); 1058 if (error) 1059 return error; 1060 } 1061 1062 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 1063 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL); 1064 if (!priv) 1065 return -ENOMEM; 1066 1067 priv->np = np; 1068 priv->dev = dev; 1069 spin_lock_init(&priv->rmw_lock); 1070 1071 priv->base = of_iomap(np, 0); 1072 if (!priv->base) { 1073 error = -ENOMEM; 1074 goto out_err; 1075 } 1076 1077 priv->num_core_clks = info->num_total_core_clks; 1078 priv->num_mod_clks = info->num_hw_mod_clks; 1079 priv->last_dt_core_clk = info->last_dt_core_clk; 1080 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 1081 priv->reg_layout = info->reg_layout; 1082 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { 1083 priv->status_regs = mstpsr; 1084 priv->control_regs = smstpcr; 1085 priv->reset_regs = srcr; 1086 priv->reset_clear_regs = srstclr; 1087 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 1088 priv->control_regs = stbcr; 1089 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { 1090 priv->status_regs = mstpsr_for_gen4; 1091 priv->control_regs = mstpcr_for_gen4; 1092 priv->reset_regs = srcr_for_gen4; 1093 priv->reset_clear_regs = srstclr_for_gen4; 1094 } else { 1095 error = -EINVAL; 1096 goto out_err; 1097 } 1098 1099 for (i = 0; i < nclks; i++) 1100 priv->clks[i] = ERR_PTR(-ENOENT); 1101 1102 error = cpg_mssr_reserved_init(priv, info); 1103 if (error) 1104 goto out_err; 1105 1106 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 1107 if (error) 1108 goto reserve_err; 1109 1110 cpg_mssr_priv = priv; 1111 1112 return 0; 1113 1114 reserve_err: 1115 cpg_mssr_reserved_exit(priv); 1116 out_err: 1117 if (priv->base) 1118 iounmap(priv->base); 1119 kfree(priv); 1120 1121 return error; 1122 } 1123 1124 void __init cpg_mssr_early_init(struct device_node *np, 1125 const struct cpg_mssr_info *info) 1126 { 1127 int error; 1128 int i; 1129 1130 error = cpg_mssr_common_init(NULL, np, info); 1131 if (error) 1132 return; 1133 1134 for (i = 0; i < info->num_early_core_clks; i++) 1135 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 1136 cpg_mssr_priv); 1137 1138 for (i = 0; i < info->num_early_mod_clks; i++) 1139 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 1140 cpg_mssr_priv); 1141 1142 } 1143 1144 static int __init cpg_mssr_probe(struct platform_device *pdev) 1145 { 1146 struct device *dev = &pdev->dev; 1147 struct device_node *np = dev->of_node; 1148 const struct cpg_mssr_info *info; 1149 struct cpg_mssr_priv *priv; 1150 unsigned int i; 1151 int error; 1152 1153 info = of_device_get_match_data(dev); 1154 1155 if (!cpg_mssr_priv) { 1156 error = cpg_mssr_common_init(dev, dev->of_node, info); 1157 if (error) 1158 return error; 1159 } 1160 1161 priv = cpg_mssr_priv; 1162 priv->dev = dev; 1163 dev_set_drvdata(dev, priv); 1164 1165 for (i = 0; i < info->num_core_clks; i++) 1166 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 1167 1168 for (i = 0; i < info->num_mod_clks; i++) 1169 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1170 1171 error = devm_add_action_or_reset(dev, 1172 cpg_mssr_del_clk_provider, 1173 np); 1174 if (error) 1175 goto reserve_exit; 1176 1177 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1178 info->num_core_pm_clks); 1179 if (error) 1180 goto reserve_exit; 1181 1182 /* Reset Controller not supported for Standby Control SoCs */ 1183 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 1184 goto reserve_exit; 1185 1186 error = cpg_mssr_reset_controller_register(priv); 1187 1188 reserve_exit: 1189 cpg_mssr_reserved_exit(priv); 1190 1191 return error; 1192 } 1193 1194 static struct platform_driver cpg_mssr_driver = { 1195 .driver = { 1196 .name = "renesas-cpg-mssr", 1197 .of_match_table = cpg_mssr_match, 1198 .pm = DEV_PM_OPS, 1199 }, 1200 }; 1201 1202 static int __init cpg_mssr_init(void) 1203 { 1204 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1205 } 1206 1207 subsys_initcall(cpg_mssr_init); 1208 1209 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1210 unsigned int num_mod_clks, 1211 const unsigned int *clks, unsigned int n) 1212 { 1213 unsigned int i, j; 1214 1215 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1216 if (mod_clks[i].id == clks[j]) { 1217 mod_clks[i].name = NULL; 1218 j++; 1219 } 1220 } 1221 1222 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1223