1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car Gen4 Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__ 10 #define __CLK_RENESAS_RCAR_GEN4_CPG_H__ 11 12 enum rcar_gen4_clk_types { 13 CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, 14 CLK_TYPE_GEN4_PLL1, 15 CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ 16 CLK_TYPE_GEN4_PLL5, 17 CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */ 18 CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */ 19 CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */ 20 CLK_TYPE_GEN4_PLL_V9_24, /* Variable fractional 9.24 PLL */ 21 CLK_TYPE_GEN4_SDSRC, 22 CLK_TYPE_GEN4_SDH, 23 CLK_TYPE_GEN4_SD, 24 CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ 25 CLK_TYPE_GEN4_Z, 26 CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ 27 CLK_TYPE_GEN4_RPCSRC, 28 CLK_TYPE_GEN4_RPC, 29 CLK_TYPE_GEN4_RPCD2, 30 31 /* SoC specific definitions start here */ 32 CLK_TYPE_GEN4_SOC_BASE, 33 }; 34 35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ 36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset) 37 38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ 39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) 40 41 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 42 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ 43 (_parent0) << 16 | (_parent1), \ 44 .div = (_div0) << 16 | (_div1), .offset = _md) 45 46 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ 47 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) 48 49 #define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \ 50 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx) 51 52 #define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \ 53 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx) 54 55 #define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \ 56 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F9_24, _parent, .offset = _idx) 57 58 #define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \ 59 DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx) 60 61 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ 62 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 63 64 struct rcar_gen4_cpg_pll_config { 65 u8 extal_div; 66 u8 pll1_mult; 67 u8 pll1_div; 68 u8 pll5_mult; 69 u8 pll5_div; 70 u8 osc_prediv; 71 }; 72 73 #define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ 74 #define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ 75 #define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ 76 #define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ 77 #define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ 78 79 struct clk *rcar_gen4_cpg_clk_register(struct device *dev, 80 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 81 struct clk **clks, void __iomem *base, 82 struct raw_notifier_head *notifiers); 83 int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, 84 unsigned int clk_extalr, u32 mode); 85 86 #endif 87