1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * Copyright (C) 2018 Renesas Electronics Corp. 7 * 8 */ 9 10 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 13 enum rcar_gen3_clk_types { 14 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 15 CLK_TYPE_GEN3_PLL0, 16 CLK_TYPE_GEN3_PLL1, 17 CLK_TYPE_GEN3_PLL2, 18 CLK_TYPE_GEN3_PLL3, 19 CLK_TYPE_GEN3_PLL4, 20 CLK_TYPE_GEN3_SDH, 21 CLK_TYPE_GEN3_SD, 22 CLK_TYPE_GEN3_R, 23 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 24 CLK_TYPE_GEN3_Z, 25 CLK_TYPE_GEN3_ZG, 26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 28 CLK_TYPE_GEN3_RPCSRC, 29 CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */ 30 CLK_TYPE_GEN3_RPC, 31 CLK_TYPE_GEN3_RPCD2, 32 33 /* SoC specific definitions start here */ 34 CLK_TYPE_GEN3_SOC_BASE, 35 }; 36 37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ 38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) 39 40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 42 43 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 44 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 45 (_parent0) << 16 | (_parent1), \ 46 .div = (_div0) << 16 | (_div1), .offset = _md) 47 48 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 49 _div_clean) \ 50 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 51 _parent_clean, _div_clean) 52 53 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 54 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 55 56 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 57 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 58 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 59 60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ 61 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 62 63 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ 64 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ 65 (_parent0) << 16 | (_parent1), .div = 8) 66 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ 67 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ 68 (_parent0) << 16 | (_parent1), .div = 5) 69 70 struct rcar_gen3_cpg_pll_config { 71 u8 extal_div; 72 u8 pll1_mult; 73 u8 pll1_div; 74 u8 pll3_mult; 75 u8 pll3_div; 76 u8 osc_prediv; 77 }; 78 79 #define CPG_RPCCKCR 0x238 80 #define CPG_RCKCR 0x240 81 82 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 83 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 84 struct clk **clks, void __iomem *base, 85 struct raw_notifier_head *notifiers); 86 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 87 unsigned int clk_extalr, u32 mode); 88 89 #endif 90