1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2H(P) CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 33 /* Internal Core Clocks */ 34 CLK_PLLCM33_DIV16, 35 CLK_PLLCLN_DIV2, 36 CLK_PLLCLN_DIV8, 37 CLK_PLLCLN_DIV16, 38 CLK_PLLDTY_ACPU, 39 CLK_PLLDTY_ACPU_DIV2, 40 CLK_PLLDTY_ACPU_DIV4, 41 CLK_PLLDTY_DIV16, 42 CLK_PLLVDO_CRU0, 43 CLK_PLLVDO_CRU1, 44 CLK_PLLVDO_CRU2, 45 CLK_PLLVDO_CRU3, 46 47 /* Module Clocks */ 48 MOD_CLK_BASE, 49 }; 50 51 static const struct clk_div_table dtable_1_8[] = { 52 {0, 1}, 53 {1, 2}, 54 {2, 4}, 55 {3, 8}, 56 {0, 0}, 57 }; 58 59 static const struct clk_div_table dtable_2_4[] = { 60 {0, 2}, 61 {1, 4}, 62 {0, 0}, 63 }; 64 65 static const struct clk_div_table dtable_2_64[] = { 66 {0, 2}, 67 {1, 4}, 68 {2, 8}, 69 {3, 16}, 70 {4, 64}, 71 {0, 0}, 72 }; 73 74 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 75 /* External Clock Inputs */ 76 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 77 DEF_INPUT("rtxin", CLK_RTXIN), 78 DEF_INPUT("qextal", CLK_QEXTAL), 79 80 /* PLL Clocks */ 81 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 82 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 83 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 84 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), 85 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 86 87 /* Internal Core Clocks */ 88 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 89 90 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 91 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 92 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 93 94 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 95 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 96 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 97 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 98 99 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 100 DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), 101 DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), 102 DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), 103 104 /* Core Clocks */ 105 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 106 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, 107 CDDIV1_DIVCTL0, dtable_1_8), 108 DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55, 109 CDDIV1_DIVCTL1, dtable_1_8), 110 DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55, 111 CDDIV1_DIVCTL2, dtable_1_8), 112 DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, 113 CDDIV1_DIVCTL3, dtable_1_8), 114 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 115 }; 116 117 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 119 BUS_MSTOP_NONE), 120 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 121 BUS_MSTOP(3, BIT(5))), 122 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 123 BUS_MSTOP(5, BIT(10))), 124 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 125 BUS_MSTOP(5, BIT(11))), 126 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 127 BUS_MSTOP(2, BIT(13))), 128 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 129 BUS_MSTOP(2, BIT(14))), 130 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 131 BUS_MSTOP(11, BIT(13))), 132 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 133 BUS_MSTOP(11, BIT(14))), 134 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 135 BUS_MSTOP(11, BIT(15))), 136 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 137 BUS_MSTOP(12, BIT(0))), 138 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 139 BUS_MSTOP(3, BIT(10))), 140 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 141 BUS_MSTOP(3, BIT(10))), 142 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 143 BUS_MSTOP(1, BIT(0))), 144 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 145 BUS_MSTOP(1, BIT(0))), 146 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 147 BUS_MSTOP(5, BIT(12))), 148 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 149 BUS_MSTOP(5, BIT(12))), 150 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 151 BUS_MSTOP(5, BIT(13))), 152 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 153 BUS_MSTOP(5, BIT(13))), 154 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 155 BUS_MSTOP(3, BIT(14))), 156 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 157 BUS_MSTOP(3, BIT(13))), 158 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 159 BUS_MSTOP(1, BIT(1))), 160 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 161 BUS_MSTOP(1, BIT(2))), 162 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 163 BUS_MSTOP(1, BIT(3))), 164 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 165 BUS_MSTOP(1, BIT(4))), 166 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 167 BUS_MSTOP(1, BIT(5))), 168 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 169 BUS_MSTOP(1, BIT(6))), 170 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 171 BUS_MSTOP(1, BIT(7))), 172 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 173 BUS_MSTOP(1, BIT(8))), 174 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 175 BUS_MSTOP(8, BIT(2))), 176 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 177 BUS_MSTOP(8, BIT(2))), 178 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 179 BUS_MSTOP(8, BIT(2))), 180 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 181 BUS_MSTOP(8, BIT(2))), 182 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 183 BUS_MSTOP(8, BIT(3))), 184 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 185 BUS_MSTOP(8, BIT(3))), 186 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 187 BUS_MSTOP(8, BIT(3))), 188 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 189 BUS_MSTOP(8, BIT(3))), 190 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 191 BUS_MSTOP(8, BIT(4))), 192 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 193 BUS_MSTOP(8, BIT(4))), 194 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 195 BUS_MSTOP(8, BIT(4))), 196 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 197 BUS_MSTOP(8, BIT(4))), 198 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 199 BUS_MSTOP(9, BIT(4))), 200 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 201 BUS_MSTOP(9, BIT(4))), 202 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 203 BUS_MSTOP(9, BIT(4))), 204 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 205 BUS_MSTOP(9, BIT(5))), 206 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 207 BUS_MSTOP(9, BIT(5))), 208 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 209 BUS_MSTOP(9, BIT(5))), 210 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, 211 BUS_MSTOP(9, BIT(6))), 212 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, 213 BUS_MSTOP(9, BIT(6))), 214 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, 215 BUS_MSTOP(9, BIT(6))), 216 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, 217 BUS_MSTOP(9, BIT(7))), 218 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, 219 BUS_MSTOP(9, BIT(7))), 220 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, 221 BUS_MSTOP(9, BIT(7))), 222 }; 223 224 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 225 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 226 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 227 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 228 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 229 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 230 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 231 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 232 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 233 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 234 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 235 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 236 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 237 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 238 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 239 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 240 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 241 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 242 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 243 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 244 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 245 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 246 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 247 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 248 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 249 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 250 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 251 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 252 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 253 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 254 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 255 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 256 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 257 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ 258 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ 259 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ 260 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ 261 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ 262 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ 263 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ 264 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ 265 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ 266 }; 267 268 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 269 /* Core Clocks */ 270 .core_clks = r9a09g057_core_clks, 271 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), 272 .last_dt_core_clk = LAST_DT_CORE_CLK, 273 .num_total_core_clks = MOD_CLK_BASE, 274 275 /* Module Clocks */ 276 .mod_clks = r9a09g057_mod_clks, 277 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), 278 .num_hw_mod_clks = 25 * 16, 279 280 /* Resets */ 281 .resets = r9a09g057_resets, 282 .num_resets = ARRAY_SIZE(r9a09g057_resets), 283 284 .num_mstop_bits = 192, 285 }; 286