1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 * 7 * Based on r9a07g044-cpg.c 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 15 #include <dt-bindings/clock/r9a09g011-cpg.h> 16 17 #include "rzg2l-cpg.h" 18 19 #define RZV2M_SAMPLL4_CLK1 0x104 20 #define RZV2M_SAMPLL4_CLK2 0x108 21 22 #define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12) 23 24 #define DIV_A DDIV_PACK(0x200, 0, 3) 25 #define DIV_B DDIV_PACK(0x204, 0, 2) 26 #define DIV_D DDIV_PACK(0x204, 4, 2) 27 #define DIV_E DDIV_PACK(0x204, 8, 1) 28 #define DIV_W DDIV_PACK(0x328, 0, 3) 29 30 #define SEL_B SEL_PLL_PACK(0x214, 0, 1) 31 #define SEL_D SEL_PLL_PACK(0x214, 1, 1) 32 #define SEL_E SEL_PLL_PACK(0x214, 2, 1) 33 #define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) 34 #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) 35 36 enum clk_ids { 37 /* Core Clock Outputs exported to DT */ 38 LAST_DT_CORE_CLK = 0, 39 40 /* External Input Clocks */ 41 CLK_EXTAL, 42 43 /* Internal Core Clocks */ 44 CLK_MAIN, 45 CLK_MAIN_24, 46 CLK_MAIN_2, 47 CLK_PLL1, 48 CLK_PLL2, 49 CLK_PLL2_800, 50 CLK_PLL2_400, 51 CLK_PLL2_200, 52 CLK_PLL2_100, 53 CLK_PLL4, 54 CLK_DIV_A, 55 CLK_DIV_B, 56 CLK_DIV_D, 57 CLK_DIV_E, 58 CLK_DIV_W, 59 CLK_SEL_B, 60 CLK_SEL_B_D2, 61 CLK_SEL_D, 62 CLK_SEL_E, 63 CLK_SEL_SDI, 64 CLK_SEL_W0, 65 66 /* Module Clocks */ 67 MOD_CLK_BASE 68 }; 69 70 /* Divider tables */ 71 static const struct clk_div_table dtable_diva[] = { 72 {0, 1}, 73 {1, 2}, 74 {2, 3}, 75 {3, 4}, 76 {4, 6}, 77 {5, 12}, 78 {6, 24}, 79 {0, 0}, 80 }; 81 82 static const struct clk_div_table dtable_divb[] = { 83 {0, 1}, 84 {1, 2}, 85 {2, 4}, 86 {3, 8}, 87 {0, 0}, 88 }; 89 90 static const struct clk_div_table dtable_divd[] = { 91 {0, 1}, 92 {1, 2}, 93 {2, 4}, 94 {0, 0}, 95 }; 96 97 98 static const struct clk_div_table dtable_divw[] = { 99 {0, 6}, 100 {1, 7}, 101 {2, 8}, 102 {3, 9}, 103 {4, 10}, 104 {5, 11}, 105 {6, 12}, 106 {0, 0}, 107 }; 108 109 /* Mux clock tables */ 110 static const char * const sel_b[] = { ".main", ".divb" }; 111 static const char * const sel_d[] = { ".main", ".divd" }; 112 static const char * const sel_e[] = { ".main", ".dive" }; 113 static const char * const sel_w[] = { ".main", ".divw" }; 114 static const char * const sel_sdi[] = { ".main", ".pll2_200" }; 115 116 static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { 117 /* External Clock Inputs */ 118 DEF_INPUT("extal", CLK_EXTAL), 119 120 /* Internal Core Clocks */ 121 DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1), 122 DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2), 123 DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24), 124 DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1), 125 DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1), 126 DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 127 DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2), 128 DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4), 129 DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8), 130 DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF), 131 132 DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), 133 DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), 134 DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd), 135 DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), 136 DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), 137 138 DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), 139 DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), 140 DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), 141 DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), 142 DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), 143 144 DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), 145 }; 146 147 static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 148 DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), 149 DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), 150 DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), 151 DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), 152 DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), 153 DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), 154 DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), 155 DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), 156 DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), 157 DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), 158 DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), 159 DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), 160 DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), 161 DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), 162 DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), 163 DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), 164 DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), 165 DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4), 166 DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5), 167 DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6), 168 DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), 169 DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12), 170 DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0), 171 DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4), 172 DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5), 173 DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6), 174 DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7), 175 DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8), 176 DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9), 177 DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10), 178 DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11), 179 DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), 180 DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0), 181 DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4), 182 DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5), 183 DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6), 184 DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7), 185 DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8), 186 DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9), 187 DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10), 188 DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11), 189 DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), 190 DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), 191 DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), 192 DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), 193 DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), 194 DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), 195 DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), 196 DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), 197 DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), 198 DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), 199 DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), 200 DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), 201 DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), 202 }; 203 204 static const struct rzg2l_reset r9a09g011_resets[] = { 205 DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), 206 DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), 207 DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), 208 DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), 209 DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7), 210 DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8), 211 DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9), 212 DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10), 213 DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), 214 DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), 215 DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1), 216 DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2), 217 DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23), 218 DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), 219 DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9), 220 DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), 221 }; 222 223 static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { 224 MOD_CLK_BASE + R9A09G011_CA53_CLK, 225 MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK, 226 MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK, 227 MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, 228 MOD_CLK_BASE + R9A09G011_GIC_CLK, 229 MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, 230 MOD_CLK_BASE + R9A09G011_URT_PCLK, 231 }; 232 233 const struct rzg2l_cpg_info r9a09g011_cpg_info = { 234 /* Core Clocks */ 235 .core_clks = r9a09g011_core_clks, 236 .num_core_clks = ARRAY_SIZE(r9a09g011_core_clks), 237 .last_dt_core_clk = LAST_DT_CORE_CLK, 238 .num_total_core_clks = MOD_CLK_BASE, 239 240 /* Critical Module Clocks */ 241 .crit_mod_clks = r9a09g011_crit_mod_clks, 242 .num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks), 243 244 /* Module Clocks */ 245 .mod_clks = r9a09g011_mod_clks, 246 .num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks), 247 .num_hw_mod_clks = R9A09G011_CA53_CLK + 1, 248 249 /* Resets */ 250 .resets = r9a09g011_resets, 251 .num_resets = ARRAY_SIZE(r9a09g011_resets), 252 253 .has_clk_mon_regs = false, 254 }; 255