1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G3S CPG driver 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/pm_domain.h> 13 14 #include <dt-bindings/clock/r9a08g045-cpg.h> 15 16 #include "rzg2l-cpg.h" 17 18 /* RZ/G3S Specific registers. */ 19 #define G3S_CPG_PL2_DDIV (0x204) 20 #define G3S_CPG_SDHI_DDIV (0x218) 21 #define G3S_CPG_PLL_DSEL (0x240) 22 #define G3S_CPG_SDHI_DSEL (0x244) 23 #define G3S_CLKDIVSTATUS (0x280) 24 #define G3S_CLKSELSTATUS (0x284) 25 26 /* RZ/G3S Specific division configuration. */ 27 #define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) 28 #define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) 29 #define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1) 30 #define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1) 31 32 /* RZ/G3S Clock status configuration. */ 33 #define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) 34 #define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1) 35 #define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1) 36 #define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) 37 #define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) 38 #define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) 39 #define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1) 40 #define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1) 41 42 #define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) 43 #define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) 44 #define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1) 45 #define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1) 46 47 /* RZ/G3S Specific clocks select. */ 48 #define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) 49 #define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) 50 #define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2) 51 #define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2) 52 53 /* PLL 1/4/6 configuration registers macro. */ 54 #define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) 55 56 #define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \ 57 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \ 58 .parent_names = (_parent_names), \ 59 .num_parents = ARRAY_SIZE((_parent_names)), \ 60 .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \ 61 .flag = (_clk_flags)) 62 63 enum clk_ids { 64 /* Core Clock Outputs exported to DT */ 65 LAST_DT_CORE_CLK = R9A08G045_SWD, 66 67 /* External Input Clocks */ 68 CLK_EXTAL, 69 70 /* Internal Core Clocks */ 71 CLK_OSC_DIV1000, 72 CLK_PLL1, 73 CLK_PLL2, 74 CLK_PLL2_DIV2, 75 CLK_PLL2_DIV2_8, 76 CLK_PLL2_DIV6, 77 CLK_PLL3, 78 CLK_PLL3_DIV2, 79 CLK_PLL3_DIV2_4, 80 CLK_PLL3_DIV2_8, 81 CLK_PLL3_DIV6, 82 CLK_PLL4, 83 CLK_PLL6, 84 CLK_PLL6_DIV2, 85 CLK_SEL_SDHI0, 86 CLK_SEL_SDHI1, 87 CLK_SEL_SDHI2, 88 CLK_SEL_PLL4, 89 CLK_P1_DIV2, 90 CLK_P3_DIV2, 91 CLK_SD0_DIV4, 92 CLK_SD1_DIV4, 93 CLK_SD2_DIV4, 94 95 /* Module Clocks */ 96 MOD_CLK_BASE, 97 }; 98 99 /* Divider tables */ 100 static const struct clk_div_table dtable_1_2[] = { 101 { 0, 1 }, 102 { 1, 2 }, 103 { 0, 0 }, 104 }; 105 106 static const struct clk_div_table dtable_1_8[] = { 107 { 0, 1 }, 108 { 1, 2 }, 109 { 2, 4 }, 110 { 3, 8 }, 111 { 0, 0 }, 112 }; 113 114 static const struct clk_div_table dtable_1_32[] = { 115 { 0, 1 }, 116 { 1, 2 }, 117 { 2, 4 }, 118 { 3, 8 }, 119 { 4, 32 }, 120 { 0, 0 }, 121 }; 122 123 /* Mux clock names tables. */ 124 static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" }; 125 static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" }; 126 127 /* Mux clock indices tables. */ 128 static const u32 mtable_sd[] = { 0, 2, 3 }; 129 static const u32 mtable_pll4[] = { 0, 1 }; 130 131 static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { 132 /* External Clock Inputs */ 133 DEF_INPUT("extal", CLK_EXTAL), 134 135 /* Internal Core Clocks */ 136 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 137 DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)), 138 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 139 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 140 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3), 141 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 142 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 143 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 144 DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6), 145 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 146 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 147 DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8), 148 DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6), 149 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), 150 DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, 151 mtable_sd, 0, NULL), 152 DEF_SD_MUX(".sel_sd1", CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi, 153 mtable_sd, 0, NULL), 154 DEF_SD_MUX(".sel_sd2", CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi, 155 mtable_sd, 0, NULL), 156 DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, 157 mtable_pll4, CLK_SET_PARENT_GATE, NULL), 158 159 /* Core output clk */ 160 DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8, 161 0, 0, 0, NULL), 162 DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS, 163 dtable_1_32, 0, 0, 0, NULL), 164 DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, 165 dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, 166 rzg3s_cpg_div_clk_notifier), 167 DEF_G3S_DIV("SD1", R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS, 168 dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, 169 rzg3s_cpg_div_clk_notifier), 170 DEF_G3S_DIV("SD2", R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS, 171 dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, 172 rzg3s_cpg_div_clk_notifier), 173 DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), 174 DEF_FIXED(".sd1_div4", CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4), 175 DEF_FIXED(".sd2_div4", CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4), 176 DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 177 DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, 178 dtable_1_32, 0, 0, 0, NULL), 179 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2), 180 DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS, 181 dtable_1_32, 0, 0, 0, NULL), 182 DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, 183 dtable_1_32, 0, 0, 0, NULL), 184 DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), 185 DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), 186 DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), 187 DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), 188 DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), 189 DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2), 190 DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8), 191 }; 192 193 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 194 DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), 195 DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), 196 DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), 197 DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), 198 DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1), 199 DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0), 200 DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1), 201 DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), 202 DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), 203 DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), 204 DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), 205 DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), 206 DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), 207 DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6), 208 DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7), 209 DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8), 210 DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), 211 DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), 212 DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), 213 DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0), 214 DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1), 215 DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2), 216 DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3), 217 DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4), 218 DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5), 219 DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6), 220 DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7), 221 DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0), 222 DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1), 223 DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2), 224 DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3), 225 DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), 226 DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), 227 DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), 228 DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), 229 DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), 230 DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), 231 DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0), 232 DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1), 233 DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2), 234 DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3), 235 DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), 236 DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1), 237 DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2), 238 DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3), 239 DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4), 240 DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5), 241 DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), 242 DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), 243 DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), 244 DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), 245 }; 246 247 static const struct rzg2l_reset r9a08g045_resets[] = { 248 DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), 249 DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), 250 DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), 251 DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0), 252 DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1), 253 DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0), 254 DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), 255 DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), 256 DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), 257 DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0), 258 DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1), 259 DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2), 260 DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3), 261 DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0), 262 DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1), 263 DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2), 264 DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3), 265 DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), 266 DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), 267 DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0), 268 DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1), 269 DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2), 270 DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3), 271 DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), 272 DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1), 273 DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2), 274 DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3), 275 DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4), 276 DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5), 277 DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), 278 DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), 279 DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), 280 DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), 281 DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), 282 DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), 283 }; 284 285 static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 286 MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, 287 MOD_CLK_BASE + R9A08G045_IA55_PCLK, 288 MOD_CLK_BASE + R9A08G045_IA55_CLK, 289 MOD_CLK_BASE + R9A08G045_DMAC_ACLK, 290 MOD_CLK_BASE + R9A08G045_VBAT_BCLK, 291 }; 292 293 static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 294 /* Keep always-on domain on the first position for proper domains registration. */ 295 DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, 296 DEF_REG_CONF(0, 0), 297 GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE), 298 DEF_PD("gic", R9A08G045_PD_GIC, 299 DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), 300 GENPD_FLAG_ALWAYS_ON), 301 DEF_PD("ia55", R9A08G045_PD_IA55, 302 DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)), 303 GENPD_FLAG_ALWAYS_ON), 304 DEF_PD("dmac", R9A08G045_PD_DMAC, 305 DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), 306 GENPD_FLAG_ALWAYS_ON), 307 DEF_PD("wdt0", R9A08G045_PD_WDT0, 308 DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 309 GENPD_FLAG_IRQ_SAFE), 310 DEF_PD("sdhi0", R9A08G045_PD_SDHI0, 311 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0), 312 DEF_PD("sdhi1", R9A08G045_PD_SDHI1, 313 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0), 314 DEF_PD("sdhi2", R9A08G045_PD_SDHI2, 315 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0), 316 DEF_PD("ssi0", R9A08G045_PD_SSI0, 317 DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0), 318 DEF_PD("ssi1", R9A08G045_PD_SSI1, 319 DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0), 320 DEF_PD("ssi2", R9A08G045_PD_SSI2, 321 DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0), 322 DEF_PD("ssi3", R9A08G045_PD_SSI3, 323 DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0), 324 DEF_PD("usb0", R9A08G045_PD_USB0, 325 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0), 326 DEF_PD("usb1", R9A08G045_PD_USB1, 327 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0), 328 DEF_PD("usb-phy", R9A08G045_PD_USB_PHY, 329 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0), 330 DEF_PD("eth0", R9A08G045_PD_ETHER0, 331 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0), 332 DEF_PD("eth1", R9A08G045_PD_ETHER1, 333 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0), 334 DEF_PD("i2c0", R9A08G045_PD_I2C0, 335 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0), 336 DEF_PD("i2c1", R9A08G045_PD_I2C1, 337 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0), 338 DEF_PD("i2c2", R9A08G045_PD_I2C2, 339 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0), 340 DEF_PD("i2c3", R9A08G045_PD_I2C3, 341 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0), 342 DEF_PD("scif0", R9A08G045_PD_SCIF0, 343 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0), 344 DEF_PD("scif1", R9A08G045_PD_SCIF1, 345 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0), 346 DEF_PD("scif2", R9A08G045_PD_SCIF2, 347 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0), 348 DEF_PD("scif3", R9A08G045_PD_SCIF3, 349 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0), 350 DEF_PD("scif4", R9A08G045_PD_SCIF4, 351 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0), 352 DEF_PD("scif5", R9A08G045_PD_SCIF5, 353 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), 354 DEF_PD("adc", R9A08G045_PD_ADC, 355 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), 356 DEF_PD("vbat", R9A08G045_PD_VBAT, 357 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), 358 GENPD_FLAG_ALWAYS_ON), 359 DEF_PD("rtc", R9A08G045_PD_RTC, 360 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), 361 }; 362 363 const struct rzg2l_cpg_info r9a08g045_cpg_info = { 364 /* Core Clocks */ 365 .core_clks = r9a08g045_core_clks, 366 .num_core_clks = ARRAY_SIZE(r9a08g045_core_clks), 367 .last_dt_core_clk = LAST_DT_CORE_CLK, 368 .num_total_core_clks = MOD_CLK_BASE, 369 370 /* Critical Module Clocks */ 371 .crit_mod_clks = r9a08g045_crit_mod_clks, 372 .num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks), 373 374 /* Module Clocks */ 375 .mod_clks = r9a08g045_mod_clks, 376 .num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks), 377 .num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1, 378 379 /* Resets */ 380 .resets = r9a08g045_resets, 381 .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ 382 383 /* Power domains */ 384 .pm_domains = r9a08g045_pm_domains, 385 .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains), 386 387 .has_clk_mon_regs = true, 388 }; 389