1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2UL CPG driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/r9a07g043-cpg.h> 14 15 #include "rzg2l-cpg.h" 16 17 /* Specific registers. */ 18 #define CPG_PL2SDHI_DSEL (0x218) 19 20 /* Clock select configuration. */ 21 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) 22 #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) 23 24 /* Clock status configuration. */ 25 #define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) 26 #define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) 27 28 enum clk_ids { 29 /* Core Clock Outputs exported to DT */ 30 LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, 31 32 /* External Input Clocks */ 33 CLK_EXTAL, 34 35 /* Internal Core Clocks */ 36 CLK_OSC_DIV1000, 37 CLK_PLL1, 38 CLK_PLL2, 39 CLK_PLL2_DIV2, 40 CLK_PLL2_DIV2_8, 41 CLK_PLL2_DIV2_10, 42 CLK_PLL3, 43 CLK_PLL3_400, 44 CLK_PLL3_533, 45 CLK_PLL3_DIV2, 46 CLK_PLL3_DIV2_4, 47 CLK_PLL3_DIV2_4_2, 48 CLK_SEL_PLL3_3, 49 CLK_DIV_PLL3_C, 50 #ifdef CONFIG_ARM64 51 CLK_PLL5, 52 CLK_PLL5_500, 53 CLK_PLL5_250, 54 #endif 55 CLK_PLL6, 56 CLK_PLL6_250, 57 CLK_P1_DIV2, 58 CLK_PLL2_800, 59 CLK_PLL2_SDHI_533, 60 CLK_PLL2_SDHI_400, 61 CLK_PLL2_SDHI_266, 62 CLK_SD0_DIV4, 63 CLK_SD1_DIV4, 64 65 /* Module Clocks */ 66 MOD_CLK_BASE, 67 }; 68 69 /* Divider tables */ 70 static const struct clk_div_table dtable_1_8[] = { 71 {0, 1}, 72 {1, 2}, 73 {2, 4}, 74 {3, 8}, 75 {0, 0}, 76 }; 77 78 static const struct clk_div_table dtable_1_32[] = { 79 {0, 1}, 80 {1, 2}, 81 {2, 4}, 82 {3, 8}, 83 {4, 32}, 84 {0, 0}, 85 }; 86 87 /* Mux clock tables */ 88 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 89 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 90 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 91 92 static const u32 mtable_sdhi[] = { 1, 2, 3 }; 93 94 static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 95 /* External Clock Inputs */ 96 DEF_INPUT("extal", CLK_EXTAL), 97 98 /* Internal Core Clocks */ 99 DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), 100 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 101 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 102 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 103 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 104 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 105 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 106 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 107 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 108 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 109 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), 110 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 111 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 112 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 113 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 114 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 115 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 116 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), 117 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), 118 #ifdef CONFIG_ARM64 119 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 120 DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), 121 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), 122 #endif 123 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 124 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 125 126 /* Core output clk */ 127 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), 128 DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), 129 DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), 130 DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), 131 DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), 132 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 133 DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), 134 DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 135 DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 136 DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), 137 DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 138 DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 139 DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, 140 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 141 DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, 142 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 143 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 144 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), 145 }; 146 147 static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 148 #ifdef CONFIG_ARM64 149 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 150 0x514, 0), 151 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 152 0x518, 0), 153 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 154 0x518, 1), 155 #endif 156 #ifdef CONFIG_RISCV 157 DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, 158 0x518, 0), 159 DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, 160 0x518, 1), 161 #endif 162 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 163 0x52c, 0), 164 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 165 0x52c, 1), 166 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 167 0x534, 0), 168 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 169 0x534, 1), 170 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 171 0x534, 2), 172 DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, 173 0x538, 0), 174 DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 175 0x548, 0), 176 DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 177 0x548, 1), 178 DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 179 0x550, 0), 180 DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, 181 0x550, 1), 182 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 183 0x554, 0), 184 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 185 0x554, 1), 186 DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 187 0x554, 2), 188 DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 189 0x554, 3), 190 DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 191 0x554, 4), 192 DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 193 0x554, 5), 194 DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 195 0x554, 6), 196 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 197 0x554, 7), 198 DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 199 0x570, 0), 200 DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 201 0x570, 1), 202 DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 203 0x570, 2), 204 DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 205 0x570, 3), 206 DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 207 0x570, 4), 208 DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 209 0x570, 5), 210 DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 211 0x570, 6), 212 DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 213 0x570, 7), 214 DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 215 0x578, 0), 216 DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 217 0x578, 1), 218 DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 219 0x578, 2), 220 DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 221 0x578, 3), 222 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 223 0x57c, 0), 224 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 225 0x57c, 0), 226 DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 227 0x57c, 1), 228 DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 229 0x57c, 1), 230 DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 231 0x580, 0), 232 DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 233 0x580, 1), 234 DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 235 0x580, 2), 236 DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 237 0x580, 3), 238 DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 239 0x584, 0), 240 DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 241 0x584, 1), 242 DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 243 0x584, 2), 244 DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 245 0x584, 3), 246 DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 247 0x584, 4), 248 DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 249 0x588, 0), 250 DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 251 0x588, 1), 252 DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, 253 0x590, 0), 254 DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, 255 0x590, 1), 256 DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, 257 0x590, 2), 258 DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 259 0x594, 0), 260 DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 261 0x598, 0), 262 DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, 263 0x5a8, 0), 264 DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, 265 0x5a8, 1), 266 DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 267 0x5ac, 0), 268 }; 269 270 static struct rzg2l_reset r9a07g043_resets[] = { 271 #ifdef CONFIG_ARM64 272 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), 273 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), 274 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 275 #endif 276 #ifdef CONFIG_RISCV 277 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), 278 #endif 279 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 280 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 281 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), 282 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), 283 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), 284 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), 285 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), 286 DEF_RST(R9A07G043_SPI_RST, 0x850, 0), 287 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 288 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 289 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), 290 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 291 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), 292 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), 293 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), 294 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), 295 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), 296 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), 297 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 298 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 299 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), 300 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), 301 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), 302 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), 303 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), 304 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), 305 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), 306 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), 307 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), 308 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), 309 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), 310 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), 311 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), 312 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), 313 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), 314 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), 315 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), 316 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), 317 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), 318 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), 319 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), 320 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), 321 }; 322 323 static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 324 #ifdef CONFIG_ARM64 325 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, 326 MOD_CLK_BASE + R9A07G043_IA55_CLK, 327 #endif 328 #ifdef CONFIG_RISCV 329 MOD_CLK_BASE + R9A07G043_IAX45_CLK, 330 #endif 331 MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 332 }; 333 334 const struct rzg2l_cpg_info r9a07g043_cpg_info = { 335 /* Core Clocks */ 336 .core_clks = r9a07g043_core_clks, 337 .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), 338 .last_dt_core_clk = LAST_DT_CORE_CLK, 339 .num_total_core_clks = MOD_CLK_BASE, 340 341 /* Critical Module Clocks */ 342 .crit_mod_clks = r9a07g043_crit_mod_clks, 343 .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), 344 345 /* Module Clocks */ 346 .mod_clks = r9a07g043_mod_clks, 347 .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 348 #ifdef CONFIG_ARM64 349 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 350 #endif 351 #ifdef CONFIG_RISCV 352 .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, 353 #endif 354 355 /* Resets */ 356 .resets = r9a07g043_resets, 357 #ifdef CONFIG_ARM64 358 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ 359 #endif 360 #ifdef CONFIG_RISCV 361 .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ 362 #endif 363 364 .has_clk_mon_regs = true, 365 }; 366