xref: /linux/drivers/clk/renesas/r9a06g032-clocks.c (revision f474808acb3c4b30552d9c59b181244e0300d218)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R9A09G032 clock driver
4  *
5  * Copyright (C) 2018 Renesas Electronics Europe Limited
6  *
7  * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/math64.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_clock.h>
21 #include <linux/pm_domain.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
25 
26 struct r9a06g032_gate {
27 	u16 gate, reset, ready, midle,
28 		scon, mirack, mistat;
29 };
30 
31 /* This is used to describe a clock for instantiation */
32 struct r9a06g032_clkdesc {
33 	const char *name;
34 	uint32_t managed: 1;
35 	uint32_t type: 3;
36 	uint32_t index: 8;
37 	uint32_t source : 8; /* source index + 1 (0 == none) */
38 	/* these are used to populate the bitsel struct */
39 	union {
40 		struct r9a06g032_gate gate;
41 		/* for dividers */
42 		struct {
43 			unsigned int div_min : 10, div_max : 10, reg: 10;
44 			u16 div_table[4];
45 		};
46 		/* For fixed-factor ones */
47 		struct {
48 			u16 div, mul;
49 		};
50 		unsigned int factor;
51 		unsigned int frequency;
52 		/* for dual gate */
53 		struct {
54 			uint16_t group : 1, index: 3;
55 			u16 sel, g1, r1, g2, r2;
56 		} dual;
57 	};
58 } __packed;
59 
60 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
61 	{ .gate = _clk, .reset = _rst, \
62 		.ready = _rdy, .midle = _midle, \
63 		.scon = _scon, .mirack = _mirack, .mistat = _mistat }
64 #define D_GATE(_idx, _n, _src, ...) \
65 	{ .type = K_GATE, .index = R9A06G032_##_idx, \
66 		.source = 1 + R9A06G032_##_src, .name = _n, \
67 		.gate = I_GATE(__VA_ARGS__) }
68 #define D_MODULE(_idx, _n, _src, ...) \
69 	{ .type = K_GATE, .index = R9A06G032_##_idx, \
70 		.source = 1 + R9A06G032_##_src, .name = _n, \
71 		.managed = 1, .gate = I_GATE(__VA_ARGS__) }
72 #define D_ROOT(_idx, _n, _mul, _div) \
73 	{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
74 		.div = _div, .mul = _mul }
75 #define D_FFC(_idx, _n, _src, _div) \
76 	{ .type = K_FFC, .index = R9A06G032_##_idx, \
77 		.source = 1 + R9A06G032_##_src, .name = _n, \
78 		.div = _div, .mul = 1}
79 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
80 	{ .type = K_DIV, .index = R9A06G032_##_idx, \
81 		.source = 1 + R9A06G032_##_src, .name = _n, \
82 		.reg = _reg, .div_min = _min, .div_max = _max, \
83 		.div_table = { __VA_ARGS__ } }
84 #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
85 	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
86 		.source = 1 + R9A06G032_##_src, .name = _n, \
87 		.dual = { .group = _g, .index = _gi, \
88 			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
89 
90 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
91 
92 /* Internal clock IDs */
93 #define R9A06G032_CLKOUT		0
94 #define R9A06G032_CLKOUT_D10		2
95 #define R9A06G032_CLKOUT_D16		3
96 #define R9A06G032_CLKOUT_D160		4
97 #define R9A06G032_CLKOUT_D1OR2		5
98 #define R9A06G032_CLKOUT_D20		6
99 #define R9A06G032_CLKOUT_D40		7
100 #define R9A06G032_CLKOUT_D5		8
101 #define R9A06G032_CLKOUT_D8		9
102 #define R9A06G032_DIV_ADC		10
103 #define R9A06G032_DIV_I2C		11
104 #define R9A06G032_DIV_NAND		12
105 #define R9A06G032_DIV_P1_PG		13
106 #define R9A06G032_DIV_P2_PG		14
107 #define R9A06G032_DIV_P3_PG		15
108 #define R9A06G032_DIV_P4_PG		16
109 #define R9A06G032_DIV_P5_PG		17
110 #define R9A06G032_DIV_P6_PG		18
111 #define R9A06G032_DIV_QSPI0		19
112 #define R9A06G032_DIV_QSPI1		20
113 #define R9A06G032_DIV_REF_SYNC		21
114 #define R9A06G032_DIV_SDIO0		22
115 #define R9A06G032_DIV_SDIO1		23
116 #define R9A06G032_DIV_SWITCH		24
117 #define R9A06G032_DIV_UART		25
118 #define R9A06G032_DIV_MOTOR		64
119 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4	78
120 #define R9A06G032_CLK_ECAT100_D4	79
121 #define R9A06G032_CLK_HSR100_D2		80
122 #define R9A06G032_CLK_REF_SYNC_D4	81
123 #define R9A06G032_CLK_REF_SYNC_D8	82
124 #define R9A06G032_CLK_SERCOS100_D2	83
125 #define R9A06G032_DIV_CA7		84
126 
127 #define R9A06G032_UART_GROUP_012	154
128 #define R9A06G032_UART_GROUP_34567	155
129 
130 #define R9A06G032_CLOCK_COUNT		(R9A06G032_UART_GROUP_34567 + 1)
131 
132 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
133 	D_ROOT(CLKOUT, "clkout", 25, 1),
134 	D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
135 	D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
136 	D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
137 	D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
138 	D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
139 	D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
140 	D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
141 	D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
142 	D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
143 	D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
144 	D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
145 	D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
146 	D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
147 	D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
148 	D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
149 	D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
150 	D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
151 	D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
152 	D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
153 	D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
154 	D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
155 	D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
156 	D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
157 	D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
158 	D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
159 	D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
160 	D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
161 	D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
162 	D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
163 	D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
164 	D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
165 	D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
166 	D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
167 	D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
168 	D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
169 	D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
170 	D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
171 	D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
172 	D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
173 	D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
174 	D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
175 	D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
176 	D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
177 	D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
178 	D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
179 	D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
180 	D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
181 	D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
182 	D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
183 	D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
184 	D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
185 	D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
186 	D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
187 	D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
188 	D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
189 	D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
190 	D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
191 	D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
192 	D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
193 	D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
194 	D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
195 	D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
196 	D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
197 	D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
198 	D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
199 	D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
200 	D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
201 	D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
202 	D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
203 	D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
204 	D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
205 	D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
206 	D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
207 	D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
208 	D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
209 	D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
210 	D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
211 	D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
212 	D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
213 	D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
214 	D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
215 	D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
216 	D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
217 	D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
218 	D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
219 	D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
220 	D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
221 	D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
222 	D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
223 	D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
224 	D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
225 	D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
226 	D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
227 	D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
228 	D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
229 	D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
230 	D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
231 	D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
232 	D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
233 	D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
234 	D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
235 	D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
236 	D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
237 	D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
238 	D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
239 	D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
240 	D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
241 	D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
242 	D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
243 	D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
244 	D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
245 	D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
246 	D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
247 	D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
248 	D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
249 	D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
250 	D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
251 	D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
252 	D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
253 	D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
254 	D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
255 	D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
256 	D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
257 	D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
258 	D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
259 	D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
260 	D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
261 	D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
262 	D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
263 	D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
264 	D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
265 	D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
266 	D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
267 	D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
268 	D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
269 	D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
270 	D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
271 	D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
272 	D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
273 	D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
274 	D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
275 	D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
276 	D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
277 	D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
278 	D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
279 	/*
280 	 * These are not hardware clocks, but are needed to handle the special
281 	 * case where we have a 'selector bit' that doesn't just change the
282 	 * parent for a clock, but also the gate it's suposed to use.
283 	 */
284 	{
285 		.index = R9A06G032_UART_GROUP_012,
286 		.name = "uart_group_012",
287 		.type = K_BITSEL,
288 		.source = 1 + R9A06G032_DIV_UART,
289 		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
290 		.dual.sel = ((0xec / 4) << 5) | 24,
291 		.dual.group = 0,
292 	},
293 	{
294 		.index = R9A06G032_UART_GROUP_34567,
295 		.name = "uart_group_34567",
296 		.type = K_BITSEL,
297 		.source = 1 + R9A06G032_DIV_P2_PG,
298 		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
299 		.dual.sel = ((0x34 / 4) << 5) | 30,
300 		.dual.group = 1,
301 	},
302 	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
303 	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
304 	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
305 	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
306 	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
307 	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
308 	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
309 	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
310 };
311 
312 struct r9a06g032_priv {
313 	struct clk_onecell_data data;
314 	spinlock_t lock; /* protects concurent access to gates */
315 	void __iomem *reg;
316 };
317 
318 /* register/bit pairs are encoded as an uint16_t */
319 static void
320 clk_rdesc_set(struct r9a06g032_priv *clocks,
321 	      u16 one, unsigned int on)
322 {
323 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
324 	u32 val = readl(reg);
325 
326 	val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
327 	writel(val, reg);
328 }
329 
330 static int
331 clk_rdesc_get(struct r9a06g032_priv *clocks,
332 	      uint16_t one)
333 {
334 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
335 	u32 val = readl(reg);
336 
337 	return !!(val & (1U << (one & 0x1f)));
338 }
339 
340 /*
341  * This implements the R9A09G032 clock gate 'driver'. We cannot use the system's
342  * clock gate framework as the gates on the R9A09G032 have a special enabling
343  * sequence, therefore we use this little proxy.
344  */
345 struct r9a06g032_clk_gate {
346 	struct clk_hw hw;
347 	struct r9a06g032_priv *clocks;
348 	u16 index;
349 
350 	struct r9a06g032_gate gate;
351 };
352 
353 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
354 
355 static int create_add_module_clock(struct of_phandle_args *clkspec,
356 				   struct device *dev)
357 {
358 	struct clk *clk;
359 	int error;
360 
361 	clk = of_clk_get_from_provider(clkspec);
362 	if (IS_ERR(clk))
363 		return PTR_ERR(clk);
364 
365 	error = pm_clk_create(dev);
366 	if (error) {
367 		clk_put(clk);
368 		return error;
369 	}
370 
371 	error = pm_clk_add_clk(dev, clk);
372 	if (error) {
373 		pm_clk_destroy(dev);
374 		clk_put(clk);
375 	}
376 
377 	return error;
378 }
379 
380 static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
381 				struct device *dev)
382 {
383 	struct device_node *np = dev->of_node;
384 	struct of_phandle_args clkspec;
385 	int i = 0;
386 	int error;
387 	int index;
388 
389 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
390 					   &clkspec)) {
391 		if (clkspec.np != pd->dev.of_node)
392 			continue;
393 
394 		index = clkspec.args[0];
395 		if (index < R9A06G032_CLOCK_COUNT &&
396 		    r9a06g032_clocks[index].managed) {
397 			error = create_add_module_clock(&clkspec, dev);
398 			of_node_put(clkspec.np);
399 			if (error)
400 				return error;
401 		}
402 		i++;
403 	}
404 
405 	return 0;
406 }
407 
408 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
409 {
410 	if (!pm_clk_no_clocks(dev))
411 		pm_clk_destroy(dev);
412 }
413 
414 static int r9a06g032_add_clk_domain(struct device *dev)
415 {
416 	struct device_node *np = dev->of_node;
417 	struct generic_pm_domain *pd;
418 
419 	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
420 	if (!pd)
421 		return -ENOMEM;
422 
423 	pd->name = np->name;
424 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
425 	pd->attach_dev = r9a06g032_attach_dev;
426 	pd->detach_dev = r9a06g032_detach_dev;
427 	pm_genpd_init(pd, &pm_domain_always_on_gov, false);
428 
429 	of_genpd_add_provider_simple(np, pd);
430 	return 0;
431 }
432 
433 static void
434 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
435 		       struct r9a06g032_gate *g, int on)
436 {
437 	unsigned long flags;
438 
439 	WARN_ON(!g->gate);
440 
441 	spin_lock_irqsave(&clocks->lock, flags);
442 	clk_rdesc_set(clocks, g->gate, on);
443 	/* De-assert reset */
444 	if (g->reset)
445 		clk_rdesc_set(clocks, g->reset, 1);
446 	spin_unlock_irqrestore(&clocks->lock, flags);
447 
448 	/* Hardware manual recommends 5us delay after enabling clock & reset */
449 	udelay(5);
450 
451 	/* If the peripheral is memory mapped (i.e. an AXI slave), there is an
452 	 * associated SLVRDY bit in the System Controller that needs to be set
453 	 * so that the FlexWAY bus fabric passes on the read/write requests.
454 	 */
455 	if (g->ready || g->midle) {
456 		spin_lock_irqsave(&clocks->lock, flags);
457 		if (g->ready)
458 			clk_rdesc_set(clocks, g->ready, on);
459 		/* Clear 'Master Idle Request' bit */
460 		if (g->midle)
461 			clk_rdesc_set(clocks, g->midle, !on);
462 		spin_unlock_irqrestore(&clocks->lock, flags);
463 	}
464 	/* Note: We don't wait for FlexWAY Socket Connection signal */
465 }
466 
467 static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
468 {
469 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
470 
471 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
472 	return 0;
473 }
474 
475 static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
476 {
477 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
478 
479 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
480 }
481 
482 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
483 {
484 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
485 
486 	/* if clock is in reset, the gate might be on, and still not 'be' on */
487 	if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
488 		return 0;
489 
490 	return clk_rdesc_get(g->clocks, g->gate.gate);
491 }
492 
493 static const struct clk_ops r9a06g032_clk_gate_ops = {
494 	.enable = r9a06g032_clk_gate_enable,
495 	.disable = r9a06g032_clk_gate_disable,
496 	.is_enabled = r9a06g032_clk_gate_is_enabled,
497 };
498 
499 static struct clk *
500 r9a06g032_register_gate(struct r9a06g032_priv *clocks,
501 			const char *parent_name,
502 			const struct r9a06g032_clkdesc *desc)
503 {
504 	struct clk *clk;
505 	struct r9a06g032_clk_gate *g;
506 	struct clk_init_data init;
507 
508 	g = kzalloc(sizeof(*g), GFP_KERNEL);
509 	if (!g)
510 		return NULL;
511 
512 	init.name = desc->name;
513 	init.ops = &r9a06g032_clk_gate_ops;
514 	init.flags = CLK_SET_RATE_PARENT;
515 	init.parent_names = parent_name ? &parent_name : NULL;
516 	init.num_parents = parent_name ? 1 : 0;
517 
518 	g->clocks = clocks;
519 	g->index = desc->index;
520 	g->gate = desc->gate;
521 	g->hw.init = &init;
522 
523 	/*
524 	 * important here, some clocks are already in use by the CM3, we
525 	 * have to assume they are not Linux's to play with and try to disable
526 	 * at the end of the boot!
527 	 */
528 	if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
529 		init.flags |= CLK_IS_CRITICAL;
530 		pr_debug("%s was enabled, making read-only\n", desc->name);
531 	}
532 
533 	clk = clk_register(NULL, &g->hw);
534 	if (IS_ERR(clk)) {
535 		kfree(g);
536 		return NULL;
537 	}
538 	return clk;
539 }
540 
541 struct r9a06g032_clk_div {
542 	struct clk_hw hw;
543 	struct r9a06g032_priv *clocks;
544 	u16 index;
545 	u16 reg;
546 	u16 min, max;
547 	u8 table_size;
548 	u16 table[8];	/* we know there are no more than 8 */
549 };
550 
551 #define to_r9a06g032_div(_hw) \
552 		container_of(_hw, struct r9a06g032_clk_div, hw)
553 
554 static unsigned long
555 r9a06g032_div_recalc_rate(struct clk_hw *hw,
556 			  unsigned long parent_rate)
557 {
558 	struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
559 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
560 	u32 div = readl(reg);
561 
562 	if (div < clk->min)
563 		div = clk->min;
564 	else if (div > clk->max)
565 		div = clk->max;
566 	return DIV_ROUND_UP(parent_rate, div);
567 }
568 
569 /*
570  * Attempts to find a value that is in range of min,max,
571  * and if a table of set dividers was specified for this
572  * register, try to find the fixed divider that is the closest
573  * to the target frequency
574  */
575 static long
576 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
577 			unsigned long rate, unsigned long prate)
578 {
579 	/* + 1 to cope with rates that have the remainder dropped */
580 	u32 div = DIV_ROUND_UP(prate, rate + 1);
581 	int i;
582 
583 	if (div <= clk->min)
584 		return clk->min;
585 	if (div >= clk->max)
586 		return clk->max;
587 
588 	for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
589 		if (div >= clk->table[i] && div <= clk->table[i + 1]) {
590 			unsigned long m = rate -
591 				DIV_ROUND_UP(prate, clk->table[i]);
592 			unsigned long p =
593 				DIV_ROUND_UP(prate, clk->table[i + 1]) -
594 				rate;
595 			/*
596 			 * select the divider that generates
597 			 * the value closest to the ideal frequency
598 			 */
599 			div = p >= m ? clk->table[i] : clk->table[i + 1];
600 			return div;
601 		}
602 	}
603 	return div;
604 }
605 
606 static long
607 r9a06g032_div_round_rate(struct clk_hw *hw,
608 			 unsigned long rate, unsigned long *prate)
609 {
610 	struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
611 	u32 div = DIV_ROUND_UP(*prate, rate);
612 
613 	pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
614 		 hw->clk, rate, *prate, div);
615 	pr_devel("   min %d (%ld) max %d (%ld)\n",
616 		 clk->min, DIV_ROUND_UP(*prate, clk->min),
617 		clk->max, DIV_ROUND_UP(*prate, clk->max));
618 
619 	div = r9a06g032_div_clamp_div(clk, rate, *prate);
620 	/*
621 	 * this is a hack. Currently the serial driver asks for a clock rate
622 	 * that is 16 times the baud rate -- and that is wildly outside the
623 	 * range of the UART divider, somehow there is no provision for that
624 	 * case of 'let the divider as is if outside range'.
625 	 * The serial driver *shouldn't* play with these clocks anyway, there's
626 	 * several uarts attached to this divider, and changing this impacts
627 	 * everyone.
628 	 */
629 	if (clk->index == R9A06G032_DIV_UART ||
630 	    clk->index == R9A06G032_DIV_P2_PG) {
631 		pr_devel("%s div uart hack!\n", __func__);
632 		return clk_get_rate(hw->clk);
633 	}
634 	pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
635 		 *prate, div, DIV_ROUND_UP(*prate, div));
636 	return DIV_ROUND_UP(*prate, div);
637 }
638 
639 static int
640 r9a06g032_div_set_rate(struct clk_hw *hw,
641 		       unsigned long rate, unsigned long parent_rate)
642 {
643 	struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
644 	/* + 1 to cope with rates that have the remainder dropped */
645 	u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
646 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
647 
648 	pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
649 		 rate, parent_rate, div);
650 
651 	/*
652 	 * Need to write the bit 31 with the divider value to
653 	 * latch it. Technically we should wait until it has been
654 	 * cleared too.
655 	 * TODO: Find whether this callback is sleepable, in case
656 	 * the hardware /does/ require some sort of spinloop here.
657 	 */
658 	writel(div | BIT(31), reg);
659 
660 	return 0;
661 }
662 
663 static const struct clk_ops r9a06g032_clk_div_ops = {
664 	.recalc_rate = r9a06g032_div_recalc_rate,
665 	.round_rate = r9a06g032_div_round_rate,
666 	.set_rate = r9a06g032_div_set_rate,
667 };
668 
669 static struct clk *
670 r9a06g032_register_div(struct r9a06g032_priv *clocks,
671 		       const char *parent_name,
672 		       const struct r9a06g032_clkdesc *desc)
673 {
674 	struct r9a06g032_clk_div *div;
675 	struct clk *clk;
676 	struct clk_init_data init;
677 	unsigned int i;
678 
679 	div = kzalloc(sizeof(*div), GFP_KERNEL);
680 	if (!div)
681 		return NULL;
682 
683 	init.name = desc->name;
684 	init.ops = &r9a06g032_clk_div_ops;
685 	init.flags = CLK_SET_RATE_PARENT;
686 	init.parent_names = parent_name ? &parent_name : NULL;
687 	init.num_parents = parent_name ? 1 : 0;
688 
689 	div->clocks = clocks;
690 	div->index = desc->index;
691 	div->reg = desc->reg;
692 	div->hw.init = &init;
693 	div->min = desc->div_min;
694 	div->max = desc->div_max;
695 	/* populate (optional) divider table fixed values */
696 	for (i = 0; i < ARRAY_SIZE(div->table) &&
697 	     i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {
698 		div->table[div->table_size++] = desc->div_table[i];
699 	}
700 
701 	clk = clk_register(NULL, &div->hw);
702 	if (IS_ERR(clk)) {
703 		kfree(div);
704 		return NULL;
705 	}
706 	return clk;
707 }
708 
709 /*
710  * This clock provider handles the case of the R9A06G032 where you have
711  * peripherals that have two potential clock source and two gates, one for
712  * each of the clock source - the used clock source (for all sub clocks)
713  * is selected by a single bit.
714  * That single bit affects all sub-clocks, and therefore needs to change the
715  * active gate (and turn the others off) and force a recalculation of the rates.
716  *
717  * This implements two clock providers, one 'bitselect' that
718  * handles the switch between both parents, and another 'dualgate'
719  * that knows which gate to poke at, depending on the parent's bit position.
720  */
721 struct r9a06g032_clk_bitsel {
722 	struct clk_hw	hw;
723 	struct r9a06g032_priv *clocks;
724 	u16 index;
725 	u16 selector;		/* selector register + bit */
726 };
727 
728 #define to_clk_bitselect(_hw) \
729 		container_of(_hw, struct r9a06g032_clk_bitsel, hw)
730 
731 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
732 {
733 	struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
734 
735 	return clk_rdesc_get(set->clocks, set->selector);
736 }
737 
738 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
739 {
740 	struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
741 
742 	/* a single bit in the register selects one of two parent clocks */
743 	clk_rdesc_set(set->clocks, set->selector, !!index);
744 
745 	return 0;
746 }
747 
748 static const struct clk_ops clk_bitselect_ops = {
749 	.get_parent = r9a06g032_clk_mux_get_parent,
750 	.set_parent = r9a06g032_clk_mux_set_parent,
751 };
752 
753 static struct clk *
754 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
755 			  const char *parent_name,
756 			  const struct r9a06g032_clkdesc *desc)
757 {
758 	struct clk *clk;
759 	struct r9a06g032_clk_bitsel *g;
760 	struct clk_init_data init;
761 	const char *names[2];
762 
763 	/* allocate the gate */
764 	g = kzalloc(sizeof(*g), GFP_KERNEL);
765 	if (!g)
766 		return NULL;
767 
768 	names[0] = parent_name;
769 	names[1] = "clk_pll_usb";
770 
771 	init.name = desc->name;
772 	init.ops = &clk_bitselect_ops;
773 	init.flags = CLK_SET_RATE_PARENT;
774 	init.parent_names = names;
775 	init.num_parents = 2;
776 
777 	g->clocks = clocks;
778 	g->index = desc->index;
779 	g->selector = desc->dual.sel;
780 	g->hw.init = &init;
781 
782 	clk = clk_register(NULL, &g->hw);
783 	if (IS_ERR(clk)) {
784 		kfree(g);
785 		return NULL;
786 	}
787 	return clk;
788 }
789 
790 struct r9a06g032_clk_dualgate {
791 	struct clk_hw	hw;
792 	struct r9a06g032_priv *clocks;
793 	u16 index;
794 	u16 selector;		/* selector register + bit */
795 	struct r9a06g032_gate gate[2];
796 };
797 
798 #define to_clk_dualgate(_hw) \
799 		container_of(_hw, struct r9a06g032_clk_dualgate, hw)
800 
801 static int
802 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
803 {
804 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
805 
806 	/* we always turn off the 'other' gate, regardless */
807 	r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
808 	r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
809 
810 	return 0;
811 }
812 
813 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
814 {
815 	struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
816 
817 	r9a06g032_clk_dualgate_setenable(gate, 1);
818 
819 	return 0;
820 }
821 
822 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
823 {
824 	struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
825 
826 	r9a06g032_clk_dualgate_setenable(gate, 0);
827 }
828 
829 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
830 {
831 	struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
832 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
833 
834 	return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
835 }
836 
837 static const struct clk_ops r9a06g032_clk_dualgate_ops = {
838 	.enable = r9a06g032_clk_dualgate_enable,
839 	.disable = r9a06g032_clk_dualgate_disable,
840 	.is_enabled = r9a06g032_clk_dualgate_is_enabled,
841 };
842 
843 static struct clk *
844 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
845 			    const char *parent_name,
846 			    const struct r9a06g032_clkdesc *desc,
847 			    uint16_t sel)
848 {
849 	struct r9a06g032_clk_dualgate *g;
850 	struct clk *clk;
851 	struct clk_init_data init;
852 
853 	/* allocate the gate */
854 	g = kzalloc(sizeof(*g), GFP_KERNEL);
855 	if (!g)
856 		return NULL;
857 	g->clocks = clocks;
858 	g->index = desc->index;
859 	g->selector = sel;
860 	g->gate[0].gate = desc->dual.g1;
861 	g->gate[0].reset = desc->dual.r1;
862 	g->gate[1].gate = desc->dual.g2;
863 	g->gate[1].reset = desc->dual.r2;
864 
865 	init.name = desc->name;
866 	init.ops = &r9a06g032_clk_dualgate_ops;
867 	init.flags = CLK_SET_RATE_PARENT;
868 	init.parent_names = &parent_name;
869 	init.num_parents = 1;
870 	g->hw.init = &init;
871 	/*
872 	 * important here, some clocks are already in use by the CM3, we
873 	 * have to assume they are not Linux's to play with and try to disable
874 	 * at the end of the boot!
875 	 */
876 	if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
877 		init.flags |= CLK_IS_CRITICAL;
878 		pr_debug("%s was enabled, making read-only\n", desc->name);
879 	}
880 
881 	clk = clk_register(NULL, &g->hw);
882 	if (IS_ERR(clk)) {
883 		kfree(g);
884 		return NULL;
885 	}
886 	return clk;
887 }
888 
889 static void r9a06g032_clocks_del_clk_provider(void *data)
890 {
891 	of_clk_del_provider(data);
892 }
893 
894 static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
895 {
896 	struct device *dev = &pdev->dev;
897 	struct device_node *np = dev->of_node;
898 	struct r9a06g032_priv *clocks;
899 	struct clk **clks;
900 	struct clk *mclk;
901 	unsigned int i;
902 	u16 uart_group_sel[2];
903 	int error;
904 
905 	clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
906 	clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
907 			    GFP_KERNEL);
908 	if (!clocks || !clks)
909 		return -ENOMEM;
910 
911 	spin_lock_init(&clocks->lock);
912 
913 	clocks->data.clks = clks;
914 	clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
915 
916 	mclk = devm_clk_get(dev, "mclk");
917 	if (IS_ERR(mclk))
918 		return PTR_ERR(mclk);
919 
920 	clocks->reg = of_iomap(np, 0);
921 	if (WARN_ON(!clocks->reg))
922 		return -ENOMEM;
923 	for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
924 		const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
925 		const char *parent_name = d->source ?
926 			__clk_get_name(clocks->data.clks[d->source - 1]) :
927 			__clk_get_name(mclk);
928 		struct clk *clk = NULL;
929 
930 		switch (d->type) {
931 		case K_FFC:
932 			clk = clk_register_fixed_factor(NULL, d->name,
933 							parent_name, 0,
934 							d->mul, d->div);
935 			break;
936 		case K_GATE:
937 			clk = r9a06g032_register_gate(clocks, parent_name, d);
938 			break;
939 		case K_DIV:
940 			clk = r9a06g032_register_div(clocks, parent_name, d);
941 			break;
942 		case K_BITSEL:
943 			/* keep that selector register around */
944 			uart_group_sel[d->dual.group] = d->dual.sel;
945 			clk = r9a06g032_register_bitsel(clocks, parent_name, d);
946 			break;
947 		case K_DUALGATE:
948 			clk = r9a06g032_register_dualgate(clocks, parent_name,
949 							  d,
950 							  uart_group_sel[d->dual.group]);
951 			break;
952 		}
953 		clocks->data.clks[d->index] = clk;
954 	}
955 	error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
956 	if (error)
957 		return error;
958 
959 	error = devm_add_action_or_reset(dev,
960 					r9a06g032_clocks_del_clk_provider, np);
961 	if (error)
962 		return error;
963 
964 	return r9a06g032_add_clk_domain(dev);
965 }
966 
967 static const struct of_device_id r9a06g032_match[] = {
968 	{ .compatible = "renesas,r9a06g032-sysctrl" },
969 	{ }
970 };
971 
972 static struct platform_driver r9a06g032_clock_driver = {
973 	.driver		= {
974 		.name	= "renesas,r9a06g032-sysctrl",
975 		.of_match_table = r9a06g032_match,
976 	},
977 };
978 
979 static int __init r9a06g032_clocks_init(void)
980 {
981 	return platform_driver_probe(&r9a06g032_clock_driver,
982 			r9a06g032_clocks_probe);
983 }
984 
985 subsys_initcall(r9a06g032_clocks_init);
986