1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R9A06G032 clock driver 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/math64.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_clock.h> 22 #include <linux/pm_domain.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/r9a06g032-sysctrl.h> 25 #include <linux/spinlock.h> 26 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 27 28 #define R9A06G032_SYSCTRL_USB 0x00 29 #define R9A06G032_SYSCTRL_USB_H2MODE (1<<1) 30 #define R9A06G032_SYSCTRL_DMAMUX 0xA0 31 32 /** 33 * struct regbit - describe one bit in a register 34 * @reg: offset of register relative to base address, 35 * expressed in units of 32-bit words (not bytes), 36 * @bit: which bit (0 to 31) in the register 37 * 38 * This structure is used to compactly encode the location 39 * of a single bit in a register. Five bits are needed to 40 * encode the bit number. With uint16_t data type, this 41 * leaves 11 bits to encode a register offset up to 2047. 42 * 43 * Since registers are aligned on 32-bit boundaries, the 44 * offset will be specified in 32-bit words rather than bytes. 45 * This allows encoding an offset up to 0x1FFC (8188) bytes. 46 * 47 * Helper macro RB() takes care of converting the register 48 * offset from bytes to 32-bit words. 49 */ 50 struct regbit { 51 u16 bit:5; 52 u16 reg:11; 53 }; 54 55 #define RB(_reg, _bit) ((struct regbit) { \ 56 .reg = (_reg) / 4, \ 57 .bit = (_bit) \ 58 }) 59 60 /** 61 * struct r9a06g032_gate - clock-related control bits 62 * @gate: clock enable/disable 63 * @reset: clock module reset (active low) 64 * @ready: enables NoC forwarding of read/write requests to device, 65 * (eg. device is ready to handle read/write requests) 66 * @midle: request to idle the NoC interconnect 67 * 68 * Each of these fields describes a single bit in a register, 69 * which controls some aspect of clock gating. The @gate field 70 * is mandatory, this one enables/disables the clock. The 71 * other fields are optional, with zero indicating "not used". 72 * 73 * In most cases there is a @reset bit which needs to be 74 * de-asserted to bring the module out of reset. 75 * 76 * Modules may also need to signal when they are @ready to 77 * handle requests (read/writes) from the NoC interconnect. 78 * 79 * Similarly, the @midle bit is used to idle the master. 80 */ 81 struct r9a06g032_gate { 82 struct regbit gate, reset, ready, midle; 83 /* Unused fields omitted to save space */ 84 /* struct regbit scon, mirack, mistat */; 85 }; 86 87 enum gate_type { 88 K_GATE = 0, /* gate which enable/disable */ 89 K_FFC, /* fixed factor clock */ 90 K_DIV, /* divisor */ 91 K_BITSEL, /* special for UARTs */ 92 K_DUALGATE /* special for UARTs */ 93 }; 94 95 /** 96 * struct r9a06g032_clkdesc - describe a single clock 97 * @name: string describing this clock 98 * @managed: boolean indicating if this clock should be 99 * started/stopped as part of power management 100 * @type: see enum @gate_type 101 * @index: the ID of this clock element 102 * @source: the ID+1 of the parent clock element. 103 * Root clock uses ID of ~0 (PARENT_ID); 104 * @gate: clock enable/disable 105 * @div_min: smallest permitted clock divider 106 * @div_max: largest permitted clock divider 107 * @reg: clock divider register offset, in 32-bit words 108 * @div_table: optional list of fixed clock divider values; 109 * must be in ascending order, zero for unused 110 * @div: divisor for fixed-factor clock 111 * @mul: multiplier for fixed-factor clock 112 * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7 113 * @sel: select either g1/r1 or g2/r2 as clock source 114 * @g1: 1st source gate (clock enable/disable) 115 * @r1: 1st source reset (module reset) 116 * @g2: 2nd source gate (clock enable/disable) 117 * @r2: 2nd source reset (module reset) 118 * 119 * Describes a single element in the clock tree hierarchy. 120 * As there are quite a large number of clock elements, this 121 * structure is packed tightly to conserve space. 122 */ 123 struct r9a06g032_clkdesc { 124 const char *name; 125 uint32_t managed:1; 126 enum gate_type type:3; 127 uint32_t index:8; 128 uint32_t source:8; /* source index + 1 (0 == none) */ 129 union { 130 /* type = K_GATE */ 131 struct r9a06g032_gate gate; 132 /* type = K_DIV */ 133 struct { 134 unsigned int div_min:10, div_max:10, reg:10; 135 u16 div_table[4]; 136 }; 137 /* type = K_FFC */ 138 struct { 139 u16 div, mul; 140 }; 141 /* type = K_DUALGATE */ 142 struct { 143 uint16_t group:1; 144 struct regbit sel, g1, r1, g2, r2; 145 } dual; 146 }; 147 }; 148 149 /* 150 * The last three arguments are not currently used, 151 * but are kept in the r9a06g032_clocks table below. 152 */ 153 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ 154 .gate = _clk, \ 155 .reset = _rst, \ 156 .ready = _rdy, \ 157 .midle = _midle, \ 158 /* .scon = _scon, */ \ 159 /* .mirack = _mirack, */ \ 160 /* .mistat = _mistat */ \ 161 } 162 #define D_GATE(_idx, _n, _src, ...) { \ 163 .type = K_GATE, \ 164 .index = R9A06G032_##_idx, \ 165 .source = 1 + R9A06G032_##_src, \ 166 .name = _n, \ 167 .gate = I_GATE(__VA_ARGS__) \ 168 } 169 #define D_MODULE(_idx, _n, _src, ...) { \ 170 .type = K_GATE, \ 171 .index = R9A06G032_##_idx, \ 172 .source = 1 + R9A06G032_##_src, \ 173 .name = _n, \ 174 .managed = 1, \ 175 .gate = I_GATE(__VA_ARGS__) \ 176 } 177 #define D_ROOT(_idx, _n, _mul, _div) { \ 178 .type = K_FFC, \ 179 .index = R9A06G032_##_idx, \ 180 .name = _n, \ 181 .div = _div, \ 182 .mul = _mul \ 183 } 184 #define D_FFC(_idx, _n, _src, _div) { \ 185 .type = K_FFC, \ 186 .index = R9A06G032_##_idx, \ 187 .source = 1 + R9A06G032_##_src, \ 188 .name = _n, \ 189 .div = _div, \ 190 .mul = 1 \ 191 } 192 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ 193 .type = K_DIV, \ 194 .index = R9A06G032_##_idx, \ 195 .source = 1 + R9A06G032_##_src, \ 196 .name = _n, \ 197 .reg = _reg, \ 198 .div_min = _min, \ 199 .div_max = _max, \ 200 .div_table = { __VA_ARGS__ } \ 201 } 202 #define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \ 203 .type = K_DUALGATE, \ 204 .index = R9A06G032_##_idx, \ 205 .source = 1 + R9A06G032_##_src, \ 206 .name = _n, \ 207 .dual = { \ 208 .group = _g, \ 209 .g1 = _g1, \ 210 .r1 = _r1, \ 211 .g2 = _g2, \ 212 .r2 = _r2 \ 213 }, \ 214 } 215 216 /* Internal clock IDs */ 217 #define R9A06G032_CLKOUT 0 218 #define R9A06G032_CLKOUT_D10 2 219 #define R9A06G032_CLKOUT_D16 3 220 #define R9A06G032_CLKOUT_D160 4 221 #define R9A06G032_CLKOUT_D1OR2 5 222 #define R9A06G032_CLKOUT_D20 6 223 #define R9A06G032_CLKOUT_D40 7 224 #define R9A06G032_CLKOUT_D5 8 225 #define R9A06G032_CLKOUT_D8 9 226 #define R9A06G032_DIV_ADC 10 227 #define R9A06G032_DIV_I2C 11 228 #define R9A06G032_DIV_NAND 12 229 #define R9A06G032_DIV_P1_PG 13 230 #define R9A06G032_DIV_P2_PG 14 231 #define R9A06G032_DIV_P3_PG 15 232 #define R9A06G032_DIV_P4_PG 16 233 #define R9A06G032_DIV_P5_PG 17 234 #define R9A06G032_DIV_P6_PG 18 235 #define R9A06G032_DIV_QSPI0 19 236 #define R9A06G032_DIV_QSPI1 20 237 #define R9A06G032_DIV_REF_SYNC 21 238 #define R9A06G032_DIV_SDIO0 22 239 #define R9A06G032_DIV_SDIO1 23 240 #define R9A06G032_DIV_SWITCH 24 241 #define R9A06G032_DIV_UART 25 242 #define R9A06G032_DIV_MOTOR 64 243 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78 244 #define R9A06G032_CLK_ECAT100_D4 79 245 #define R9A06G032_CLK_HSR100_D2 80 246 #define R9A06G032_CLK_REF_SYNC_D4 81 247 #define R9A06G032_CLK_REF_SYNC_D8 82 248 #define R9A06G032_CLK_SERCOS100_D2 83 249 #define R9A06G032_DIV_CA7 84 250 251 #define R9A06G032_UART_GROUP_012 154 252 #define R9A06G032_UART_GROUP_34567 155 253 254 #define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1) 255 256 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { 257 D_ROOT(CLKOUT, "clkout", 25, 1), 258 D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10), 259 D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10), 260 D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16), 261 D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160), 262 D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2), 263 D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20), 264 D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40), 265 D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5), 266 D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8), 267 D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250), 268 D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16), 269 D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32), 270 D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200), 271 D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128), 272 D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128), 273 D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128), 274 D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40), 275 D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64), 276 D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7), 277 D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7), 278 D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16), 279 D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128), 280 D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128), 281 D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40), 282 D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128), 283 D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9), 284 RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0), 285 RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)), 286 D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12), 287 RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0), 288 RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)), 289 D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15), 290 RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0), 291 RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)), 292 D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18), 293 RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0), 294 RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)), 295 D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21), 296 RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0), 297 RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)), 298 D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10), 299 RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0), 300 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 301 D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5), 302 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 303 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 304 D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3), 305 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 306 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 307 D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6), 308 RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0), 309 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 310 D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8), 311 RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0), 312 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 313 D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2), 314 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 315 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 316 D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4), 317 RB(0x50, 5), RB(0x00, 0), RB(0x00, 0), 318 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 319 D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20), 320 RB(0xec, 21), RB(0x00, 0), RB(0x00, 0), 321 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 322 D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2), 323 RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0), 324 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 325 D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4), 326 RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0), 327 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 328 D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6), 329 RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0), 330 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 331 D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4), 332 RB(0x104, 5), RB(0x00, 0), RB(0x00, 0), 333 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 334 D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6), 335 RB(0x104, 7), RB(0x00, 0), RB(0x00, 0), 336 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 337 D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0), 338 RB(0x114, 1), RB(0x114, 2), RB(0x00, 0), 339 RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)), 340 D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3), 341 RB(0x114, 4), RB(0x114, 5), RB(0x00, 0), 342 RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)), 343 D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6), 344 RB(0x114, 7), RB(0x114, 8), RB(0x00, 0), 345 RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)), 346 D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9), 347 RB(0x114, 10), RB(0x114, 11), RB(0x00, 0), 348 RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)), 349 D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6), 350 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 351 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 352 D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4), 353 RB(0x54, 5), RB(0x00, 0), RB(0x00, 0), 354 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 355 D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4), 356 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), 357 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 358 D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0), 359 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 360 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 361 D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1), 362 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 363 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 364 D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4), 365 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 366 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 367 D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4), 368 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 369 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 370 D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5), 371 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 372 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 373 D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0), 374 RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0), 375 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 376 D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0), 377 RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0), 378 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 379 D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2), 380 RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0), 381 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 382 D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4), 383 RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0), 384 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 385 D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6), 386 RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0), 387 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 388 D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0), 389 RB(0x104, 1), RB(0x00, 0), RB(0x00, 0), 390 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 391 D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2), 392 RB(0x104, 3), RB(0x00, 0), RB(0x00, 0), 393 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 394 D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2), 395 RB(0x130, 3), RB(0x00, 0), RB(0x00, 0), 396 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 397 D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8), 398 D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0), 399 RB(0x80, 1), RB(0x00, 0), RB(0x80, 2), 400 RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)), 401 D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0), 402 RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0), 403 RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)), 404 D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0), 405 RB(0x84, 2), RB(0x00, 0), RB(0x84, 1), 406 RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)), 407 D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3), 408 RB(0x118, 4), RB(0x118, 5), RB(0x00, 0), 409 RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)), 410 D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6), 411 RB(0x118, 7), RB(0x118, 8), RB(0x00, 0), 412 RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)), 413 D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9), 414 RB(0x118, 10), RB(0x118, 11), RB(0x00, 0), 415 RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)), 416 D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3), 417 RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0), 418 RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)), 419 D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6), 420 RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0), 421 RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)), 422 D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3), 423 RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4), 424 RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)), 425 D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0), 426 RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2), 427 RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)), 428 D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5), 429 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), 430 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 431 D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12), 432 RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14), 433 RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)), 434 D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9), 435 RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0), 436 RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)), 437 D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4), 438 D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4), 439 D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2), 440 D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4), 441 D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8), 442 D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2), 443 D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4), 444 D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3), 445 RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0), 446 RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)), 447 D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6), 448 RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0), 449 RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)), 450 D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15), 451 RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0), 452 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 453 D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12), 454 RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0), 455 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 456 D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0), 457 RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0), 458 RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)), 459 D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0), 460 RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0), 461 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 462 D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3), 463 RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0), 464 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 465 D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640), 466 D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0), 467 RB(0x174, 1), RB(0x00, 0), RB(0x174, 2), 468 RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)), 469 D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3), 470 RB(0x64, 4), RB(0x00, 0), RB(0x00, 0), 471 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 472 D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3), 473 RB(0x80, 4), RB(0x00, 0), RB(0x00, 0), 474 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 475 D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4), 476 RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), 477 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 478 D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0), 479 RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0), 480 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 481 D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4), 482 RB(0x84, 3), RB(0x00, 0), RB(0x00, 0), 483 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 484 D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15), 485 RB(0x34, 16), RB(0x34, 17), RB(0x00, 0), 486 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 487 D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0), 488 RB(0x184, 1), RB(0x184, 2), RB(0x00, 0), 489 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 490 D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3), 491 RB(0x24, 4), RB(0x24, 5), RB(0x00, 0), 492 RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)), 493 D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0), 494 RB(0x24, 1), RB(0x00, 0), RB(0x24, 2), 495 RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)), 496 D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0), 497 RB(0x64, 2), RB(0x00, 0), RB(0x64, 1), 498 RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)), 499 D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0), 500 RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3), 501 RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)), 502 D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4), 503 RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7), 504 RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)), 505 D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0), 506 RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3), 507 RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)), 508 D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0), 509 RB(0x70, 1), RB(0x70, 2), RB(0x70, 3), 510 RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)), 511 D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18), 512 RB(0x40, 19), RB(0x40, 20), RB(0x00, 0), 513 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 514 D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21), 515 RB(0x40, 22), RB(0x40, 23), RB(0x00, 0), 516 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 517 D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9), 518 RB(0x44, 10), RB(0x44, 11), RB(0x00, 0), 519 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 520 D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0), 521 RB(0x90, 2), RB(0x00, 0), RB(0x90, 1), 522 RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)), 523 D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9), 524 RB(0x34, 10), RB(0x34, 11), RB(0x00, 0), 525 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 526 D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12), 527 RB(0x34, 13), RB(0x34, 14), RB(0x00, 0), 528 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 529 D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0), 530 RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0), 531 RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)), 532 D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4), 533 RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0), 534 RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)), 535 D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0), 536 RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3), 537 RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)), 538 D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0), 539 RB(0x50, 1), RB(0x50, 2), RB(0x50, 3), 540 RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)), 541 D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12), 542 RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14), 543 RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)), 544 D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12), 545 RB(0x44, 13), RB(0x44, 14), RB(0x00, 0), 546 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 547 D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15), 548 RB(0x44, 16), RB(0x44, 17), RB(0x00, 0), 549 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 550 D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6), 551 RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0), 552 RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)), 553 D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9), 554 RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0), 555 RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)), 556 D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0), 557 RB(0x54, 1), RB(0x54, 2), RB(0x54, 3), 558 RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)), 559 D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0), 560 RB(0x90, 1), RB(0x90, 2), RB(0x90, 3), 561 RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)), 562 D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0), 563 RB(0x154, 1), RB(0x154, 2), RB(0x00, 0), 564 RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)), 565 D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0), 566 RB(0x140, 3), RB(0x00, 0), RB(0x140, 2), 567 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 568 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0), 569 RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3), 570 RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)), 571 D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0), 572 RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3), 573 RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)), 574 D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3), 575 RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0), 576 RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)), 577 D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0), 578 RB(0x40, 1), RB(0x40, 2), RB(0x00, 0), 579 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 580 D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3), 581 RB(0x40, 4), RB(0x40, 5), RB(0x00, 0), 582 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 583 D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6), 584 RB(0x40, 7), RB(0x40, 8), RB(0x00, 0), 585 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 586 D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9), 587 RB(0x40, 10), RB(0x40, 11), RB(0x00, 0), 588 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 589 D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12), 590 RB(0x40, 13), RB(0x40, 14), RB(0x00, 0), 591 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 592 D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15), 593 RB(0x40, 16), RB(0x40, 17), RB(0x00, 0), 594 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 595 D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0), 596 RB(0x00, 0), RB(0x130, 1), RB(0x00, 0), 597 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 598 D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0), 599 RB(0x188, 1), RB(0x188, 2), RB(0x00, 0), 600 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 601 D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0), 602 RB(0x34, 1), RB(0x34, 2), RB(0x00, 0), 603 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 604 D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3), 605 RB(0x34, 4), RB(0x34, 5), RB(0x00, 0), 606 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 607 D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6), 608 RB(0x34, 7), RB(0x34, 8), RB(0x00, 0), 609 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 610 D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24), 611 RB(0x40, 25), RB(0x40, 26), RB(0x00, 0), 612 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 613 D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27), 614 RB(0x40, 28), RB(0x40, 29), RB(0x00, 0), 615 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 616 D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0), 617 RB(0x44, 1), RB(0x44, 2), RB(0x00, 0), 618 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 619 D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3), 620 RB(0x44, 4), RB(0x44, 5), RB(0x00, 0), 621 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 622 D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6), 623 RB(0x44, 7), RB(0x44, 8), RB(0x00, 0), 624 RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), 625 /* 626 * These are not hardware clocks, but are needed to handle the special 627 * case where we have a 'selector bit' that doesn't just change the 628 * parent for a clock, but also the gate it's supposed to use. 629 */ 630 { 631 .index = R9A06G032_UART_GROUP_012, 632 .name = "uart_group_012", 633 .type = K_BITSEL, 634 .source = 1 + R9A06G032_DIV_UART, 635 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ 636 .dual.sel = RB(0x34, 30), 637 .dual.group = 0, 638 }, 639 { 640 .index = R9A06G032_UART_GROUP_34567, 641 .name = "uart_group_34567", 642 .type = K_BITSEL, 643 .source = 1 + R9A06G032_DIV_P2_PG, 644 /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ 645 .dual.sel = RB(0xec, 24), 646 .dual.group = 1, 647 }, 648 D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 649 RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)), 650 D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 651 RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)), 652 D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 653 RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)), 654 D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 655 RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)), 656 D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 657 RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)), 658 D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 659 RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)), 660 D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 661 RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)), 662 D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 663 RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)), 664 }; 665 666 struct r9a06g032_priv { 667 struct clk_onecell_data data; 668 spinlock_t lock; /* protects concurrent access to gates */ 669 void __iomem *reg; 670 }; 671 672 static struct r9a06g032_priv *sysctrl_priv; 673 674 /* Exported helper to access the DMAMUX register */ 675 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) 676 { 677 unsigned long flags; 678 u32 dmamux; 679 680 if (!sysctrl_priv) 681 return -EPROBE_DEFER; 682 683 spin_lock_irqsave(&sysctrl_priv->lock, flags); 684 685 dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 686 dmamux &= ~mask; 687 dmamux |= val & mask; 688 writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); 689 690 spin_unlock_irqrestore(&sysctrl_priv->lock, flags); 691 692 return 0; 693 } 694 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); 695 696 static void clk_rdesc_set(struct r9a06g032_priv *clocks, 697 struct regbit rb, unsigned int on) 698 { 699 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 700 u32 val; 701 702 if (!rb.reg && !rb.bit) 703 return; 704 705 val = readl(reg); 706 val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit); 707 writel(val, reg); 708 } 709 710 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) 711 { 712 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 713 u32 val = readl(reg); 714 715 return !!(val & BIT(rb.bit)); 716 } 717 718 /* 719 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's 720 * clock gate framework as the gates on the R9A06G032 have a special enabling 721 * sequence, therefore we use this little proxy. 722 */ 723 struct r9a06g032_clk_gate { 724 struct clk_hw hw; 725 struct r9a06g032_priv *clocks; 726 u16 index; 727 728 struct r9a06g032_gate gate; 729 }; 730 731 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw) 732 733 static int create_add_module_clock(struct of_phandle_args *clkspec, 734 struct device *dev) 735 { 736 struct clk *clk; 737 int error; 738 739 clk = of_clk_get_from_provider(clkspec); 740 if (IS_ERR(clk)) 741 return PTR_ERR(clk); 742 743 error = pm_clk_create(dev); 744 if (error) { 745 clk_put(clk); 746 return error; 747 } 748 749 error = pm_clk_add_clk(dev, clk); 750 if (error) { 751 pm_clk_destroy(dev); 752 clk_put(clk); 753 } 754 755 return error; 756 } 757 758 static int r9a06g032_attach_dev(struct generic_pm_domain *pd, 759 struct device *dev) 760 { 761 struct device_node *np = dev->of_node; 762 struct of_phandle_args clkspec; 763 int i = 0; 764 int error; 765 int index; 766 767 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, 768 &clkspec)) { 769 if (clkspec.np != pd->dev.of_node) 770 continue; 771 772 index = clkspec.args[0]; 773 if (index < R9A06G032_CLOCK_COUNT && 774 r9a06g032_clocks[index].managed) { 775 error = create_add_module_clock(&clkspec, dev); 776 of_node_put(clkspec.np); 777 if (error) 778 return error; 779 } 780 } 781 782 return 0; 783 } 784 785 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev) 786 { 787 if (!pm_clk_no_clocks(dev)) 788 pm_clk_destroy(dev); 789 } 790 791 static int r9a06g032_add_clk_domain(struct device *dev) 792 { 793 struct device_node *np = dev->of_node; 794 struct generic_pm_domain *pd; 795 796 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); 797 if (!pd) 798 return -ENOMEM; 799 800 pd->name = np->name; 801 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 802 GENPD_FLAG_ACTIVE_WAKEUP; 803 pd->attach_dev = r9a06g032_attach_dev; 804 pd->detach_dev = r9a06g032_detach_dev; 805 pm_genpd_init(pd, &pm_domain_always_on_gov, false); 806 807 of_genpd_add_provider_simple(np, pd); 808 return 0; 809 } 810 811 static void 812 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, 813 struct r9a06g032_gate *g, int on) 814 { 815 unsigned long flags; 816 817 WARN_ON(!g->gate.reg && !g->gate.bit); 818 819 spin_lock_irqsave(&clocks->lock, flags); 820 clk_rdesc_set(clocks, g->gate, on); 821 /* De-assert reset */ 822 clk_rdesc_set(clocks, g->reset, 1); 823 spin_unlock_irqrestore(&clocks->lock, flags); 824 825 /* Hardware manual recommends 5us delay after enabling clock & reset */ 826 udelay(5); 827 828 /* If the peripheral is memory mapped (i.e. an AXI slave), there is an 829 * associated SLVRDY bit in the System Controller that needs to be set 830 * so that the FlexWAY bus fabric passes on the read/write requests. 831 */ 832 spin_lock_irqsave(&clocks->lock, flags); 833 clk_rdesc_set(clocks, g->ready, on); 834 /* Clear 'Master Idle Request' bit */ 835 clk_rdesc_set(clocks, g->midle, !on); 836 spin_unlock_irqrestore(&clocks->lock, flags); 837 838 /* Note: We don't wait for FlexWAY Socket Connection signal */ 839 } 840 841 static int r9a06g032_clk_gate_enable(struct clk_hw *hw) 842 { 843 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 844 845 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1); 846 return 0; 847 } 848 849 static void r9a06g032_clk_gate_disable(struct clk_hw *hw) 850 { 851 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 852 853 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0); 854 } 855 856 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw) 857 { 858 struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); 859 860 /* if clock is in reset, the gate might be on, and still not 'be' on */ 861 if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset)) 862 return 0; 863 864 return clk_rdesc_get(g->clocks, g->gate.gate); 865 } 866 867 static const struct clk_ops r9a06g032_clk_gate_ops = { 868 .enable = r9a06g032_clk_gate_enable, 869 .disable = r9a06g032_clk_gate_disable, 870 .is_enabled = r9a06g032_clk_gate_is_enabled, 871 }; 872 873 static struct clk * 874 r9a06g032_register_gate(struct r9a06g032_priv *clocks, 875 const char *parent_name, 876 const struct r9a06g032_clkdesc *desc) 877 { 878 struct clk *clk; 879 struct r9a06g032_clk_gate *g; 880 struct clk_init_data init = {}; 881 882 g = kzalloc(sizeof(*g), GFP_KERNEL); 883 if (!g) 884 return NULL; 885 886 init.name = desc->name; 887 init.ops = &r9a06g032_clk_gate_ops; 888 init.flags = CLK_SET_RATE_PARENT; 889 init.parent_names = parent_name ? &parent_name : NULL; 890 init.num_parents = parent_name ? 1 : 0; 891 892 g->clocks = clocks; 893 g->index = desc->index; 894 g->gate = desc->gate; 895 g->hw.init = &init; 896 897 /* 898 * important here, some clocks are already in use by the CM3, we 899 * have to assume they are not Linux's to play with and try to disable 900 * at the end of the boot! 901 */ 902 if (r9a06g032_clk_gate_is_enabled(&g->hw)) { 903 init.flags |= CLK_IS_CRITICAL; 904 pr_debug("%s was enabled, making read-only\n", desc->name); 905 } 906 907 clk = clk_register(NULL, &g->hw); 908 if (IS_ERR(clk)) { 909 kfree(g); 910 return NULL; 911 } 912 return clk; 913 } 914 915 struct r9a06g032_clk_div { 916 struct clk_hw hw; 917 struct r9a06g032_priv *clocks; 918 u16 index; 919 u16 reg; 920 u16 min, max; 921 u8 table_size; 922 u16 table[8]; /* we know there are no more than 8 */ 923 }; 924 925 #define to_r9a06g032_div(_hw) \ 926 container_of(_hw, struct r9a06g032_clk_div, hw) 927 928 static unsigned long 929 r9a06g032_div_recalc_rate(struct clk_hw *hw, 930 unsigned long parent_rate) 931 { 932 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 933 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 934 u32 div = readl(reg); 935 936 if (div < clk->min) 937 div = clk->min; 938 else if (div > clk->max) 939 div = clk->max; 940 return DIV_ROUND_UP(parent_rate, div); 941 } 942 943 /* 944 * Attempts to find a value that is in range of min,max, 945 * and if a table of set dividers was specified for this 946 * register, try to find the fixed divider that is the closest 947 * to the target frequency 948 */ 949 static long 950 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, 951 unsigned long rate, unsigned long prate) 952 { 953 /* + 1 to cope with rates that have the remainder dropped */ 954 u32 div = DIV_ROUND_UP(prate, rate + 1); 955 int i; 956 957 if (div <= clk->min) 958 return clk->min; 959 if (div >= clk->max) 960 return clk->max; 961 962 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) { 963 if (div >= clk->table[i] && div <= clk->table[i + 1]) { 964 unsigned long m = rate - 965 DIV_ROUND_UP(prate, clk->table[i]); 966 unsigned long p = 967 DIV_ROUND_UP(prate, clk->table[i + 1]) - 968 rate; 969 /* 970 * select the divider that generates 971 * the value closest to the ideal frequency 972 */ 973 div = p >= m ? clk->table[i] : clk->table[i + 1]; 974 return div; 975 } 976 } 977 return div; 978 } 979 980 static int 981 r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 982 { 983 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 984 u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate); 985 986 pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__, 987 hw->clk, req->rate, req->best_parent_rate, div); 988 pr_devel(" min %d (%ld) max %d (%ld)\n", 989 clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min), 990 clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max)); 991 992 div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate); 993 /* 994 * this is a hack. Currently the serial driver asks for a clock rate 995 * that is 16 times the baud rate -- and that is wildly outside the 996 * range of the UART divider, somehow there is no provision for that 997 * case of 'let the divider as is if outside range'. 998 * The serial driver *shouldn't* play with these clocks anyway, there's 999 * several uarts attached to this divider, and changing this impacts 1000 * everyone. 1001 */ 1002 if (clk->index == R9A06G032_DIV_UART || 1003 clk->index == R9A06G032_DIV_P2_PG) { 1004 pr_devel("%s div uart hack!\n", __func__); 1005 req->rate = clk_get_rate(hw->clk); 1006 return 0; 1007 } 1008 req->rate = DIV_ROUND_UP(req->best_parent_rate, div); 1009 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk, 1010 req->best_parent_rate, div, req->rate); 1011 return 0; 1012 } 1013 1014 static int 1015 r9a06g032_div_set_rate(struct clk_hw *hw, 1016 unsigned long rate, unsigned long parent_rate) 1017 { 1018 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); 1019 /* + 1 to cope with rates that have the remainder dropped */ 1020 u32 div = DIV_ROUND_UP(parent_rate, rate + 1); 1021 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); 1022 1023 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk, 1024 rate, parent_rate, div); 1025 1026 /* 1027 * Need to write the bit 31 with the divider value to 1028 * latch it. Technically we should wait until it has been 1029 * cleared too. 1030 * TODO: Find whether this callback is sleepable, in case 1031 * the hardware /does/ require some sort of spinloop here. 1032 */ 1033 writel(div | BIT(31), reg); 1034 1035 return 0; 1036 } 1037 1038 static const struct clk_ops r9a06g032_clk_div_ops = { 1039 .recalc_rate = r9a06g032_div_recalc_rate, 1040 .determine_rate = r9a06g032_div_determine_rate, 1041 .set_rate = r9a06g032_div_set_rate, 1042 }; 1043 1044 static struct clk * 1045 r9a06g032_register_div(struct r9a06g032_priv *clocks, 1046 const char *parent_name, 1047 const struct r9a06g032_clkdesc *desc) 1048 { 1049 struct r9a06g032_clk_div *div; 1050 struct clk *clk; 1051 struct clk_init_data init = {}; 1052 unsigned int i; 1053 1054 div = kzalloc(sizeof(*div), GFP_KERNEL); 1055 if (!div) 1056 return NULL; 1057 1058 init.name = desc->name; 1059 init.ops = &r9a06g032_clk_div_ops; 1060 init.flags = CLK_SET_RATE_PARENT; 1061 init.parent_names = parent_name ? &parent_name : NULL; 1062 init.num_parents = parent_name ? 1 : 0; 1063 1064 div->clocks = clocks; 1065 div->index = desc->index; 1066 div->reg = desc->reg; 1067 div->hw.init = &init; 1068 div->min = desc->div_min; 1069 div->max = desc->div_max; 1070 /* populate (optional) divider table fixed values */ 1071 for (i = 0; i < ARRAY_SIZE(div->table) && 1072 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { 1073 div->table[div->table_size++] = desc->div_table[i]; 1074 } 1075 1076 clk = clk_register(NULL, &div->hw); 1077 if (IS_ERR(clk)) { 1078 kfree(div); 1079 return NULL; 1080 } 1081 return clk; 1082 } 1083 1084 /* 1085 * This clock provider handles the case of the R9A06G032 where you have 1086 * peripherals that have two potential clock source and two gates, one for 1087 * each of the clock source - the used clock source (for all sub clocks) 1088 * is selected by a single bit. 1089 * That single bit affects all sub-clocks, and therefore needs to change the 1090 * active gate (and turn the others off) and force a recalculation of the rates. 1091 * 1092 * This implements two clock providers, one 'bitselect' that 1093 * handles the switch between both parents, and another 'dualgate' 1094 * that knows which gate to poke at, depending on the parent's bit position. 1095 */ 1096 struct r9a06g032_clk_bitsel { 1097 struct clk_hw hw; 1098 struct r9a06g032_priv *clocks; 1099 u16 index; 1100 struct regbit selector; /* selector register + bit */ 1101 }; 1102 1103 #define to_clk_bitselect(_hw) \ 1104 container_of(_hw, struct r9a06g032_clk_bitsel, hw) 1105 1106 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw) 1107 { 1108 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 1109 1110 return clk_rdesc_get(set->clocks, set->selector); 1111 } 1112 1113 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index) 1114 { 1115 struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw); 1116 1117 /* a single bit in the register selects one of two parent clocks */ 1118 clk_rdesc_set(set->clocks, set->selector, !!index); 1119 1120 return 0; 1121 } 1122 1123 static const struct clk_ops clk_bitselect_ops = { 1124 .determine_rate = clk_hw_determine_rate_no_reparent, 1125 .get_parent = r9a06g032_clk_mux_get_parent, 1126 .set_parent = r9a06g032_clk_mux_set_parent, 1127 }; 1128 1129 static struct clk * 1130 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, 1131 const char *parent_name, 1132 const struct r9a06g032_clkdesc *desc) 1133 { 1134 struct clk *clk; 1135 struct r9a06g032_clk_bitsel *g; 1136 struct clk_init_data init = {}; 1137 const char *names[2]; 1138 1139 /* allocate the gate */ 1140 g = kzalloc(sizeof(*g), GFP_KERNEL); 1141 if (!g) 1142 return NULL; 1143 1144 names[0] = parent_name; 1145 names[1] = "clk_pll_usb"; 1146 1147 init.name = desc->name; 1148 init.ops = &clk_bitselect_ops; 1149 init.flags = CLK_SET_RATE_PARENT; 1150 init.parent_names = names; 1151 init.num_parents = 2; 1152 1153 g->clocks = clocks; 1154 g->index = desc->index; 1155 g->selector = desc->dual.sel; 1156 g->hw.init = &init; 1157 1158 clk = clk_register(NULL, &g->hw); 1159 if (IS_ERR(clk)) { 1160 kfree(g); 1161 return NULL; 1162 } 1163 return clk; 1164 } 1165 1166 struct r9a06g032_clk_dualgate { 1167 struct clk_hw hw; 1168 struct r9a06g032_priv *clocks; 1169 u16 index; 1170 struct regbit selector; /* selector register + bit */ 1171 struct r9a06g032_gate gate[2]; 1172 }; 1173 1174 #define to_clk_dualgate(_hw) \ 1175 container_of(_hw, struct r9a06g032_clk_dualgate, hw) 1176 1177 static int 1178 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable) 1179 { 1180 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 1181 1182 /* we always turn off the 'other' gate, regardless */ 1183 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0); 1184 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable); 1185 1186 return 0; 1187 } 1188 1189 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw) 1190 { 1191 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 1192 1193 r9a06g032_clk_dualgate_setenable(gate, 1); 1194 1195 return 0; 1196 } 1197 1198 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw) 1199 { 1200 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw); 1201 1202 r9a06g032_clk_dualgate_setenable(gate, 0); 1203 } 1204 1205 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw) 1206 { 1207 struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw); 1208 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); 1209 1210 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate); 1211 } 1212 1213 static const struct clk_ops r9a06g032_clk_dualgate_ops = { 1214 .enable = r9a06g032_clk_dualgate_enable, 1215 .disable = r9a06g032_clk_dualgate_disable, 1216 .is_enabled = r9a06g032_clk_dualgate_is_enabled, 1217 }; 1218 1219 static struct clk * 1220 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, 1221 const char *parent_name, 1222 const struct r9a06g032_clkdesc *desc, 1223 struct regbit sel) 1224 { 1225 struct r9a06g032_clk_dualgate *g; 1226 struct clk *clk; 1227 struct clk_init_data init = {}; 1228 1229 /* allocate the gate */ 1230 g = kzalloc(sizeof(*g), GFP_KERNEL); 1231 if (!g) 1232 return NULL; 1233 g->clocks = clocks; 1234 g->index = desc->index; 1235 g->selector = sel; 1236 g->gate[0].gate = desc->dual.g1; 1237 g->gate[0].reset = desc->dual.r1; 1238 g->gate[1].gate = desc->dual.g2; 1239 g->gate[1].reset = desc->dual.r2; 1240 1241 init.name = desc->name; 1242 init.ops = &r9a06g032_clk_dualgate_ops; 1243 init.flags = CLK_SET_RATE_PARENT; 1244 init.parent_names = &parent_name; 1245 init.num_parents = 1; 1246 g->hw.init = &init; 1247 /* 1248 * important here, some clocks are already in use by the CM3, we 1249 * have to assume they are not Linux's to play with and try to disable 1250 * at the end of the boot! 1251 */ 1252 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) { 1253 init.flags |= CLK_IS_CRITICAL; 1254 pr_debug("%s was enabled, making read-only\n", desc->name); 1255 } 1256 1257 clk = clk_register(NULL, &g->hw); 1258 if (IS_ERR(clk)) { 1259 kfree(g); 1260 return NULL; 1261 } 1262 return clk; 1263 } 1264 1265 static void r9a06g032_clocks_del_clk_provider(void *data) 1266 { 1267 of_clk_del_provider(data); 1268 } 1269 1270 static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) 1271 { 1272 struct device_node *usbf_np = NULL; 1273 u32 usb; 1274 1275 while ((usbf_np = of_find_compatible_node(usbf_np, NULL, 1276 "renesas,rzn1-usbf"))) { 1277 if (of_device_is_available(usbf_np)) 1278 break; 1279 } 1280 1281 usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB); 1282 if (usbf_np) { 1283 /* 1 host and 1 device mode */ 1284 usb &= ~R9A06G032_SYSCTRL_USB_H2MODE; 1285 of_node_put(usbf_np); 1286 } else { 1287 /* 2 hosts mode */ 1288 usb |= R9A06G032_SYSCTRL_USB_H2MODE; 1289 } 1290 writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB); 1291 } 1292 1293 static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 1294 { 1295 struct device *dev = &pdev->dev; 1296 struct device_node *np = dev->of_node; 1297 struct r9a06g032_priv *clocks; 1298 struct clk **clks; 1299 struct clk *mclk; 1300 unsigned int i; 1301 struct regbit uart_group_sel[2]; 1302 int error; 1303 1304 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL); 1305 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *), 1306 GFP_KERNEL); 1307 if (!clocks || !clks) 1308 return -ENOMEM; 1309 1310 spin_lock_init(&clocks->lock); 1311 1312 clocks->data.clks = clks; 1313 clocks->data.clk_num = R9A06G032_CLOCK_COUNT; 1314 1315 mclk = devm_clk_get(dev, "mclk"); 1316 if (IS_ERR(mclk)) 1317 return PTR_ERR(mclk); 1318 1319 clocks->reg = of_iomap(np, 0); 1320 if (WARN_ON(!clocks->reg)) 1321 return -ENOMEM; 1322 1323 r9a06g032_init_h2mode(clocks); 1324 1325 for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) { 1326 const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i]; 1327 const char *parent_name = d->source ? 1328 __clk_get_name(clocks->data.clks[d->source - 1]) : 1329 __clk_get_name(mclk); 1330 struct clk *clk = NULL; 1331 1332 switch (d->type) { 1333 case K_FFC: 1334 clk = clk_register_fixed_factor(NULL, d->name, 1335 parent_name, 0, 1336 d->mul, d->div); 1337 break; 1338 case K_GATE: 1339 clk = r9a06g032_register_gate(clocks, parent_name, d); 1340 break; 1341 case K_DIV: 1342 clk = r9a06g032_register_div(clocks, parent_name, d); 1343 break; 1344 case K_BITSEL: 1345 /* keep that selector register around */ 1346 uart_group_sel[d->dual.group] = d->dual.sel; 1347 clk = r9a06g032_register_bitsel(clocks, parent_name, d); 1348 break; 1349 case K_DUALGATE: 1350 clk = r9a06g032_register_dualgate(clocks, parent_name, 1351 d, 1352 uart_group_sel[d->dual.group]); 1353 break; 1354 } 1355 clocks->data.clks[d->index] = clk; 1356 } 1357 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data); 1358 if (error) 1359 return error; 1360 1361 error = devm_add_action_or_reset(dev, 1362 r9a06g032_clocks_del_clk_provider, np); 1363 if (error) 1364 return error; 1365 1366 error = r9a06g032_add_clk_domain(dev); 1367 if (error) 1368 return error; 1369 1370 sysctrl_priv = clocks; 1371 1372 error = of_platform_populate(np, NULL, NULL, dev); 1373 if (error) 1374 dev_err(dev, "Failed to populate children (%d)\n", error); 1375 1376 return 0; 1377 } 1378 1379 static const struct of_device_id r9a06g032_match[] = { 1380 { .compatible = "renesas,r9a06g032-sysctrl" }, 1381 { } 1382 }; 1383 1384 static struct platform_driver r9a06g032_clock_driver = { 1385 .driver = { 1386 .name = "renesas,r9a06g032-sysctrl", 1387 .of_match_table = r9a06g032_match, 1388 }, 1389 }; 1390 1391 static int __init r9a06g032_clocks_init(void) 1392 { 1393 return platform_driver_probe(&r9a06g032_clock_driver, 1394 r9a06g032_clocks_probe); 1395 } 1396 1397 subsys_initcall(r9a06g032_clocks_init); 1398