1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 * 7 * Based on r8a779g0-cpg-mssr.c 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/soc/renesas/rcar-rst.h> 17 18 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> 19 20 #include "renesas-cpg-mssr.h" 21 #include "rcar-gen4-cpg.h" 22 23 enum clk_ids { 24 /* Core Clock Outputs exported to DT */ 25 LAST_DT_CORE_CLK = R8A779H0_CLK_R, 26 27 /* External Input Clocks */ 28 CLK_EXTAL, 29 CLK_EXTALR, 30 31 /* Internal Core Clocks */ 32 CLK_MAIN, 33 CLK_PLL1, 34 CLK_PLL2, 35 CLK_PLL3, 36 CLK_PLL4, 37 CLK_PLL5, 38 CLK_PLL6, 39 CLK_PLL1_DIV2, 40 CLK_PLL2_DIV2, 41 CLK_PLL3_DIV2, 42 CLK_PLL4_DIV2, 43 CLK_PLL4_DIV5, 44 CLK_PLL5_DIV2, 45 CLK_PLL5_DIV4, 46 CLK_PLL6_DIV2, 47 CLK_S0, 48 CLK_S0_VIO, 49 CLK_S0_VC, 50 CLK_S0_HSC, 51 CLK_SASYNCPER, 52 CLK_SV_VIP, 53 CLK_SV_IR, 54 CLK_IMPASRC, 55 CLK_IMPBSRC, 56 CLK_VIOSRC, 57 CLK_VCSRC, 58 CLK_SDSRC, 59 CLK_RPCSRC, 60 CLK_OCO, 61 62 /* Module Clocks */ 63 MOD_CLK_BASE 64 }; 65 66 static const struct cpg_core_clk r8a779h0_core_clks[] = { 67 /* External Clock Inputs */ 68 DEF_INPUT("extal", CLK_EXTAL), 69 DEF_INPUT("extalr", CLK_EXTALR), 70 71 /* Internal Core Clocks */ 72 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), 73 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), 74 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), 75 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), 76 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), 77 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), 78 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), 79 80 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 81 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), 82 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), 83 DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), 84 DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), 85 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 86 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 87 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), 88 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 89 DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1), 90 DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1), 91 DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1), 92 DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), 93 DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1), 94 DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1), 95 DEF_FIXED(".impasrc", CLK_IMPASRC, CLK_PLL1_DIV2, 2, 1), 96 DEF_FIXED(".impbsrc", CLK_IMPBSRC, CLK_PLL1, 4, 1), 97 DEF_FIXED(".viosrc", CLK_VIOSRC, CLK_PLL1, 6, 1), 98 DEF_FIXED(".vcsrc", CLK_VCSRC, CLK_PLL1, 6, 1), 99 DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), 100 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), 101 DEF_RATE(".oco", CLK_OCO, 32768), 102 103 /* Core Clock Outputs */ 104 DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), 105 DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), 106 DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), 107 DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), 108 DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), 109 DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), 110 DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), 111 DEF_FIXED("cl16m", R8A779H0_CLK_CL16M, CLK_S0, 48, 1), 112 DEF_FIXED("s0d2_rt", R8A779H0_CLK_S0D2_RT, CLK_S0, 2, 1), 113 DEF_FIXED("s0d3_rt", R8A779H0_CLK_S0D3_RT, CLK_S0, 3, 1), 114 DEF_FIXED("s0d4_rt", R8A779H0_CLK_S0D4_RT, CLK_S0, 4, 1), 115 DEF_FIXED("s0d6_rt", R8A779H0_CLK_S0D6_RT, CLK_S0, 6, 1), 116 DEF_FIXED("cl16m_rt", R8A779H0_CLK_CL16M_RT, CLK_S0, 48, 1), 117 DEF_FIXED("s0d2_per", R8A779H0_CLK_S0D2_PER, CLK_S0, 2, 1), 118 DEF_FIXED("s0d3_per", R8A779H0_CLK_S0D3_PER, CLK_S0, 3, 1), 119 DEF_FIXED("s0d4_per", R8A779H0_CLK_S0D4_PER, CLK_S0, 4, 1), 120 DEF_FIXED("s0d6_per", R8A779H0_CLK_S0D6_PER, CLK_S0, 6, 1), 121 DEF_FIXED("s0d12_per", R8A779H0_CLK_S0D12_PER, CLK_S0, 12, 1), 122 DEF_FIXED("s0d24_per", R8A779H0_CLK_S0D24_PER, CLK_S0, 24, 1), 123 DEF_FIXED("cl16m_per", R8A779H0_CLK_CL16M_PER, CLK_S0, 48, 1), 124 DEF_FIXED("s0d2_mm", R8A779H0_CLK_S0D2_MM, CLK_S0, 2, 1), 125 DEF_FIXED("s0d4_mm", R8A779H0_CLK_S0D4_MM, CLK_S0, 4, 1), 126 DEF_FIXED("cl16m_mm", R8A779H0_CLK_CL16M_MM, CLK_S0, 48, 1), 127 DEF_FIXED("s0d2_u3dg", R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2, 1), 128 DEF_FIXED("s0d4_u3dg", R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4, 1), 129 DEF_FIXED("s0d1_vio", R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1), 130 DEF_FIXED("s0d2_vio", R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1), 131 DEF_FIXED("s0d4_vio", R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1), 132 DEF_FIXED("s0d8_vio", R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1), 133 DEF_FIXED("s0d1_vc", R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1, 1), 134 DEF_FIXED("s0d2_vc", R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2, 1), 135 DEF_FIXED("s0d4_vc", R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4, 1), 136 DEF_FIXED("s0d1_hsc", R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1), 137 DEF_FIXED("s0d2_hsc", R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1), 138 DEF_FIXED("s0d4_hsc", R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1), 139 DEF_FIXED("s0d8_hsc", R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8, 1), 140 DEF_FIXED("cl16m_hsc", R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1), 141 DEF_FIXED("sasyncrt", R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), 142 DEF_FIXED("sasyncperd1", R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1, 1), 143 DEF_FIXED("sasyncperd2", R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2, 1), 144 DEF_FIXED("sasyncperd4", R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4, 1), 145 DEF_FIXED("svd1_vip", R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1), 146 DEF_FIXED("svd2_vip", R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1), 147 DEF_FIXED("svd1_ir", R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1, 1), 148 DEF_FIXED("svd2_ir", R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2, 1), 149 DEF_FIXED("cbfusa", R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 150 DEF_FIXED("cpex", R8A779H0_CLK_CPEX, CLK_EXTAL, 2, 1), 151 DEF_FIXED("cp", R8A779H0_CLK_CP, CLK_EXTAL, 2, 1), 152 DEF_FIXED("impad1", R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1, 1), 153 DEF_FIXED("impad4", R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4, 1), 154 DEF_FIXED("impb", R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1, 1), 155 DEF_FIXED("viobusd1", R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1, 1), 156 DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1), 157 DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1), 158 DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1), 159 DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 160 DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880), 161 DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), 162 DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), 163 DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 164 165 DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870), 166 DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870), 167 168 DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), 169 DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC), 170 171 DEF_GEN4_OSC("osc", R8A779H0_CLK_OSC, CLK_EXTAL, 8), 172 DEF_GEN4_MDSEL("r", R8A779H0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 173 }; 174 175 static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 176 DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), 177 DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), 178 DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), 179 DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), 180 DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), 181 DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), 182 DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1), 183 DEF_MOD("i2c0", 518, R8A779H0_CLK_S0D6_PER), 184 DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), 185 DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), 186 DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), 187 DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M), 188 DEF_MOD("msi0", 618, R8A779H0_CLK_MSO), 189 DEF_MOD("msi1", 619, R8A779H0_CLK_MSO), 190 DEF_MOD("msi2", 620, R8A779H0_CLK_MSO), 191 DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), 192 DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), 193 DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), 194 DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), 195 DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), 196 DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4), 197 DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4), 198 DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4), 199 DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), 200 DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), 201 DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER), 202 DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT), 203 DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2), 204 DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2), 205 DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2), 206 DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2), 207 DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), 208 DEF_MOD("cmt0", 910, R8A779H0_CLK_R), 209 DEF_MOD("cmt1", 911, R8A779H0_CLK_R), 210 DEF_MOD("cmt2", 912, R8A779H0_CLK_R), 211 DEF_MOD("cmt3", 913, R8A779H0_CLK_R), 212 DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), 213 DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), 214 DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), 215 DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), 216 }; 217 218 /* 219 * CPG Clock Data 220 */ 221 /* 222 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC 223 * 14 13 (MHz) 224 * ------------------------------------------------------------------------ 225 * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16 226 * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19 227 * 1 0 Prohibited setting 228 * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32 229 */ 230 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 231 (((md) & BIT(13)) >> 13)) 232 233 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { 234 /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ 235 { 1, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 16, }, 236 { 1, 160, 1, 200, 1, 160, 1, 200, 1, 160, 1, 140, 1, 19, }, 237 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 238 { 2, 192, 1, 240, 1, 192, 1, 240, 1, 192, 1, 168, 1, 32, }, 239 }; 240 241 static int __init r8a779h0_cpg_mssr_init(struct device *dev) 242 { 243 const struct rcar_gen4_cpg_pll_config *cpg_pll_config; 244 u32 cpg_mode; 245 int error; 246 247 error = rcar_rst_read_mode_pins(&cpg_mode); 248 if (error) 249 return error; 250 251 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 252 if (!cpg_pll_config->extal_div) { 253 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 254 return -EINVAL; 255 } 256 257 return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 258 } 259 260 const struct cpg_mssr_info r8a779h0_cpg_mssr_info __initconst = { 261 /* Core Clocks */ 262 .core_clks = r8a779h0_core_clks, 263 .num_core_clks = ARRAY_SIZE(r8a779h0_core_clks), 264 .last_dt_core_clk = LAST_DT_CORE_CLK, 265 .num_total_core_clks = MOD_CLK_BASE, 266 267 /* Module Clocks */ 268 .mod_clks = r8a779h0_mod_clks, 269 .num_mod_clks = ARRAY_SIZE(r8a779h0_mod_clks), 270 .num_hw_mod_clks = 30 * 32, 271 272 /* Callbacks */ 273 .init = r8a779h0_cpg_mssr_init, 274 .cpg_clk_register = rcar_gen4_cpg_clk_register, 275 276 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, 277 }; 278