1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/pm.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/rcar-rst.h> 25 26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28 #include "renesas-cpg-mssr.h" 29 #include "rcar-gen3-cpg.h" 30 31 enum rcar_r8a779a0_clk_types { 32 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 33 CLK_TYPE_R8A779A0_PLL1, 34 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 35 CLK_TYPE_R8A779A0_PLL5, 36 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 37 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 38 }; 39 40 struct rcar_r8a779a0_cpg_pll_config { 41 u8 extal_div; 42 u8 pll1_mult; 43 u8 pll1_div; 44 u8 pll5_mult; 45 u8 pll5_div; 46 u8 osc_prediv; 47 }; 48 49 enum clk_ids { 50 /* Core Clock Outputs exported to DT */ 51 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 52 53 /* External Input Clocks */ 54 CLK_EXTAL, 55 CLK_EXTALR, 56 57 /* Internal Core Clocks */ 58 CLK_MAIN, 59 CLK_PLL1, 60 CLK_PLL20, 61 CLK_PLL21, 62 CLK_PLL30, 63 CLK_PLL31, 64 CLK_PLL5, 65 CLK_PLL1_DIV2, 66 CLK_PLL20_DIV2, 67 CLK_PLL21_DIV2, 68 CLK_PLL30_DIV2, 69 CLK_PLL31_DIV2, 70 CLK_PLL5_DIV2, 71 CLK_PLL5_DIV4, 72 CLK_S1, 73 CLK_S2, 74 CLK_S3, 75 CLK_SDSRC, 76 CLK_RPCSRC, 77 CLK_OCO, 78 79 /* Module Clocks */ 80 MOD_CLK_BASE 81 }; 82 83 #define DEF_PLL(_name, _id, _offset) \ 84 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 85 .offset = _offset) 86 87 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 88 /* External Clock Inputs */ 89 DEF_INPUT("extal", CLK_EXTAL), 90 DEF_INPUT("extalr", CLK_EXTALR), 91 92 /* Internal Core Clocks */ 93 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 94 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 95 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 96 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 97 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 98 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 99 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 100 101 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 102 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 103 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 104 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 105 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 106 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 107 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 108 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 109 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 110 DEF_RATE(".oco", CLK_OCO, 32768), 111 112 /* Core Clock Outputs */ 113 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 114 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 115 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 116 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 117 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 118 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 119 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 120 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 121 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 122 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 123 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 124 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 125 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 126 DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), 127 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 128 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 129 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 130 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 131 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 132 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 133 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1), 134 135 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 136 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 137 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 138 139 DEF_GEN3_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 140 DEF_GEN3_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 141 }; 142 143 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 144 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 145 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 146 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 147 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 148 }; 149 150 static spinlock_t cpg_lock; 151 152 static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 153 static unsigned int cpg_clk_extalr __initdata; 154 static u32 cpg_mode __initdata; 155 156 struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 157 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 158 struct clk **clks, void __iomem *base, 159 struct raw_notifier_head *notifiers) 160 { 161 const struct clk *parent; 162 unsigned int mult = 1; 163 unsigned int div = 1; 164 u32 value; 165 166 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 167 if (IS_ERR(parent)) 168 return ERR_CAST(parent); 169 170 switch (core->type) { 171 case CLK_TYPE_R8A779A0_MAIN: 172 div = cpg_pll_config->extal_div; 173 break; 174 175 case CLK_TYPE_R8A779A0_PLL1: 176 mult = cpg_pll_config->pll1_mult; 177 div = cpg_pll_config->pll1_div; 178 break; 179 180 case CLK_TYPE_R8A779A0_PLL2X_3X: 181 value = readl(base + core->offset); 182 mult = (((value >> 24) & 0x7f) + 1) * 2; 183 break; 184 185 case CLK_TYPE_R8A779A0_PLL5: 186 mult = cpg_pll_config->pll5_mult; 187 div = cpg_pll_config->pll5_div; 188 break; 189 190 case CLK_TYPE_R8A779A0_MDSEL: 191 /* 192 * Clock selectable between two parents and two fixed dividers 193 * using a mode pin 194 */ 195 if (cpg_mode & BIT(core->offset)) { 196 div = core->div & 0xffff; 197 } else { 198 parent = clks[core->parent >> 16]; 199 if (IS_ERR(parent)) 200 return ERR_CAST(parent); 201 div = core->div >> 16; 202 } 203 mult = 1; 204 break; 205 206 case CLK_TYPE_R8A779A0_OSC: 207 /* 208 * Clock combining OSC EXTAL predivider and a fixed divider 209 */ 210 div = cpg_pll_config->osc_prediv * core->div; 211 break; 212 213 default: 214 return ERR_PTR(-EINVAL); 215 } 216 217 return clk_register_fixed_factor(NULL, core->name, 218 __clk_get_name(parent), 0, mult, div); 219 } 220 221 /* 222 * CPG Clock Data 223 */ 224 /* 225 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 226 * 14 13 (MHz) 21 31 227 * -------------------------------------------------------- 228 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 229 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 230 * 1 0 Prohibited setting 231 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 232 */ 233 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 234 (((md) & BIT(13)) >> 13)) 235 236 static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 237 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 238 { 1, 128, 1, 192, 1, 16, }, 239 { 1, 106, 1, 160, 1, 19, }, 240 { 0, 0, 0, 0, 0, 0, }, 241 { 2, 128, 1, 192, 1, 32, }, 242 }; 243 244 static int __init r8a779a0_cpg_mssr_init(struct device *dev) 245 { 246 int error; 247 248 error = rcar_rst_read_mode_pins(&cpg_mode); 249 if (error) 250 return error; 251 252 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 253 cpg_clk_extalr = CLK_EXTALR; 254 spin_lock_init(&cpg_lock); 255 256 return 0; 257 } 258 259 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 260 /* Core Clocks */ 261 .core_clks = r8a779a0_core_clks, 262 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 263 .last_dt_core_clk = LAST_DT_CORE_CLK, 264 .num_total_core_clks = MOD_CLK_BASE, 265 266 /* Module Clocks */ 267 .mod_clks = r8a779a0_mod_clks, 268 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 269 .num_hw_mod_clks = 15 * 32, 270 271 /* Callbacks */ 272 .init = r8a779a0_cpg_mssr_init, 273 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 274 275 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 276 }; 277