1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 * 7 * Based on r8a7795-cpg-mssr.c 8 * 9 * Copyright (C) 2015 Glider bvba 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/pm.h> 23 #include <linux/slab.h> 24 #include <linux/soc/renesas/rcar-rst.h> 25 26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 27 28 #include "renesas-cpg-mssr.h" 29 30 enum rcar_r8a779a0_clk_types { 31 CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM, 32 CLK_TYPE_R8A779A0_PLL1, 33 CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ 34 CLK_TYPE_R8A779A0_PLL5, 35 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ 36 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ 37 }; 38 39 struct rcar_r8a779a0_cpg_pll_config { 40 u8 extal_div; 41 u8 pll1_mult; 42 u8 pll1_div; 43 u8 pll5_mult; 44 u8 pll5_div; 45 u8 osc_prediv; 46 }; 47 48 enum clk_ids { 49 /* Core Clock Outputs exported to DT */ 50 LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, 51 52 /* External Input Clocks */ 53 CLK_EXTAL, 54 CLK_EXTALR, 55 56 /* Internal Core Clocks */ 57 CLK_MAIN, 58 CLK_PLL1, 59 CLK_PLL20, 60 CLK_PLL21, 61 CLK_PLL30, 62 CLK_PLL31, 63 CLK_PLL5, 64 CLK_PLL1_DIV2, 65 CLK_PLL20_DIV2, 66 CLK_PLL21_DIV2, 67 CLK_PLL30_DIV2, 68 CLK_PLL31_DIV2, 69 CLK_PLL5_DIV2, 70 CLK_PLL5_DIV4, 71 CLK_S1, 72 CLK_S2, 73 CLK_S3, 74 CLK_SDSRC, 75 CLK_RPCSRC, 76 CLK_OCO, 77 78 /* Module Clocks */ 79 MOD_CLK_BASE 80 }; 81 82 #define DEF_PLL(_name, _id, _offset) \ 83 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ 84 .offset = _offset) 85 86 #define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 87 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ 88 (_parent0) << 16 | (_parent1), \ 89 .div = (_div0) << 16 | (_div1), .offset = _md) 90 91 #define DEF_OSC(_name, _id, _parent, _div) \ 92 DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) 93 94 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 95 /* External Clock Inputs */ 96 DEF_INPUT("extal", CLK_EXTAL), 97 DEF_INPUT("extalr", CLK_EXTALR), 98 99 /* Internal Core Clocks */ 100 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), 101 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), 102 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), 103 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 104 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 105 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 106 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 107 108 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 109 DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), 110 DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1), 111 DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1), 112 DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1), 113 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), 114 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), 115 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), 116 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), 117 DEF_RATE(".oco", CLK_OCO, 32768), 118 119 /* Core Clock Outputs */ 120 DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), 121 DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), 122 DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), 123 DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1), 124 DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1), 125 DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1), 126 DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1), 127 DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1), 128 DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1), 129 DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), 130 DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), 131 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), 132 DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), 133 DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), 134 DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), 135 DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), 136 DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), 137 DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), 138 DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), 139 DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), 140 DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1), 141 142 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 143 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 144 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), 145 146 DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), 147 DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 148 }; 149 150 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 151 DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), 152 DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), 153 DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), 154 DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), 155 DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), 156 DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), 157 DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), 158 DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8), 159 DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), 160 DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), 161 DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), 162 DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1), 163 DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1), 164 DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1), 165 DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1), 166 DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1), 167 DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1), 168 DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1), 169 DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1), 170 DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1), 171 DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1), 172 DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1), 173 DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1), 174 DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1), 175 DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1), 176 DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1), 177 DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1), 178 DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1), 179 DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1), 180 DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1), 181 DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1), 182 DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1), 183 DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1), 184 DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1), 185 DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1), 186 DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1), 187 DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1), 188 DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), 189 DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), 190 DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), 191 }; 192 193 static spinlock_t cpg_lock; 194 195 static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata; 196 static unsigned int cpg_clk_extalr __initdata; 197 static u32 cpg_mode __initdata; 198 199 static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, 200 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 201 struct clk **clks, void __iomem *base, 202 struct raw_notifier_head *notifiers) 203 { 204 const struct clk *parent; 205 unsigned int mult = 1; 206 unsigned int div = 1; 207 u32 value; 208 209 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 210 if (IS_ERR(parent)) 211 return ERR_CAST(parent); 212 213 switch (core->type) { 214 case CLK_TYPE_R8A779A0_MAIN: 215 div = cpg_pll_config->extal_div; 216 break; 217 218 case CLK_TYPE_R8A779A0_PLL1: 219 mult = cpg_pll_config->pll1_mult; 220 div = cpg_pll_config->pll1_div; 221 break; 222 223 case CLK_TYPE_R8A779A0_PLL2X_3X: 224 value = readl(base + core->offset); 225 mult = (((value >> 24) & 0x7f) + 1) * 2; 226 break; 227 228 case CLK_TYPE_R8A779A0_PLL5: 229 mult = cpg_pll_config->pll5_mult; 230 div = cpg_pll_config->pll5_div; 231 break; 232 233 case CLK_TYPE_R8A779A0_MDSEL: 234 /* 235 * Clock selectable between two parents and two fixed dividers 236 * using a mode pin 237 */ 238 if (cpg_mode & BIT(core->offset)) { 239 div = core->div & 0xffff; 240 } else { 241 parent = clks[core->parent >> 16]; 242 if (IS_ERR(parent)) 243 return ERR_CAST(parent); 244 div = core->div >> 16; 245 } 246 mult = 1; 247 break; 248 249 case CLK_TYPE_R8A779A0_OSC: 250 /* 251 * Clock combining OSC EXTAL predivider and a fixed divider 252 */ 253 div = cpg_pll_config->osc_prediv * core->div; 254 break; 255 256 default: 257 return ERR_PTR(-EINVAL); 258 } 259 260 return clk_register_fixed_factor(NULL, core->name, 261 __clk_get_name(parent), 0, mult, div); 262 } 263 264 /* 265 * CPG Clock Data 266 */ 267 /* 268 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC 269 * 14 13 (MHz) 21 31 270 * -------------------------------------------------------- 271 * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 272 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 273 * 1 0 Prohibited setting 274 * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 275 */ 276 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 277 (((md) & BIT(13)) >> 13)) 278 279 static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = { 280 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 281 { 1, 128, 1, 192, 1, 16, }, 282 { 1, 106, 1, 160, 1, 19, }, 283 { 0, 0, 0, 0, 0, 0, }, 284 { 2, 128, 1, 192, 1, 32, }, 285 }; 286 287 static int __init r8a779a0_cpg_mssr_init(struct device *dev) 288 { 289 int error; 290 291 error = rcar_rst_read_mode_pins(&cpg_mode); 292 if (error) 293 return error; 294 295 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 296 cpg_clk_extalr = CLK_EXTALR; 297 spin_lock_init(&cpg_lock); 298 299 return 0; 300 } 301 302 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { 303 /* Core Clocks */ 304 .core_clks = r8a779a0_core_clks, 305 .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), 306 .last_dt_core_clk = LAST_DT_CORE_CLK, 307 .num_total_core_clks = MOD_CLK_BASE, 308 309 /* Module Clocks */ 310 .mod_clks = r8a779a0_mod_clks, 311 .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), 312 .num_hw_mod_clks = 15 * 32, 313 314 /* Callbacks */ 315 .init = r8a779a0_cpg_mssr_init, 316 .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, 317 318 .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, 319 }; 320