1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * r8a77980 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 * 8 * Based on r8a7795-cpg-mssr.c 9 * 10 * Copyright (C) 2015 Glider bvba 11 */ 12 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/soc/renesas/rcar-rst.h> 17 #include <linux/sys_soc.h> 18 19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h> 20 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen3-cpg.h" 23 24 enum clk_ids { 25 /* Core Clock Outputs exported to DT */ 26 LAST_DT_CORE_CLK = R8A77980_CLK_OSC, 27 28 /* External Input Clocks */ 29 CLK_EXTAL, 30 CLK_EXTALR, 31 32 /* Internal Core Clocks */ 33 CLK_MAIN, 34 CLK_PLL1, 35 CLK_PLL2, 36 CLK_PLL3, 37 CLK_PLL1_DIV2, 38 CLK_PLL1_DIV4, 39 CLK_S0, 40 CLK_S1, 41 CLK_S2, 42 CLK_S3, 43 CLK_SDSRC, 44 CLK_RPCSRC, 45 CLK_OCO, 46 47 /* Module Clocks */ 48 MOD_CLK_BASE 49 }; 50 51 static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { 52 /* External Clock Inputs */ 53 DEF_INPUT("extal", CLK_EXTAL), 54 DEF_INPUT("extalr", CLK_EXTALR), 55 56 /* Internal Core Clocks */ 57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 61 62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 63 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 64 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 65 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 66 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 67 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 68 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 69 70 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), 71 72 DEF_RATE(".oco", CLK_OCO, 32768), 73 74 /* Core Clock Outputs */ 75 DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1), 76 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 77 DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 78 DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 79 DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 80 DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1), 81 DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1), 82 DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1), 83 DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1), 84 DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1), 85 DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1), 86 DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1), 87 DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1), 88 DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1), 89 DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1), 90 DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1), 91 DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1), 92 DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1), 93 DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1), 94 DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1), 95 DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1), 96 97 DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074), 98 DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074), 99 100 DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), 101 DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC), 102 103 DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), 104 DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), 105 DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1), 106 107 DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 108 DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 109 DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), 110 111 DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8), 112 DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), 113 }; 114 115 static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { 116 DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6), 117 DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6), 118 DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6), 119 DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6), 120 DEF_MOD("tmu0", 125, R8A77980_CLK_CP), 121 DEF_MOD("scif4", 203, R8A77980_CLK_S3D4), 122 DEF_MOD("scif3", 204, R8A77980_CLK_S3D4), 123 DEF_MOD("scif1", 206, R8A77980_CLK_S3D4), 124 DEF_MOD("scif0", 207, R8A77980_CLK_S3D4), 125 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO), 126 DEF_MOD("msiof2", 209, R8A77980_CLK_MSO), 127 DEF_MOD("msiof1", 210, R8A77980_CLK_MSO), 128 DEF_MOD("msiof0", 211, R8A77980_CLK_MSO), 129 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3), 130 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3), 131 DEF_MOD("cmt3", 300, R8A77980_CLK_R), 132 DEF_MOD("cmt2", 301, R8A77980_CLK_R), 133 DEF_MOD("cmt1", 302, R8A77980_CLK_R), 134 DEF_MOD("cmt0", 303, R8A77980_CLK_R), 135 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), 136 DEF_MOD("sdif", 314, R8A77980_CLK_SD0), 137 DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2), 138 DEF_MOD("rwdt", 402, R8A77980_CLK_R), 139 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), 140 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), 141 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), 142 DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1), 143 DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1), 144 DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1), 145 DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), 146 DEF_MOD("thermal", 522, R8A77980_CLK_CP), 147 DEF_MOD("pwm", 523, R8A77980_CLK_S0D12), 148 DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1), 149 DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1), 150 DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1), 151 DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1), 152 DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1), 153 DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1), 154 DEF_MOD("vin15", 604, R8A77980_CLK_S2D1), 155 DEF_MOD("vin14", 605, R8A77980_CLK_S2D1), 156 DEF_MOD("vin13", 608, R8A77980_CLK_S2D1), 157 DEF_MOD("vin12", 612, R8A77980_CLK_S2D1), 158 DEF_MOD("vin11", 618, R8A77980_CLK_S2D1), 159 DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1), 160 DEF_MOD("vin10", 625, R8A77980_CLK_S2D1), 161 DEF_MOD("vin9", 627, R8A77980_CLK_S2D1), 162 DEF_MOD("vin8", 628, R8A77980_CLK_S2D1), 163 DEF_MOD("csi41", 715, R8A77980_CLK_CSI0), 164 DEF_MOD("csi40", 716, R8A77980_CLK_CSI0), 165 DEF_MOD("du0", 724, R8A77980_CLK_S2D1), 166 DEF_MOD("lvds", 727, R8A77980_CLK_S2D1), 167 DEF_MOD("vin7", 804, R8A77980_CLK_S2D1), 168 DEF_MOD("vin6", 805, R8A77980_CLK_S2D1), 169 DEF_MOD("vin5", 806, R8A77980_CLK_S2D1), 170 DEF_MOD("vin4", 807, R8A77980_CLK_S2D1), 171 DEF_MOD("vin3", 808, R8A77980_CLK_S2D1), 172 DEF_MOD("vin2", 809, R8A77980_CLK_S2D1), 173 DEF_MOD("vin1", 810, R8A77980_CLK_S2D1), 174 DEF_MOD("vin0", 811, R8A77980_CLK_S2D1), 175 DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2), 176 DEF_MOD("gether", 813, R8A77980_CLK_S3D2), 177 DEF_MOD("imp3", 824, R8A77980_CLK_S1D1), 178 DEF_MOD("imp2", 825, R8A77980_CLK_S1D1), 179 DEF_MOD("imp1", 826, R8A77980_CLK_S1D1), 180 DEF_MOD("imp0", 827, R8A77980_CLK_S1D1), 181 DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1), 182 DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1), 183 DEF_MOD("impram", 830, R8A77980_CLK_S1D1), 184 DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1), 185 DEF_MOD("gpio5", 907, R8A77980_CLK_CP), 186 DEF_MOD("gpio4", 908, R8A77980_CLK_CP), 187 DEF_MOD("gpio3", 909, R8A77980_CLK_CP), 188 DEF_MOD("gpio2", 910, R8A77980_CLK_CP), 189 DEF_MOD("gpio1", 911, R8A77980_CLK_CP), 190 DEF_MOD("gpio0", 912, R8A77980_CLK_CP), 191 DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), 192 DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2), 193 DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6), 194 DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), 195 DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), 196 DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), 197 DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2), 198 DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2), 199 }; 200 201 static const unsigned int r8a77980_crit_mod_clks[] __initconst = { 202 MOD_CLK_ID(402), /* RWDT */ 203 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 204 }; 205 206 /* 207 * CPG Clock Data 208 */ 209 210 /* 211 * MD EXTAL PLL2 PLL1 PLL3 OSC 212 * 14 13 (MHz) 213 * -------------------------------------------------------- 214 * 0 0 16.66 x 1 x240 x192 x192 /16 215 * 0 1 20 x 1 x200 x160 x160 /19 216 * 1 0 27 x 1 x148 x118 x118 /26 217 * 1 1 33.33 / 2 x240 x192 x192 /32 218 */ 219 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 220 (((md) & BIT(13)) >> 13)) 221 222 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { 223 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ 224 { 1, 192, 1, 192, 1, 16, }, 225 { 1, 160, 1, 160, 1, 19, }, 226 { 1, 118, 1, 118, 1, 26, }, 227 { 2, 192, 1, 192, 1, 32, }, 228 }; 229 230 static int __init r8a77980_cpg_mssr_init(struct device *dev) 231 { 232 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 233 u32 cpg_mode; 234 int error; 235 236 error = rcar_rst_read_mode_pins(&cpg_mode); 237 if (error) 238 return error; 239 240 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 241 242 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 243 } 244 245 const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = { 246 /* Core Clocks */ 247 .core_clks = r8a77980_core_clks, 248 .num_core_clks = ARRAY_SIZE(r8a77980_core_clks), 249 .last_dt_core_clk = LAST_DT_CORE_CLK, 250 .num_total_core_clks = MOD_CLK_BASE, 251 252 /* Module Clocks */ 253 .mod_clks = r8a77980_mod_clks, 254 .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks), 255 .num_hw_mod_clks = 12 * 32, 256 257 /* Critical Module Clocks */ 258 .crit_mod_clks = r8a77980_crit_mod_clks, 259 .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks), 260 261 /* Callbacks */ 262 .init = r8a77980_cpg_mssr_init, 263 .cpg_clk_register = rcar_gen3_cpg_clk_register, 264 }; 265