1 /* 2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2015 Glider bvba 5 * 6 * Based on clk-rcar-gen3.c 7 * 8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 */ 14 15 #include <linux/bug.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/of.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 26 27 #include "renesas-cpg-mssr.h" 28 29 30 enum clk_ids { 31 /* Core Clock Outputs exported to DT */ 32 LAST_DT_CORE_CLK = R8A7795_CLK_OSC, 33 34 /* External Input Clocks */ 35 CLK_EXTAL, 36 CLK_EXTALR, 37 38 /* Internal Core Clocks */ 39 CLK_MAIN, 40 CLK_PLL0, 41 CLK_PLL1, 42 CLK_PLL2, 43 CLK_PLL3, 44 CLK_PLL4, 45 CLK_PLL1_DIV2, 46 CLK_PLL1_DIV4, 47 CLK_S0, 48 CLK_S1, 49 CLK_S2, 50 CLK_S3, 51 CLK_SDSRC, 52 CLK_SSPSRC, 53 54 /* Module Clocks */ 55 MOD_CLK_BASE 56 }; 57 58 enum r8a7795_clk_types { 59 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 60 CLK_TYPE_GEN3_PLL0, 61 CLK_TYPE_GEN3_PLL1, 62 CLK_TYPE_GEN3_PLL2, 63 CLK_TYPE_GEN3_PLL3, 64 CLK_TYPE_GEN3_PLL4, 65 CLK_TYPE_GEN3_SD, 66 }; 67 68 static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 69 /* External Clock Inputs */ 70 DEF_INPUT("extal", CLK_EXTAL), 71 DEF_INPUT("extalr", CLK_EXTALR), 72 73 /* Internal Core Clocks */ 74 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 75 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 76 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 77 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 78 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 79 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 80 81 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 82 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 83 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 84 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 85 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 86 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 87 88 /* Core Clock Outputs */ 89 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 90 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 91 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 92 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 93 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 94 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 95 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 96 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 97 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 98 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 99 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 100 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 101 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 102 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 103 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 104 105 DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074), 106 DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078), 107 DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268), 108 DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c), 109 110 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 111 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 112 113 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 114 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), 115 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 116 }; 117 118 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 119 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 120 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 121 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 122 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 123 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 124 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 125 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 126 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 127 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 128 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), 129 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), 130 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), 131 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 132 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 133 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 134 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 135 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 136 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 137 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 138 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), 139 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 140 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 141 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 142 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 143 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 144 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), 145 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), 146 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 147 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 148 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 149 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 150 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 151 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), 152 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), 153 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), 154 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), 155 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), 156 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), 157 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), 158 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), 159 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), 160 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), 161 DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), 162 DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), 163 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), 164 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), 165 DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), 166 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), 167 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), 168 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), 169 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1), 170 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1), 171 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1), 172 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), 173 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1), 174 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1), 175 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 176 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 177 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 178 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 179 DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 180 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 181 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 182 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 183 DEF_MOD("lvds", 727, R8A7795_CLK_S2D1), 184 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 185 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 186 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), 187 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 188 DEF_MOD("gpio7", 905, R8A7795_CLK_CP), 189 DEF_MOD("gpio6", 906, R8A7795_CLK_CP), 190 DEF_MOD("gpio5", 907, R8A7795_CLK_CP), 191 DEF_MOD("gpio4", 908, R8A7795_CLK_CP), 192 DEF_MOD("gpio3", 909, R8A7795_CLK_CP), 193 DEF_MOD("gpio2", 910, R8A7795_CLK_CP), 194 DEF_MOD("gpio1", 911, R8A7795_CLK_CP), 195 DEF_MOD("gpio0", 912, R8A7795_CLK_CP), 196 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 197 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 198 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 199 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), 200 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2), 201 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2), 202 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2), 203 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 204 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 205 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 206 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 207 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 208 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 209 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 210 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 211 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 212 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 213 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 214 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 215 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 216 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 217 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 218 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 219 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 220 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 221 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 222 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 223 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 224 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 225 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 226 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 227 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 228 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 229 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 230 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 231 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 232 }; 233 234 static const unsigned int r8a7795_crit_mod_clks[] __initconst = { 235 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 236 }; 237 238 /* ----------------------------------------------------------------------------- 239 * SDn Clock 240 * 241 */ 242 #define CPG_SD_STP_HCK BIT(9) 243 #define CPG_SD_STP_CK BIT(8) 244 245 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) 246 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) 247 248 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ 249 { \ 250 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ 251 ((stp_ck) ? CPG_SD_STP_CK : 0) | \ 252 ((sd_srcfc) << 2) | \ 253 ((sd_fc) << 0), \ 254 .div = (sd_div), \ 255 } 256 257 struct sd_div_table { 258 u32 val; 259 unsigned int div; 260 }; 261 262 struct sd_clock { 263 struct clk_hw hw; 264 void __iomem *reg; 265 const struct sd_div_table *div_table; 266 unsigned int div_num; 267 unsigned int div_min; 268 unsigned int div_max; 269 }; 270 271 /* SDn divider 272 * sd_srcfc sd_fc div 273 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc 274 *------------------------------------------------------------------- 275 * 0 0 0 (1) 1 (4) 4 276 * 0 0 1 (2) 1 (4) 8 277 * 1 0 2 (4) 1 (4) 16 278 * 1 0 3 (8) 1 (4) 32 279 * 1 0 4 (16) 1 (4) 64 280 * 0 0 0 (1) 0 (2) 2 281 * 0 0 1 (2) 0 (2) 4 282 * 1 0 2 (4) 0 (2) 8 283 * 1 0 3 (8) 0 (2) 16 284 * 1 0 4 (16) 0 (2) 32 285 */ 286 static const struct sd_div_table cpg_sd_div_table[] = { 287 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ 288 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), 289 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), 290 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), 291 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), 292 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), 293 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), 294 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), 295 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), 296 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), 297 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), 298 }; 299 300 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw) 301 302 static int cpg_sd_clock_enable(struct clk_hw *hw) 303 { 304 struct sd_clock *clock = to_sd_clock(hw); 305 u32 val, sd_fc; 306 unsigned int i; 307 308 val = clk_readl(clock->reg); 309 310 sd_fc = val & CPG_SD_FC_MASK; 311 for (i = 0; i < clock->div_num; i++) 312 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) 313 break; 314 315 if (i >= clock->div_num) 316 return -EINVAL; 317 318 val &= ~(CPG_SD_STP_MASK); 319 val |= clock->div_table[i].val & CPG_SD_STP_MASK; 320 321 clk_writel(val, clock->reg); 322 323 return 0; 324 } 325 326 static void cpg_sd_clock_disable(struct clk_hw *hw) 327 { 328 struct sd_clock *clock = to_sd_clock(hw); 329 330 clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg); 331 } 332 333 static int cpg_sd_clock_is_enabled(struct clk_hw *hw) 334 { 335 struct sd_clock *clock = to_sd_clock(hw); 336 337 return !(clk_readl(clock->reg) & CPG_SD_STP_MASK); 338 } 339 340 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, 341 unsigned long parent_rate) 342 { 343 struct sd_clock *clock = to_sd_clock(hw); 344 unsigned long rate = parent_rate; 345 u32 val, sd_fc; 346 unsigned int i; 347 348 val = clk_readl(clock->reg); 349 350 sd_fc = val & CPG_SD_FC_MASK; 351 for (i = 0; i < clock->div_num; i++) 352 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) 353 break; 354 355 if (i >= clock->div_num) 356 return -EINVAL; 357 358 return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div); 359 } 360 361 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, 362 unsigned long rate, 363 unsigned long parent_rate) 364 { 365 unsigned int div; 366 367 if (!rate) 368 rate = 1; 369 370 div = DIV_ROUND_CLOSEST(parent_rate, rate); 371 372 return clamp_t(unsigned int, div, clock->div_min, clock->div_max); 373 } 374 375 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, 376 unsigned long *parent_rate) 377 { 378 struct sd_clock *clock = to_sd_clock(hw); 379 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); 380 381 return DIV_ROUND_CLOSEST(*parent_rate, div); 382 } 383 384 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, 385 unsigned long parent_rate) 386 { 387 struct sd_clock *clock = to_sd_clock(hw); 388 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); 389 u32 val; 390 unsigned int i; 391 392 for (i = 0; i < clock->div_num; i++) 393 if (div == clock->div_table[i].div) 394 break; 395 396 if (i >= clock->div_num) 397 return -EINVAL; 398 399 val = clk_readl(clock->reg); 400 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); 401 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); 402 clk_writel(val, clock->reg); 403 404 return 0; 405 } 406 407 static const struct clk_ops cpg_sd_clock_ops = { 408 .enable = cpg_sd_clock_enable, 409 .disable = cpg_sd_clock_disable, 410 .is_enabled = cpg_sd_clock_is_enabled, 411 .recalc_rate = cpg_sd_clock_recalc_rate, 412 .round_rate = cpg_sd_clock_round_rate, 413 .set_rate = cpg_sd_clock_set_rate, 414 }; 415 416 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 417 void __iomem *base, 418 const char *parent_name) 419 { 420 struct clk_init_data init; 421 struct sd_clock *clock; 422 struct clk *clk; 423 unsigned int i; 424 425 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 426 if (!clock) 427 return ERR_PTR(-ENOMEM); 428 429 init.name = core->name; 430 init.ops = &cpg_sd_clock_ops; 431 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; 432 init.parent_names = &parent_name; 433 init.num_parents = 1; 434 435 clock->reg = base + core->offset; 436 clock->hw.init = &init; 437 clock->div_table = cpg_sd_div_table; 438 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 439 440 clock->div_max = clock->div_table[0].div; 441 clock->div_min = clock->div_max; 442 for (i = 1; i < clock->div_num; i++) { 443 clock->div_max = max(clock->div_max, clock->div_table[i].div); 444 clock->div_min = min(clock->div_min, clock->div_table[i].div); 445 } 446 447 clk = clk_register(NULL, &clock->hw); 448 if (IS_ERR(clk)) 449 kfree(clock); 450 451 return clk; 452 } 453 454 #define CPG_PLL0CR 0x00d8 455 #define CPG_PLL2CR 0x002c 456 #define CPG_PLL4CR 0x01f4 457 458 /* 459 * CPG Clock Data 460 */ 461 462 /* 463 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 464 * 14 13 19 17 (MHz) 465 *------------------------------------------------------------------- 466 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 467 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 468 * 0 0 1 0 Prohibited setting 469 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 470 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 471 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 472 * 0 1 1 0 Prohibited setting 473 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 474 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 475 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 476 * 1 0 1 0 Prohibited setting 477 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 478 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 479 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 480 * 1 1 1 0 Prohibited setting 481 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 482 */ 483 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 484 (((md) & BIT(13)) >> 11) | \ 485 (((md) & BIT(19)) >> 18) | \ 486 (((md) & BIT(17)) >> 17)) 487 488 struct cpg_pll_config { 489 unsigned int extal_div; 490 unsigned int pll1_mult; 491 unsigned int pll3_mult; 492 }; 493 494 static const struct cpg_pll_config cpg_pll_configs[16] __initconst = { 495 /* EXTAL div PLL1 mult PLL3 mult */ 496 { 1, 192, 192, }, 497 { 1, 192, 128, }, 498 { 0, /* Prohibited setting */ }, 499 { 1, 192, 192, }, 500 { 1, 160, 160, }, 501 { 1, 160, 106, }, 502 { 0, /* Prohibited setting */ }, 503 { 1, 160, 160, }, 504 { 1, 128, 128, }, 505 { 1, 128, 84, }, 506 { 0, /* Prohibited setting */ }, 507 { 1, 128, 128, }, 508 { 2, 192, 192, }, 509 { 2, 192, 128, }, 510 { 0, /* Prohibited setting */ }, 511 { 2, 192, 192, }, 512 }; 513 514 static const struct cpg_pll_config *cpg_pll_config __initdata; 515 516 static 517 struct clk * __init r8a7795_cpg_clk_register(struct device *dev, 518 const struct cpg_core_clk *core, 519 const struct cpg_mssr_info *info, 520 struct clk **clks, 521 void __iomem *base) 522 { 523 const struct clk *parent; 524 unsigned int mult = 1; 525 unsigned int div = 1; 526 u32 value; 527 528 parent = clks[core->parent]; 529 if (IS_ERR(parent)) 530 return ERR_CAST(parent); 531 532 switch (core->type) { 533 case CLK_TYPE_GEN3_MAIN: 534 div = cpg_pll_config->extal_div; 535 break; 536 537 case CLK_TYPE_GEN3_PLL0: 538 /* 539 * PLL0 is a configurable multiplier clock. Register it as a 540 * fixed factor clock for now as there's no generic multiplier 541 * clock implementation and we currently have no need to change 542 * the multiplier value. 543 */ 544 value = readl(base + CPG_PLL0CR); 545 mult = (((value >> 24) & 0x7f) + 1) * 2; 546 break; 547 548 case CLK_TYPE_GEN3_PLL1: 549 mult = cpg_pll_config->pll1_mult; 550 break; 551 552 case CLK_TYPE_GEN3_PLL2: 553 /* 554 * PLL2 is a configurable multiplier clock. Register it as a 555 * fixed factor clock for now as there's no generic multiplier 556 * clock implementation and we currently have no need to change 557 * the multiplier value. 558 */ 559 value = readl(base + CPG_PLL2CR); 560 mult = (((value >> 24) & 0x7f) + 1) * 2; 561 break; 562 563 case CLK_TYPE_GEN3_PLL3: 564 mult = cpg_pll_config->pll3_mult; 565 break; 566 567 case CLK_TYPE_GEN3_PLL4: 568 /* 569 * PLL4 is a configurable multiplier clock. Register it as a 570 * fixed factor clock for now as there's no generic multiplier 571 * clock implementation and we currently have no need to change 572 * the multiplier value. 573 */ 574 value = readl(base + CPG_PLL4CR); 575 mult = (((value >> 24) & 0x7f) + 1) * 2; 576 break; 577 578 case CLK_TYPE_GEN3_SD: 579 return cpg_sd_clk_register(core, base, __clk_get_name(parent)); 580 581 default: 582 return ERR_PTR(-EINVAL); 583 } 584 585 return clk_register_fixed_factor(NULL, core->name, 586 __clk_get_name(parent), 0, mult, div); 587 } 588 589 /* 590 * Reset register definitions. 591 */ 592 #define MODEMR 0xe6160060 593 594 static u32 rcar_gen3_read_mode_pins(void) 595 { 596 void __iomem *modemr = ioremap_nocache(MODEMR, 4); 597 u32 mode; 598 599 BUG_ON(!modemr); 600 mode = ioread32(modemr); 601 iounmap(modemr); 602 603 return mode; 604 } 605 606 static int __init r8a7795_cpg_mssr_init(struct device *dev) 607 { 608 u32 cpg_mode = rcar_gen3_read_mode_pins(); 609 610 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 611 if (!cpg_pll_config->extal_div) { 612 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); 613 return -EINVAL; 614 } 615 616 return 0; 617 } 618 619 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 620 /* Core Clocks */ 621 .core_clks = r8a7795_core_clks, 622 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), 623 .last_dt_core_clk = LAST_DT_CORE_CLK, 624 .num_total_core_clks = MOD_CLK_BASE, 625 626 /* Module Clocks */ 627 .mod_clks = r8a7795_mod_clks, 628 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), 629 .num_hw_mod_clks = 12 * 32, 630 631 /* Critical Module Clocks */ 632 .crit_mod_clks = r8a7795_crit_mod_clks, 633 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), 634 635 /* Callbacks */ 636 .init = r8a7795_cpg_mssr_init, 637 .cpg_clk_register = r8a7795_cpg_clk_register, 638 }; 639