1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R7S9210 Clock Pulse Generator / Module Standby 4 * 5 * Based on r8a7795-cpg-mssr.c 6 * 7 * Copyright (C) 2018 Chris Brandt 8 * Copyright (C) 2018 Renesas Electronics Corp. 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <dt-bindings/clock/r7s9210-cpg-mssr.h> 15 #include "renesas-cpg-mssr.h" 16 17 #define CPG_FRQCR 0x00 18 19 static u8 cpg_mode; 20 21 /* Internal Clock ratio table */ 22 static const struct { 23 unsigned int i; 24 unsigned int g; 25 unsigned int b; 26 unsigned int p1; 27 /* p0 is always 32 */; 28 } ratio_tab[5] = { /* I, G, B, P1 */ 29 { 2, 4, 8, 16}, /* FRQCR = 0x012 */ 30 { 4, 4, 8, 16}, /* FRQCR = 0x112 */ 31 { 8, 4, 8, 16}, /* FRQCR = 0x212 */ 32 { 16, 8, 16, 16}, /* FRQCR = 0x322 */ 33 { 16, 16, 32, 32}, /* FRQCR = 0x333 */ 34 }; 35 36 enum rz_clk_types { 37 CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM, 38 CLK_TYPE_RZA_PLL, 39 }; 40 41 enum clk_ids { 42 /* Core Clock Outputs exported to DT */ 43 LAST_DT_CORE_CLK = R7S9210_CLK_P0, 44 45 /* External Input Clocks */ 46 CLK_EXTAL, 47 48 /* Internal Core Clocks */ 49 CLK_MAIN, 50 CLK_PLL, 51 52 /* Module Clocks */ 53 MOD_CLK_BASE 54 }; 55 56 static struct cpg_core_clk r7s9210_core_clks[] = { 57 /* External Clock Inputs */ 58 DEF_INPUT("extal", CLK_EXTAL), 59 60 /* Internal Core Clocks */ 61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL), 62 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN), 63 64 /* Core Clock Outputs */ 65 DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1), 66 DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1), 67 DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1), 68 DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1), 69 DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1), 70 DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1), 71 }; 72 73 static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { 74 DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C), 75 DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C), 76 DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C), 77 78 DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C), 79 DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C), 80 DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C), 81 DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C), 82 DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C), 83 84 DEF_MOD_STB("ether1", 64, R7S9210_CLK_B), 85 DEF_MOD_STB("ether0", 65, R7S9210_CLK_B), 86 87 DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1), 88 DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1), 89 DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1), 90 DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1), 91 92 }; 93 94 struct clk * __init rza2_cpg_clk_register(struct device *dev, 95 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 96 struct clk **clks, void __iomem *base, 97 struct raw_notifier_head *notifiers) 98 { 99 struct clk *parent; 100 unsigned int mult = 1; 101 unsigned int div = 1; 102 u16 frqcr; 103 u8 index; 104 int i; 105 106 parent = clks[core->parent]; 107 if (IS_ERR(parent)) 108 return ERR_CAST(parent); 109 110 switch (core->id) { 111 case CLK_MAIN: 112 break; 113 114 case CLK_PLL: 115 if (cpg_mode) 116 mult = 44; /* Divider 1 is 1/2 */ 117 else 118 mult = 88; /* Divider 1 is 1 */ 119 break; 120 121 default: 122 return ERR_PTR(-EINVAL); 123 } 124 125 /* Adjust the dividers based on the current FRQCR setting */ 126 if (core->id == CLK_MAIN) { 127 128 /* If EXTAL is above 12MHz, then we know it is Mode 1 */ 129 if (clk_get_rate(parent) > 12000000) 130 cpg_mode = 1; 131 132 frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF; 133 if (frqcr == 0x012) 134 index = 0; 135 else if (frqcr == 0x112) 136 index = 1; 137 else if (frqcr == 0x212) 138 index = 2; 139 else if (frqcr == 0x322) 140 index = 3; 141 else if (frqcr == 0x333) 142 index = 4; 143 else 144 BUG_ON(1); /* Illegal FRQCR value */ 145 146 for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) { 147 switch (r7s9210_core_clks[i].id) { 148 case R7S9210_CLK_I: 149 r7s9210_core_clks[i].div = ratio_tab[index].i; 150 break; 151 case R7S9210_CLK_G: 152 r7s9210_core_clks[i].div = ratio_tab[index].g; 153 break; 154 case R7S9210_CLK_B: 155 r7s9210_core_clks[i].div = ratio_tab[index].b; 156 break; 157 case R7S9210_CLK_P1: 158 case R7S9210_CLK_P1C: 159 r7s9210_core_clks[i].div = ratio_tab[index].p1; 160 break; 161 case R7S9210_CLK_P0: 162 r7s9210_core_clks[i].div = 32; 163 break; 164 } 165 } 166 } 167 168 return clk_register_fixed_factor(NULL, core->name, 169 __clk_get_name(parent), 0, mult, div); 170 } 171 172 const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = { 173 /* Core Clocks */ 174 .core_clks = r7s9210_core_clks, 175 .num_core_clks = ARRAY_SIZE(r7s9210_core_clks), 176 .last_dt_core_clk = LAST_DT_CORE_CLK, 177 .num_total_core_clks = MOD_CLK_BASE, 178 179 /* Module Clocks */ 180 .mod_clks = r7s9210_mod_clks, 181 .num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks), 182 .num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */ 183 184 /* Callbacks */ 185 .cpg_clk_register = rza2_cpg_clk_register, 186 187 /* RZ/A2 has Standby Control Registers */ 188 .stbyctrl = true, 189 }; 190