1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * VBATTB clock driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/cleanup.h> 9 #include <linux/clk-provider.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 17 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 18 19 #define VBATTB_BKSCCR 0x1c 20 #define VBATTB_BKSCCR_SOSEL 6 21 #define VBATTB_SOSCCR2 0x24 22 #define VBATTB_SOSCCR2_SOSTP2 0 23 #define VBATTB_XOSCCR 0x30 24 #define VBATTB_XOSCCR_OUTEN 16 25 #define VBATTB_XOSCCR_XSEL GENMASK(1, 0) 26 #define VBATTB_XOSCCR_XSEL_4_PF 0x0 27 #define VBATTB_XOSCCR_XSEL_7_PF 0x1 28 #define VBATTB_XOSCCR_XSEL_9_PF 0x2 29 #define VBATTB_XOSCCR_XSEL_12_5_PF 0x3 30 31 /** 32 * struct vbattb_clk - VBATTB clock data structure 33 * @base: base address 34 * @lock: lock 35 */ 36 struct vbattb_clk { 37 void __iomem *base; 38 spinlock_t lock; 39 }; 40 41 static int vbattb_clk_validate_load_capacitance(u32 *reg_lc, u32 of_lc) 42 { 43 switch (of_lc) { 44 case 4000: 45 *reg_lc = VBATTB_XOSCCR_XSEL_4_PF; 46 break; 47 case 7000: 48 *reg_lc = VBATTB_XOSCCR_XSEL_7_PF; 49 break; 50 case 9000: 51 *reg_lc = VBATTB_XOSCCR_XSEL_9_PF; 52 break; 53 case 12500: 54 *reg_lc = VBATTB_XOSCCR_XSEL_12_5_PF; 55 break; 56 default: 57 return -EINVAL; 58 } 59 60 return 0; 61 } 62 63 static void vbattb_clk_action(void *data) 64 { 65 struct device *dev = data; 66 struct reset_control *rstc = dev_get_drvdata(dev); 67 int ret; 68 69 ret = reset_control_assert(rstc); 70 if (ret) 71 dev_err(dev, "Failed to de-assert reset!\n"); 72 73 ret = pm_runtime_put_sync(dev); 74 if (ret < 0) 75 dev_err(dev, "Failed to runtime suspend!\n"); 76 77 of_clk_del_provider(dev->of_node); 78 } 79 80 static int vbattb_clk_probe(struct platform_device *pdev) 81 { 82 struct device_node *np = pdev->dev.of_node; 83 struct clk_parent_data parent_data = {}; 84 struct clk_hw_onecell_data *clk_data; 85 const struct clk_hw *parent_hws[2]; 86 struct device *dev = &pdev->dev; 87 struct reset_control *rstc; 88 struct vbattb_clk *vbclk; 89 u32 of_lc, reg_lc; 90 struct clk_hw *hw; 91 /* 4 clocks are exported: VBATTB_XC, VBATTB_XBYP, VBATTB_MUX, VBATTB_VBATTCLK. */ 92 u8 num_clks = 4; 93 int ret; 94 95 /* Default to 4pF as this is not needed if external clock device is connected. */ 96 of_lc = 4000; 97 of_property_read_u32(np, "quartz-load-femtofarads", &of_lc); 98 99 ret = vbattb_clk_validate_load_capacitance(®_lc, of_lc); 100 if (ret) 101 return ret; 102 103 vbclk = devm_kzalloc(dev, sizeof(*vbclk), GFP_KERNEL); 104 if (!vbclk) 105 return -ENOMEM; 106 107 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_clks), GFP_KERNEL); 108 if (!clk_data) 109 return -ENOMEM; 110 clk_data->num = num_clks; 111 112 vbclk->base = devm_platform_ioremap_resource(pdev, 0); 113 if (IS_ERR(vbclk->base)) 114 return PTR_ERR(vbclk->base); 115 116 ret = devm_pm_runtime_enable(dev); 117 if (ret) 118 return ret; 119 120 rstc = devm_reset_control_get_shared(dev, NULL); 121 if (IS_ERR(rstc)) 122 return PTR_ERR(rstc); 123 124 ret = pm_runtime_resume_and_get(dev); 125 if (ret) 126 return ret; 127 128 ret = reset_control_deassert(rstc); 129 if (ret) { 130 pm_runtime_put_sync(dev); 131 return ret; 132 } 133 134 dev_set_drvdata(dev, rstc); 135 ret = devm_add_action_or_reset(dev, vbattb_clk_action, dev); 136 if (ret) 137 return ret; 138 139 spin_lock_init(&vbclk->lock); 140 141 parent_data.fw_name = "rtx"; 142 hw = devm_clk_hw_register_gate_parent_data(dev, "xc", &parent_data, 0, 143 vbclk->base + VBATTB_SOSCCR2, 144 VBATTB_SOSCCR2_SOSTP2, 145 CLK_GATE_SET_TO_DISABLE, &vbclk->lock); 146 if (IS_ERR(hw)) 147 return PTR_ERR(hw); 148 clk_data->hws[VBATTB_XC] = hw; 149 150 hw = devm_clk_hw_register_fixed_factor_fwname(dev, np, "xbyp", "rtx", 0, 1, 1); 151 if (IS_ERR(hw)) 152 return PTR_ERR(hw); 153 clk_data->hws[VBATTB_XBYP] = hw; 154 155 parent_hws[0] = clk_data->hws[VBATTB_XC]; 156 parent_hws[1] = clk_data->hws[VBATTB_XBYP]; 157 hw = devm_clk_hw_register_mux_parent_hws(dev, "mux", parent_hws, 2, 0, 158 vbclk->base + VBATTB_BKSCCR, 159 VBATTB_BKSCCR_SOSEL, 160 1, 0, &vbclk->lock); 161 if (IS_ERR(hw)) 162 return PTR_ERR(hw); 163 clk_data->hws[VBATTB_MUX] = hw; 164 165 /* Set load capacitance before registering the VBATTCLK clock. */ 166 scoped_guard(spinlock, &vbclk->lock) { 167 u32 val = readl_relaxed(vbclk->base + VBATTB_XOSCCR); 168 169 val &= ~VBATTB_XOSCCR_XSEL; 170 val |= reg_lc; 171 writel_relaxed(val, vbclk->base + VBATTB_XOSCCR); 172 } 173 174 /* This feeds the RTC counter clock and it needs to stay on. */ 175 hw = devm_clk_hw_register_gate_parent_hw(dev, "vbattclk", hw, CLK_IS_CRITICAL, 176 vbclk->base + VBATTB_XOSCCR, 177 VBATTB_XOSCCR_OUTEN, 0, 178 &vbclk->lock); 179 180 if (IS_ERR(hw)) 181 return PTR_ERR(hw); 182 clk_data->hws[VBATTB_VBATTCLK] = hw; 183 184 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 185 } 186 187 static const struct of_device_id vbattb_clk_match[] = { 188 { .compatible = "renesas,r9a08g045-vbattb" }, 189 { /* sentinel */ } 190 }; 191 MODULE_DEVICE_TABLE(of, vbattb_clk_match); 192 193 static struct platform_driver vbattb_clk_driver = { 194 .driver = { 195 .name = "renesas-vbattb-clk", 196 .of_match_table = vbattb_clk_match, 197 }, 198 .probe = vbattb_clk_probe, 199 }; 200 module_platform_driver(vbattb_clk_driver); 201 202 MODULE_DESCRIPTION("Renesas VBATTB Clock Driver"); 203 MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>"); 204 MODULE_LICENSE("GPL"); 205