1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sh73a0 Core CPG Clocks 4 * 5 * Copyright (C) 2014 Ulrich Hecht 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/clk/renesas.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 18 struct sh73a0_cpg { 19 struct clk_onecell_data data; 20 spinlock_t lock; 21 void __iomem *reg; 22 }; 23 24 #define CPG_FRQCRA 0x00 25 #define CPG_FRQCRB 0x04 26 #define CPG_SD0CKCR 0x74 27 #define CPG_SD1CKCR 0x78 28 #define CPG_SD2CKCR 0x7c 29 #define CPG_PLLECR 0xd0 30 #define CPG_PLL0CR 0xd8 31 #define CPG_PLL1CR 0x28 32 #define CPG_PLL2CR 0x2c 33 #define CPG_PLL3CR 0xdc 34 #define CPG_CKSCR 0xc0 35 #define CPG_DSI0PHYCR 0x6c 36 #define CPG_DSI1PHYCR 0x70 37 38 #define CLK_ENABLE_ON_INIT BIT(0) 39 40 struct div4_clk { 41 const char *name; 42 const char *parent; 43 unsigned int reg; 44 unsigned int shift; 45 }; 46 47 static const struct div4_clk div4_clks[] = { 48 { "zg", "pll0", CPG_FRQCRA, 16 }, 49 { "m3", "pll1", CPG_FRQCRA, 12 }, 50 { "b", "pll1", CPG_FRQCRA, 8 }, 51 { "m1", "pll1", CPG_FRQCRA, 4 }, 52 { "m2", "pll1", CPG_FRQCRA, 0 }, 53 { "zx", "pll1", CPG_FRQCRB, 12 }, 54 { "hp", "pll1", CPG_FRQCRB, 4 }, 55 { NULL, NULL, 0, 0 }, 56 }; 57 58 static const struct clk_div_table div4_div_table[] = { 59 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, 60 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, 61 { 12, 7 }, { 0, 0 } 62 }; 63 64 static const struct clk_div_table z_div_table[] = { 65 /* ZSEL == 0 */ 66 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 }, 67 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 }, 68 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 }, 69 /* ZSEL == 1 */ 70 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 }, 71 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 } 72 }; 73 74 static struct clk * __init 75 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, 76 const char *name) 77 { 78 const struct clk_div_table *table = NULL; 79 unsigned int shift, reg, width; 80 const char *parent_name = NULL; 81 unsigned int mult = 1; 82 unsigned int div = 1; 83 84 if (!strcmp(name, "main")) { 85 /* extal1, extal1_div2, extal2, extal2_div2 */ 86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; 87 88 parent_name = of_clk_get_parent_name(np, parent_idx >> 1); 89 div = (parent_idx & 1) + 1; 90 } else if (!strncmp(name, "pll", 3)) { 91 void __iomem *enable_reg = cpg->reg; 92 u32 enable_bit = name[3] - '0'; 93 94 parent_name = "main"; 95 switch (enable_bit) { 96 case 0: 97 enable_reg += CPG_PLL0CR; 98 break; 99 case 1: 100 enable_reg += CPG_PLL1CR; 101 break; 102 case 2: 103 enable_reg += CPG_PLL2CR; 104 break; 105 case 3: 106 enable_reg += CPG_PLL3CR; 107 break; 108 default: 109 return ERR_PTR(-EINVAL); 110 } 111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { 112 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; 113 /* handle CFG bit for PLL1 and PLL2 */ 114 if (enable_bit == 1 || enable_bit == 2) 115 if (readl(enable_reg) & BIT(20)) 116 mult *= 2; 117 } 118 } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { 119 u32 phy_no = name[3] - '0'; 120 void __iomem *dsi_reg = cpg->reg + 121 (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); 122 123 parent_name = phy_no ? "dsi1pck" : "dsi0pck"; 124 mult = __raw_readl(dsi_reg); 125 if (!(mult & 0x8000)) 126 mult = 1; 127 else 128 mult = (mult & 0x3f) + 1; 129 } else if (!strcmp(name, "z")) { 130 parent_name = "pll0"; 131 table = z_div_table; 132 reg = CPG_FRQCRB; 133 shift = 24; 134 width = 5; 135 } else { 136 const struct div4_clk *c; 137 138 for (c = div4_clks; c->name; c++) { 139 if (!strcmp(name, c->name)) { 140 parent_name = c->parent; 141 table = div4_div_table; 142 reg = c->reg; 143 shift = c->shift; 144 width = 4; 145 break; 146 } 147 } 148 if (!c->name) 149 return ERR_PTR(-EINVAL); 150 } 151 152 if (!table) { 153 return clk_register_fixed_factor(NULL, name, parent_name, 0, 154 mult, div); 155 } else { 156 return clk_register_divider_table(NULL, name, parent_name, 0, 157 cpg->reg + reg, shift, width, 0, 158 table, &cpg->lock); 159 } 160 } 161 162 static void __init sh73a0_cpg_clocks_init(struct device_node *np) 163 { 164 struct sh73a0_cpg *cpg; 165 struct clk **clks; 166 unsigned int i; 167 int num_clks; 168 169 num_clks = of_property_count_strings(np, "clock-output-names"); 170 if (num_clks < 0) { 171 pr_err("%s: failed to count clocks\n", __func__); 172 return; 173 } 174 175 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); 176 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); 177 if (cpg == NULL || clks == NULL) { 178 /* We're leaking memory on purpose, there's no point in cleaning 179 * up as the system won't boot anyway. 180 */ 181 return; 182 } 183 184 spin_lock_init(&cpg->lock); 185 186 cpg->data.clks = clks; 187 cpg->data.clk_num = num_clks; 188 189 cpg->reg = of_iomap(np, 0); 190 if (WARN_ON(cpg->reg == NULL)) 191 return; 192 193 /* Set SDHI clocks to a known state */ 194 writel(0x108, cpg->reg + CPG_SD0CKCR); 195 writel(0x108, cpg->reg + CPG_SD1CKCR); 196 writel(0x108, cpg->reg + CPG_SD2CKCR); 197 198 for (i = 0; i < num_clks; ++i) { 199 const char *name; 200 struct clk *clk; 201 202 of_property_read_string_index(np, "clock-output-names", i, 203 &name); 204 205 clk = sh73a0_cpg_register_clock(np, cpg, name); 206 if (IS_ERR(clk)) 207 pr_err("%s: failed to register %pOFn %s clock (%ld)\n", 208 __func__, np, name, PTR_ERR(clk)); 209 else 210 cpg->data.clks[i] = clk; 211 } 212 213 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); 214 } 215 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks", 216 sh73a0_cpg_clocks_init); 217