1 /* 2 * r8a7790 Common Clock Framework support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * 6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/slab.h> 20 21 #include "clk-div6.h" 22 23 #define CPG_DIV6_CKSTP BIT(8) 24 #define CPG_DIV6_DIV(d) ((d) & 0x3f) 25 #define CPG_DIV6_DIV_MASK 0x3f 26 27 /** 28 * struct div6_clock - CPG 6 bit divider clock 29 * @hw: handle between common and hardware-specific interfaces 30 * @reg: IO-remapped register 31 * @div: divisor value (1-64) 32 * @src_shift: Shift to access the register bits to select the parent clock 33 * @src_width: Number of register bits to select the parent clock (may be 0) 34 * @parents: Array to map from valid parent clocks indices to hardware indices 35 */ 36 struct div6_clock { 37 struct clk_hw hw; 38 void __iomem *reg; 39 unsigned int div; 40 u32 src_shift; 41 u32 src_width; 42 u8 *parents; 43 }; 44 45 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw) 46 47 static int cpg_div6_clock_enable(struct clk_hw *hw) 48 { 49 struct div6_clock *clock = to_div6_clock(hw); 50 u32 val; 51 52 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) 53 | CPG_DIV6_DIV(clock->div - 1); 54 clk_writel(val, clock->reg); 55 56 return 0; 57 } 58 59 static void cpg_div6_clock_disable(struct clk_hw *hw) 60 { 61 struct div6_clock *clock = to_div6_clock(hw); 62 u32 val; 63 64 val = clk_readl(clock->reg); 65 val |= CPG_DIV6_CKSTP; 66 /* 67 * DIV6 clocks require the divisor field to be non-zero when stopping 68 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be 69 * re-enabled later if the divisor field is changed when stopping the 70 * clock 71 */ 72 if (!(val & CPG_DIV6_DIV_MASK)) 73 val |= CPG_DIV6_DIV_MASK; 74 clk_writel(val, clock->reg); 75 } 76 77 static int cpg_div6_clock_is_enabled(struct clk_hw *hw) 78 { 79 struct div6_clock *clock = to_div6_clock(hw); 80 81 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); 82 } 83 84 static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, 85 unsigned long parent_rate) 86 { 87 struct div6_clock *clock = to_div6_clock(hw); 88 89 return parent_rate / clock->div; 90 } 91 92 static unsigned int cpg_div6_clock_calc_div(unsigned long rate, 93 unsigned long parent_rate) 94 { 95 unsigned int div; 96 97 if (!rate) 98 rate = 1; 99 100 div = DIV_ROUND_CLOSEST(parent_rate, rate); 101 return clamp_t(unsigned int, div, 1, 64); 102 } 103 104 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, 105 unsigned long *parent_rate) 106 { 107 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); 108 109 return *parent_rate / div; 110 } 111 112 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, 113 unsigned long parent_rate) 114 { 115 struct div6_clock *clock = to_div6_clock(hw); 116 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); 117 u32 val; 118 119 clock->div = div; 120 121 val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK; 122 /* Only program the new divisor if the clock isn't stopped. */ 123 if (!(val & CPG_DIV6_CKSTP)) 124 clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); 125 126 return 0; 127 } 128 129 static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) 130 { 131 struct div6_clock *clock = to_div6_clock(hw); 132 unsigned int i; 133 u8 hw_index; 134 135 if (clock->src_width == 0) 136 return 0; 137 138 hw_index = (clk_readl(clock->reg) >> clock->src_shift) & 139 (BIT(clock->src_width) - 1); 140 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 141 if (clock->parents[i] == hw_index) 142 return i; 143 } 144 145 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", 146 __func__, clk_hw_get_name(hw), hw_index); 147 return 0; 148 } 149 150 static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) 151 { 152 struct div6_clock *clock = to_div6_clock(hw); 153 u8 hw_index; 154 u32 mask; 155 156 if (index >= clk_hw_get_num_parents(hw)) 157 return -EINVAL; 158 159 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); 160 hw_index = clock->parents[index]; 161 162 clk_writel((clk_readl(clock->reg) & mask) | 163 (hw_index << clock->src_shift), clock->reg); 164 165 return 0; 166 } 167 168 static const struct clk_ops cpg_div6_clock_ops = { 169 .enable = cpg_div6_clock_enable, 170 .disable = cpg_div6_clock_disable, 171 .is_enabled = cpg_div6_clock_is_enabled, 172 .get_parent = cpg_div6_clock_get_parent, 173 .set_parent = cpg_div6_clock_set_parent, 174 .recalc_rate = cpg_div6_clock_recalc_rate, 175 .round_rate = cpg_div6_clock_round_rate, 176 .set_rate = cpg_div6_clock_set_rate, 177 }; 178 179 180 /** 181 * cpg_div6_register - Register a DIV6 clock 182 * @name: Name of the DIV6 clock 183 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8) 184 * @parent_names: Array containing the names of the parent clocks 185 * @reg: Mapped register used to control the DIV6 clock 186 */ 187 struct clk * __init cpg_div6_register(const char *name, 188 unsigned int num_parents, 189 const char **parent_names, 190 void __iomem *reg) 191 { 192 unsigned int valid_parents; 193 struct clk_init_data init; 194 struct div6_clock *clock; 195 struct clk *clk; 196 unsigned int i; 197 198 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 199 if (!clock) 200 return ERR_PTR(-ENOMEM); 201 202 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents), 203 GFP_KERNEL); 204 if (!clock->parents) { 205 clk = ERR_PTR(-ENOMEM); 206 goto free_clock; 207 } 208 209 clock->reg = reg; 210 211 /* 212 * Read the divisor. Disabling the clock overwrites the divisor, so we 213 * need to cache its value for the enable operation. 214 */ 215 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; 216 217 switch (num_parents) { 218 case 1: 219 /* fixed parent clock */ 220 clock->src_shift = clock->src_width = 0; 221 break; 222 case 4: 223 /* clock with EXSRC bits 6-7 */ 224 clock->src_shift = 6; 225 clock->src_width = 2; 226 break; 227 case 8: 228 /* VCLK with EXSRC bits 12-14 */ 229 clock->src_shift = 12; 230 clock->src_width = 3; 231 break; 232 default: 233 pr_err("%s: invalid number of parents for DIV6 clock %s\n", 234 __func__, name); 235 clk = ERR_PTR(-EINVAL); 236 goto free_parents; 237 } 238 239 /* Filter out invalid parents */ 240 for (i = 0, valid_parents = 0; i < num_parents; i++) { 241 if (parent_names[i]) { 242 parent_names[valid_parents] = parent_names[i]; 243 clock->parents[valid_parents] = i; 244 valid_parents++; 245 } 246 } 247 248 /* Register the clock. */ 249 init.name = name; 250 init.ops = &cpg_div6_clock_ops; 251 init.flags = CLK_IS_BASIC; 252 init.parent_names = parent_names; 253 init.num_parents = valid_parents; 254 255 clock->hw.init = &init; 256 257 clk = clk_register(NULL, &clock->hw); 258 if (IS_ERR(clk)) 259 goto free_parents; 260 261 return clk; 262 263 free_parents: 264 kfree(clock->parents); 265 free_clock: 266 kfree(clock); 267 return clk; 268 } 269 270 static void __init cpg_div6_clock_init(struct device_node *np) 271 { 272 unsigned int num_parents; 273 const char **parent_names; 274 const char *clk_name = np->name; 275 void __iomem *reg; 276 struct clk *clk; 277 unsigned int i; 278 279 num_parents = of_clk_get_parent_count(np); 280 if (num_parents < 1) { 281 pr_err("%s: no parent found for %s DIV6 clock\n", 282 __func__, np->name); 283 return; 284 } 285 286 parent_names = kmalloc_array(num_parents, sizeof(*parent_names), 287 GFP_KERNEL); 288 if (!parent_names) 289 return; 290 291 reg = of_iomap(np, 0); 292 if (reg == NULL) { 293 pr_err("%s: failed to map %s DIV6 clock register\n", 294 __func__, np->name); 295 goto error; 296 } 297 298 /* Parse the DT properties. */ 299 of_property_read_string(np, "clock-output-names", &clk_name); 300 301 for (i = 0; i < num_parents; i++) 302 parent_names[i] = of_clk_get_parent_name(np, i); 303 304 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg); 305 if (IS_ERR(clk)) { 306 pr_err("%s: failed to register %s DIV6 clock (%ld)\n", 307 __func__, np->name, PTR_ERR(clk)); 308 goto error; 309 } 310 311 of_clk_add_provider(np, of_clk_src_simple_get, clk); 312 313 kfree(parent_names); 314 return; 315 316 error: 317 if (reg) 318 iounmap(reg); 319 kfree(parent_names); 320 } 321 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init); 322