19e288cefSKuninori Morimoto# SPDX-License-Identifier: GPL-2.0 29e288cefSKuninori Morimoto 380978a4bSGeert Uytterhoevenconfig CLK_RENESAS 480978a4bSGeert Uytterhoeven bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS 580978a4bSGeert Uytterhoeven default y if ARCH_RENESAS 680978a4bSGeert Uytterhoeven select CLK_EMEV2 if ARCH_EMEV2 780978a4bSGeert Uytterhoeven select CLK_RZA1 if ARCH_R7S72100 8fde35c9cSChris Brandt select CLK_R7S9210 if ARCH_R7S9210 980978a4bSGeert Uytterhoeven select CLK_R8A73A4 if ARCH_R8A73A4 1080978a4bSGeert Uytterhoeven select CLK_R8A7740 if ARCH_R8A7740 11e8208a71SLad Prabhakar select CLK_R8A7742 if ARCH_R8A7742 12016f9663SBiju Das select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 1380978a4bSGeert Uytterhoeven select CLK_R8A7745 if ARCH_R8A7745 145bf2fbbeSBiju Das select CLK_R8A77470 if ARCH_R8A77470 15331a53e0SBiju Das select CLK_R8A774A1 if ARCH_R8A774A1 160b9f1c2cSBiju Das select CLK_R8A774B1 if ARCH_R8A774B1 17906e0a4aSFabrizio Castro select CLK_R8A774C0 if ARCH_R8A774C0 18c8a53fa1SMarian-Cristian Rotariu select CLK_R8A774E1 if ARCH_R8A774E1 1980978a4bSGeert Uytterhoeven select CLK_R8A7778 if ARCH_R8A7778 2080978a4bSGeert Uytterhoeven select CLK_R8A7779 if ARCH_R8A7779 2180978a4bSGeert Uytterhoeven select CLK_R8A7790 if ARCH_R8A7790 2280978a4bSGeert Uytterhoeven select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 2380978a4bSGeert Uytterhoeven select CLK_R8A7792 if ARCH_R8A7792 2480978a4bSGeert Uytterhoeven select CLK_R8A7794 if ARCH_R8A7794 25b1dec4e7SWolfram Sang select CLK_R8A7795 if ARCH_R8A77951 2603975b72SGeert Uytterhoeven select CLK_R8A77960 if ARCH_R8A77960 272ba738d5SGeert Uytterhoeven select CLK_R8A77961 if ARCH_R8A77961 287ce36da9SJacopo Mondi select CLK_R8A77965 if ARCH_R8A77965 298d46e28fSSergei Shtylyov select CLK_R8A77970 if ARCH_R8A77970 30ce15783cSSergei Shtylyov select CLK_R8A77980 if ARCH_R8A77980 313570a2afSYoshihiro Shimoda select CLK_R8A77990 if ARCH_R8A77990 32d71e851dSGeert Uytterhoeven select CLK_R8A77995 if ARCH_R8A77995 3317bcc803SYoshihiro Shimoda select CLK_R8A779A0 if ARCH_R8A779A0 3424aaff6aSYoshihiro Shimoda select CLK_R8A779F0 if ARCH_R8A779F0 350ab55cf1SYoshihiro Shimoda select CLK_R8A779G0 if ARCH_R8A779G0 36f077cab3SCong Dang select CLK_R8A779H0 if ARCH_R8A779H0 374c3d8852SMichel Pollet select CLK_R9A06G032 if ARCH_R9A06G032 38c8b08822SBiju Das select CLK_R9A07G043 if ARCH_R9A07G043 3917f0ff3dSLad Prabhakar select CLK_R9A07G044 if ARCH_R9A07G044 40a1bcf50aSBiju Das select CLK_R9A07G054 if ARCH_R9A07G054 41de60a3ebSClaudiu Beznea select CLK_R9A08G045 if ARCH_R9A08G045 421dd65bb0SPhil Edworthy select CLK_R9A09G011 if ARCH_R9A09G011 43bb6a9aafSBiju Das select CLK_R9A09G047 if ARCH_R9A09G047 44f6462eb0SLad Prabhakar select CLK_R9A09G056 if ARCH_R9A09G056 4536932cbcSLad Prabhakar select CLK_R9A09G057 if ARCH_R9A09G057 46065fe720SThierry Bultel select CLK_R9A09G077 if ARCH_R9A09G077 47*8b8ca279SLad Prabhakar select CLK_R9A09G087 if ARCH_R9A09G087 4880978a4bSGeert Uytterhoeven select CLK_SH73A0 if ARCH_SH73A0 4980978a4bSGeert Uytterhoeven 5080978a4bSGeert Uytterhoevenif CLK_RENESAS 5180978a4bSGeert Uytterhoeven 5280978a4bSGeert Uytterhoeven# SoC 5380978a4bSGeert Uytterhoevenconfig CLK_EMEV2 5480978a4bSGeert Uytterhoeven bool "Emma Mobile EV2 clock support" if COMPILE_TEST 5580978a4bSGeert Uytterhoeven 5680978a4bSGeert Uytterhoevenconfig CLK_RZA1 57371dd373SGeert Uytterhoeven bool "RZ/A1H clock support" if COMPILE_TEST 5880978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 5980978a4bSGeert Uytterhoeven 60fde35c9cSChris Brandtconfig CLK_R7S9210 61fde35c9cSChris Brandt bool "RZ/A2 clock support" if COMPILE_TEST 62fde35c9cSChris Brandt select CLK_RENESAS_CPG_MSSR 63fde35c9cSChris Brandt 6480978a4bSGeert Uytterhoevenconfig CLK_R8A73A4 65371dd373SGeert Uytterhoeven bool "R-Mobile APE6 clock support" if COMPILE_TEST 6680978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 6780978a4bSGeert Uytterhoeven select CLK_RENESAS_DIV6 6880978a4bSGeert Uytterhoeven 6980978a4bSGeert Uytterhoevenconfig CLK_R8A7740 70371dd373SGeert Uytterhoeven bool "R-Mobile A1 clock support" if COMPILE_TEST 7180978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 7280978a4bSGeert Uytterhoeven select CLK_RENESAS_DIV6 7380978a4bSGeert Uytterhoeven 74e8208a71SLad Prabhakarconfig CLK_R8A7742 75e8208a71SLad Prabhakar bool "RZ/G1H clock support" if COMPILE_TEST 76e8208a71SLad Prabhakar select CLK_RCAR_GEN2_CPG 77e8208a71SLad Prabhakar 7880978a4bSGeert Uytterhoevenconfig CLK_R8A7743 79371dd373SGeert Uytterhoeven bool "RZ/G1M clock support" if COMPILE_TEST 8080978a4bSGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 8180978a4bSGeert Uytterhoeven 8280978a4bSGeert Uytterhoevenconfig CLK_R8A7745 83371dd373SGeert Uytterhoeven bool "RZ/G1E clock support" if COMPILE_TEST 8480978a4bSGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 8580978a4bSGeert Uytterhoeven 865bf2fbbeSBiju Dasconfig CLK_R8A77470 875bf2fbbeSBiju Das bool "RZ/G1C clock support" if COMPILE_TEST 885bf2fbbeSBiju Das select CLK_RCAR_GEN2_CPG 895bf2fbbeSBiju Das 90331a53e0SBiju Dasconfig CLK_R8A774A1 91331a53e0SBiju Das bool "RZ/G2M clock support" if COMPILE_TEST 92331a53e0SBiju Das select CLK_RCAR_GEN3_CPG 93331a53e0SBiju Das 940b9f1c2cSBiju Dasconfig CLK_R8A774B1 950b9f1c2cSBiju Das bool "RZ/G2N clock support" if COMPILE_TEST 960b9f1c2cSBiju Das select CLK_RCAR_GEN3_CPG 970b9f1c2cSBiju Das 98906e0a4aSFabrizio Castroconfig CLK_R8A774C0 99906e0a4aSFabrizio Castro bool "RZ/G2E clock support" if COMPILE_TEST 100906e0a4aSFabrizio Castro select CLK_RCAR_GEN3_CPG 101906e0a4aSFabrizio Castro 102c8a53fa1SMarian-Cristian Rotariuconfig CLK_R8A774E1 103c8a53fa1SMarian-Cristian Rotariu bool "RZ/G2H clock support" if COMPILE_TEST 104c8a53fa1SMarian-Cristian Rotariu select CLK_RCAR_GEN3_CPG 105c8a53fa1SMarian-Cristian Rotariu 10680978a4bSGeert Uytterhoevenconfig CLK_R8A7778 107371dd373SGeert Uytterhoeven bool "R-Car M1A clock support" if COMPILE_TEST 10880978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 10980978a4bSGeert Uytterhoeven 11080978a4bSGeert Uytterhoevenconfig CLK_R8A7779 111371dd373SGeert Uytterhoeven bool "R-Car H1 clock support" if COMPILE_TEST 11280978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 11380978a4bSGeert Uytterhoeven 11480978a4bSGeert Uytterhoevenconfig CLK_R8A7790 115371dd373SGeert Uytterhoeven bool "R-Car H2 clock support" if COMPILE_TEST 116d4e59f10SGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 11780978a4bSGeert Uytterhoeven 11880978a4bSGeert Uytterhoevenconfig CLK_R8A7791 119371dd373SGeert Uytterhoeven bool "R-Car M2-W/N clock support" if COMPILE_TEST 1206449ab81SGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 12180978a4bSGeert Uytterhoeven 12280978a4bSGeert Uytterhoevenconfig CLK_R8A7792 123371dd373SGeert Uytterhoeven bool "R-Car V2H clock support" if COMPILE_TEST 124fd3c2f38SGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 12580978a4bSGeert Uytterhoeven 12680978a4bSGeert Uytterhoevenconfig CLK_R8A7794 127371dd373SGeert Uytterhoeven bool "R-Car E2 clock support" if COMPILE_TEST 1282d75588aSGeert Uytterhoeven select CLK_RCAR_GEN2_CPG 12980978a4bSGeert Uytterhoeven 13080978a4bSGeert Uytterhoevenconfig CLK_R8A7795 131371dd373SGeert Uytterhoeven bool "R-Car H3 clock support" if COMPILE_TEST 13280978a4bSGeert Uytterhoeven select CLK_RCAR_GEN3_CPG 13380978a4bSGeert Uytterhoeven 13492d1ebaeSGeert Uytterhoevenconfig CLK_R8A77960 135371dd373SGeert Uytterhoeven bool "R-Car M3-W clock support" if COMPILE_TEST 13680978a4bSGeert Uytterhoeven select CLK_RCAR_GEN3_CPG 13780978a4bSGeert Uytterhoeven 1382ba738d5SGeert Uytterhoevenconfig CLK_R8A77961 1392ba738d5SGeert Uytterhoeven bool "R-Car M3-W+ clock support" if COMPILE_TEST 1402ba738d5SGeert Uytterhoeven select CLK_RCAR_GEN3_CPG 1412ba738d5SGeert Uytterhoeven 1427ce36da9SJacopo Mondiconfig CLK_R8A77965 1437ce36da9SJacopo Mondi bool "R-Car M3-N clock support" if COMPILE_TEST 1447ce36da9SJacopo Mondi select CLK_RCAR_GEN3_CPG 1457ce36da9SJacopo Mondi 1468d46e28fSSergei Shtylyovconfig CLK_R8A77970 1478d46e28fSSergei Shtylyov bool "R-Car V3M clock support" if COMPILE_TEST 1488d46e28fSSergei Shtylyov select CLK_RCAR_GEN3_CPG 1498d46e28fSSergei Shtylyov 150ce15783cSSergei Shtylyovconfig CLK_R8A77980 151ce15783cSSergei Shtylyov bool "R-Car V3H clock support" if COMPILE_TEST 152ce15783cSSergei Shtylyov select CLK_RCAR_GEN3_CPG 153ce15783cSSergei Shtylyov 1543570a2afSYoshihiro Shimodaconfig CLK_R8A77990 1553570a2afSYoshihiro Shimoda bool "R-Car E3 clock support" if COMPILE_TEST 1563570a2afSYoshihiro Shimoda select CLK_RCAR_GEN3_CPG 1573570a2afSYoshihiro Shimoda 158d71e851dSGeert Uytterhoevenconfig CLK_R8A77995 159d71e851dSGeert Uytterhoeven bool "R-Car D3 clock support" if COMPILE_TEST 160d71e851dSGeert Uytterhoeven select CLK_RCAR_GEN3_CPG 161d71e851dSGeert Uytterhoeven 16217bcc803SYoshihiro Shimodaconfig CLK_R8A779A0 16317bcc803SYoshihiro Shimoda bool "R-Car V3U clock support" if COMPILE_TEST 164470e3f0dSYoshihiro Shimoda select CLK_RCAR_GEN4_CPG 16517bcc803SYoshihiro Shimoda 16624aaff6aSYoshihiro Shimodaconfig CLK_R8A779F0 16724aaff6aSYoshihiro Shimoda bool "R-Car S4-8 clock support" if COMPILE_TEST 16824aaff6aSYoshihiro Shimoda select CLK_RCAR_GEN4_CPG 16924aaff6aSYoshihiro Shimoda 1700ab55cf1SYoshihiro Shimodaconfig CLK_R8A779G0 1710ab55cf1SYoshihiro Shimoda bool "R-Car V4H clock support" if COMPILE_TEST 1720ab55cf1SYoshihiro Shimoda select CLK_RCAR_GEN4_CPG 1730ab55cf1SYoshihiro Shimoda 174f077cab3SCong Dangconfig CLK_R8A779H0 175f077cab3SCong Dang bool "R-Car V4M clock support" if COMPILE_TEST 176f077cab3SCong Dang select CLK_RCAR_GEN4_CPG 177f077cab3SCong Dang 1784c3d8852SMichel Polletconfig CLK_R9A06G032 179e8425dd5SGeert Uytterhoeven bool "RZ/N1D clock support" if COMPILE_TEST 1804c3d8852SMichel Pollet 181c8b08822SBiju Dasconfig CLK_R9A07G043 182c8b08822SBiju Das bool "RZ/G2UL clock support" if COMPILE_TEST 183c8b08822SBiju Das select CLK_RZG2L 184c8b08822SBiju Das 18517f0ff3dSLad Prabhakarconfig CLK_R9A07G044 18617f0ff3dSLad Prabhakar bool "RZ/G2L clock support" if COMPILE_TEST 18717f0ff3dSLad Prabhakar select CLK_RZG2L 18817f0ff3dSLad Prabhakar 189a1bcf50aSBiju Dasconfig CLK_R9A07G054 190a1bcf50aSBiju Das bool "RZ/V2L clock support" if COMPILE_TEST 191a1bcf50aSBiju Das select CLK_RZG2L 192a1bcf50aSBiju Das 193de60a3ebSClaudiu Bezneaconfig CLK_R9A08G045 194de60a3ebSClaudiu Beznea bool "RZ/G3S clock support" if COMPILE_TEST 195de60a3ebSClaudiu Beznea select CLK_RZG2L 196de60a3ebSClaudiu Beznea 1971dd65bb0SPhil Edworthyconfig CLK_R9A09G011 1981dd65bb0SPhil Edworthy bool "RZ/V2M clock support" if COMPILE_TEST 1991dd65bb0SPhil Edworthy select CLK_RZG2L 2001dd65bb0SPhil Edworthy 201bb6a9aafSBiju Dasconfig CLK_R9A09G047 202bb6a9aafSBiju Das bool "RZ/G3E clock support" if COMPILE_TEST 203bb6a9aafSBiju Das select CLK_RZV2H 204bb6a9aafSBiju Das 205f6462eb0SLad Prabhakarconfig CLK_R9A09G056 206f6462eb0SLad Prabhakar bool "RZ/V2N clock support" if COMPILE_TEST 207f6462eb0SLad Prabhakar select CLK_RZV2H 208f6462eb0SLad Prabhakar 20936932cbcSLad Prabhakarconfig CLK_R9A09G057 21036932cbcSLad Prabhakar bool "RZ/V2H(P) clock support" if COMPILE_TEST 21136932cbcSLad Prabhakar select CLK_RZV2H 21236932cbcSLad Prabhakar 213065fe720SThierry Bultelconfig CLK_R9A09G077 214065fe720SThierry Bultel bool "RZ/T2H clock support" if COMPILE_TEST 215065fe720SThierry Bultel select CLK_RENESAS_CPG_MSSR 216065fe720SThierry Bultel 217*8b8ca279SLad Prabhakarconfig CLK_R9A09G087 218*8b8ca279SLad Prabhakar bool "RZ/N2H clock support" if COMPILE_TEST 219*8b8ca279SLad Prabhakar select CLK_RENESAS_CPG_MSSR 220*8b8ca279SLad Prabhakar 22180978a4bSGeert Uytterhoevenconfig CLK_SH73A0 222371dd373SGeert Uytterhoeven bool "SH-Mobile AG5 clock support" if COMPILE_TEST 22380978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSTP 22480978a4bSGeert Uytterhoeven select CLK_RENESAS_DIV6 22580978a4bSGeert Uytterhoeven 22680978a4bSGeert Uytterhoeven 22780978a4bSGeert Uytterhoeven# Family 2288bb67d87SWolfram Sangconfig CLK_RCAR_CPG_LIB 2298bb67d87SWolfram Sang bool "CPG/MSSR library functions" if COMPILE_TEST 2308bb67d87SWolfram Sang 23180978a4bSGeert Uytterhoevenconfig CLK_RCAR_GEN2_CPG 232371dd373SGeert Uytterhoeven bool "R-Car Gen2 CPG clock support" if COMPILE_TEST 23380978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSSR 23480978a4bSGeert Uytterhoeven 23580978a4bSGeert Uytterhoevenconfig CLK_RCAR_GEN3_CPG 23615d683e6SLad Prabhakar bool "R-Car Gen3 and RZ/G2 CPG clock support" if COMPILE_TEST 2378bb67d87SWolfram Sang select CLK_RCAR_CPG_LIB 23880978a4bSGeert Uytterhoeven select CLK_RENESAS_CPG_MSSR 23980978a4bSGeert Uytterhoeven 240470e3f0dSYoshihiro Shimodaconfig CLK_RCAR_GEN4_CPG 241470e3f0dSYoshihiro Shimoda bool "R-Car Gen4 clock support" if COMPILE_TEST 242470e3f0dSYoshihiro Shimoda select CLK_RCAR_CPG_LIB 243470e3f0dSYoshihiro Shimoda select CLK_RENESAS_CPG_MSSR 244470e3f0dSYoshihiro Shimoda 245311accb6SYoshihiro Shimodaconfig CLK_RCAR_USB2_CLOCK_SEL 246ebae969dSGeert Uytterhoeven bool "R-Car USB2 clock selector support" 247311accb6SYoshihiro Shimoda depends on ARCH_RENESAS || COMPILE_TEST 2481ab4f439SYoshihiro Shimoda select RESET_CONTROLLER 249311accb6SYoshihiro Shimoda help 250311accb6SYoshihiro Shimoda This is a driver for R-Car USB2 clock selector 25180978a4bSGeert Uytterhoeven 252ef3c613cSLad Prabhakarconfig CLK_RZG2L 253ebae969dSGeert Uytterhoeven bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST 254ef3c613cSLad Prabhakar select RESET_CONTROLLER 255ef3c613cSLad Prabhakar 256dd22e562SLad Prabhakarconfig CLK_RZV2H 257bb6a9aafSBiju Das bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST 258dd22e562SLad Prabhakar select RESET_CONTROLLER 259dd22e562SLad Prabhakar 2603b42450cSClaudiu Bezneaconfig CLK_RENESAS_VBATTB 2613b42450cSClaudiu Beznea tristate "Renesas VBATTB clock controller" 2623b42450cSClaudiu Beznea depends on ARCH_RZG2L || COMPILE_TEST 2633b42450cSClaudiu Beznea select RESET_CONTROLLER 2643b42450cSClaudiu Beznea 26580978a4bSGeert Uytterhoeven# Generic 266a5bd7f7aSGeert Uytterhoevenconfig CLK_RENESAS_CPG_MSSR 267371dd373SGeert Uytterhoeven bool "CPG/MSSR clock support" if COMPILE_TEST 26880978a4bSGeert Uytterhoeven select CLK_RENESAS_DIV6 269a5bd7f7aSGeert Uytterhoeven 270a5bd7f7aSGeert Uytterhoevenconfig CLK_RENESAS_CPG_MSTP 271371dd373SGeert Uytterhoeven bool "MSTP clock support" if COMPILE_TEST 27280978a4bSGeert Uytterhoeven 27380978a4bSGeert Uytterhoevenconfig CLK_RENESAS_DIV6 27480978a4bSGeert Uytterhoeven bool "DIV6 clock support" if COMPILE_TEST 27580978a4bSGeert Uytterhoeven 27680978a4bSGeert Uytterhoevenendif # CLK_RENESAS 277