1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MTMIPS SoCs Clock Driver 4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/clk-provider.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/reset-controller.h> 13 #include <linux/slab.h> 14 15 /* Configuration registers */ 16 #define SYSC_REG_SYSTEM_CONFIG 0x10 17 #define SYSC_REG_CLKCFG0 0x2c 18 #define SYSC_REG_RESET_CTRL 0x34 19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c 20 #define SYSC_REG_CPLL_CONFIG0 0x54 21 #define SYSC_REG_CPLL_CONFIG1 0x58 22 23 /* RT2880 SoC */ 24 #define RT2880_CONFIG_CPUCLK_SHIFT 20 25 #define RT2880_CONFIG_CPUCLK_MASK 0x3 26 #define RT2880_CONFIG_CPUCLK_250 0x0 27 #define RT2880_CONFIG_CPUCLK_266 0x1 28 #define RT2880_CONFIG_CPUCLK_280 0x2 29 #define RT2880_CONFIG_CPUCLK_300 0x3 30 31 /* RT305X SoC */ 32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18 33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1 34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0 35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 36 37 /* RT3352 SoC */ 38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 42 43 /* RT3383 SoC */ 44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) 45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8 46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3 47 #define RT3883_SYSCFG0_CPUCLK_250 0x0 48 #define RT3883_SYSCFG0_CPUCLK_384 0x1 49 #define RT3883_SYSCFG0_CPUCLK_480 0x2 50 #define RT3883_SYSCFG0_CPUCLK_500 0x3 51 52 /* RT5350 SoC */ 53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20) 54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 56 #define RT5350_SYSCFG0_CPUCLK_360 0x0 57 #define RT5350_SYSCFG0_CPUCLK_320 0x2 58 #define RT5350_SYSCFG0_CPUCLK_300 0x3 59 60 /* MT7620 and MT76x8 SoCs */ 61 #define MT7620_XTAL_FREQ_SEL BIT(6) 62 #define CPLL_CFG0_SW_CFG BIT(31) 63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 65 #define CPLL_CFG0_LC_CURFCK BIT(15) 66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14) 67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 69 #define CPLL_CFG1_CPU_AUX1 BIT(25) 70 #define CPLL_CFG1_CPU_AUX0 BIT(24) 71 #define CLKCFG0_PERI_CLK_SEL BIT(4) 72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf 74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ 75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ 76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ 77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ 78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ 79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ 80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ 81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ 82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ 83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f 85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f 87 88 /* clock scaling */ 89 #define CLKCFG_FDIV_MASK 0x1f00 90 #define CLKCFG_FDIV_USB_VAL 0x0300 91 #define CLKCFG_FFRAC_MASK 0x001f 92 #define CLKCFG_FFRAC_USB_VAL 0x0003 93 94 struct mtmips_clk; 95 struct mtmips_clk_fixed; 96 struct mtmips_clk_factor; 97 98 struct mtmips_clk_data { 99 struct mtmips_clk *clk_base; 100 size_t num_clk_base; 101 struct mtmips_clk_fixed *clk_fixed; 102 size_t num_clk_fixed; 103 struct mtmips_clk_factor *clk_factor; 104 size_t num_clk_factor; 105 struct mtmips_clk *clk_periph; 106 size_t num_clk_periph; 107 }; 108 109 struct mtmips_clk_priv { 110 struct regmap *sysc; 111 const struct mtmips_clk_data *data; 112 }; 113 114 struct mtmips_clk { 115 struct clk_hw hw; 116 struct mtmips_clk_priv *priv; 117 }; 118 119 struct mtmips_clk_fixed { 120 const char *name; 121 const char *parent; 122 unsigned long rate; 123 struct clk_hw *hw; 124 }; 125 126 struct mtmips_clk_factor { 127 const char *name; 128 const char *parent; 129 int mult; 130 int div; 131 unsigned long flags; 132 struct clk_hw *hw; 133 }; 134 135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, 136 unsigned long parent_rate) 137 { 138 return parent_rate; 139 } 140 141 static const struct clk_ops mtmips_periph_clk_ops = { 142 .recalc_rate = mtmips_pherip_clk_rate, 143 }; 144 145 #define CLK_PERIPH(_name, _parent) { \ 146 .init = &(const struct clk_init_data) { \ 147 .name = _name, \ 148 .ops = &mtmips_periph_clk_ops, \ 149 .parent_data = &(const struct clk_parent_data) {\ 150 .name = _parent, \ 151 .fw_name = _parent \ 152 }, \ 153 .num_parents = 1, \ 154 /* \ 155 * There are drivers for these SoCs that are \ 156 * older than clock driver and are not prepared \ 157 * for the clock. We don't want the kernel to \ 158 * disable anything so we add CLK_IS_CRITICAL \ 159 * flag here. \ 160 */ \ 161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \ 162 }, \ 163 } 164 165 static struct mtmips_clk rt2880_pherip_clks[] = { 166 { CLK_PERIPH("300100.timer", "bus") }, 167 { CLK_PERIPH("300120.watchdog", "bus") }, 168 { CLK_PERIPH("300500.uart", "bus") }, 169 { CLK_PERIPH("300900.i2c", "bus") }, 170 { CLK_PERIPH("300c00.uartlite", "bus") }, 171 { CLK_PERIPH("400000.ethernet", "bus") }, 172 { CLK_PERIPH("480000.wmac", "xtal") } 173 }; 174 175 static struct mtmips_clk rt305x_pherip_clks[] = { 176 { CLK_PERIPH("10000100.timer", "bus") }, 177 { CLK_PERIPH("10000120.watchdog", "bus") }, 178 { CLK_PERIPH("10000500.uart", "bus") }, 179 { CLK_PERIPH("10000900.i2c", "bus") }, 180 { CLK_PERIPH("10000a00.i2s", "bus") }, 181 { CLK_PERIPH("10000b00.spi", "bus") }, 182 { CLK_PERIPH("10000b40.spi", "bus") }, 183 { CLK_PERIPH("10000c00.uartlite", "bus") }, 184 { CLK_PERIPH("10100000.ethernet", "bus") }, 185 { CLK_PERIPH("10180000.wmac", "xtal") } 186 }; 187 188 static struct mtmips_clk rt5350_pherip_clks[] = { 189 { CLK_PERIPH("10000100.timer", "bus") }, 190 { CLK_PERIPH("10000120.watchdog", "bus") }, 191 { CLK_PERIPH("10000500.uart", "periph") }, 192 { CLK_PERIPH("10000900.i2c", "periph") }, 193 { CLK_PERIPH("10000a00.i2s", "periph") }, 194 { CLK_PERIPH("10000b00.spi", "bus") }, 195 { CLK_PERIPH("10000b40.spi", "bus") }, 196 { CLK_PERIPH("10000c00.uartlite", "periph") }, 197 { CLK_PERIPH("10100000.ethernet", "bus") }, 198 { CLK_PERIPH("10180000.wmac", "xtal") } 199 }; 200 201 static struct mtmips_clk mt7620_pherip_clks[] = { 202 { CLK_PERIPH("10000100.timer", "periph") }, 203 { CLK_PERIPH("10000120.watchdog", "periph") }, 204 { CLK_PERIPH("10000500.uart", "periph") }, 205 { CLK_PERIPH("10000900.i2c", "periph") }, 206 { CLK_PERIPH("10000a00.i2s", "periph") }, 207 { CLK_PERIPH("10000b00.spi", "bus") }, 208 { CLK_PERIPH("10000b40.spi", "bus") }, 209 { CLK_PERIPH("10000c00.uartlite", "periph") }, 210 { CLK_PERIPH("10130000.mmc", "sdhc") }, 211 { CLK_PERIPH("10180000.wmac", "xtal") } 212 }; 213 214 static struct mtmips_clk mt76x8_pherip_clks[] = { 215 { CLK_PERIPH("10000100.timer", "periph") }, 216 { CLK_PERIPH("10000120.watchdog", "periph") }, 217 { CLK_PERIPH("10000900.i2c", "periph") }, 218 { CLK_PERIPH("10000a00.i2s", "pcmi2s") }, 219 { CLK_PERIPH("10000b00.spi", "bus") }, 220 { CLK_PERIPH("10000b40.spi", "bus") }, 221 { CLK_PERIPH("10000c00.uart0", "periph") }, 222 { CLK_PERIPH("10000d00.uart1", "periph") }, 223 { CLK_PERIPH("10000e00.uart2", "periph") }, 224 { CLK_PERIPH("10130000.mmc", "sdhc") }, 225 { CLK_PERIPH("10300000.wmac", "xtal") } 226 }; 227 228 static int mtmips_register_pherip_clocks(struct device_node *np, 229 struct clk_hw_onecell_data *clk_data, 230 struct mtmips_clk_priv *priv) 231 { 232 struct clk_hw **hws = clk_data->hws; 233 struct mtmips_clk *sclk; 234 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + 235 priv->data->num_clk_factor; 236 int ret, i; 237 238 for (i = 0; i < priv->data->num_clk_periph; i++) { 239 int idx = idx_start + i; 240 241 sclk = &priv->data->clk_periph[i]; 242 ret = of_clk_hw_register(np, &sclk->hw); 243 if (ret) { 244 pr_err("Couldn't register peripheral clock %d\n", idx); 245 goto err_clk_unreg; 246 } 247 248 hws[idx] = &sclk->hw; 249 } 250 251 return 0; 252 253 err_clk_unreg: 254 while (--i >= 0) { 255 sclk = &priv->data->clk_periph[i]; 256 clk_hw_unregister(&sclk->hw); 257 } 258 return ret; 259 } 260 261 #define CLK_FIXED(_name, _parent, _rate) \ 262 { \ 263 .name = _name, \ 264 .parent = _parent, \ 265 .rate = _rate \ 266 } 267 268 static struct mtmips_clk_fixed rt3883_fixed_clocks[] = { 269 CLK_FIXED("periph", "xtal", 40000000) 270 }; 271 272 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = { 273 CLK_FIXED("periph", "xtal", 40000000) 274 }; 275 276 static struct mtmips_clk_fixed mt7620_fixed_clocks[] = { 277 CLK_FIXED("bbppll", "xtal", 480000000) 278 }; 279 280 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = { 281 CLK_FIXED("bbppll", "xtal", 480000000), 282 CLK_FIXED("pcmi2s", "bbppll", 480000000), 283 CLK_FIXED("periph", "xtal", 40000000) 284 }; 285 286 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, 287 struct mtmips_clk_priv *priv) 288 { 289 struct clk_hw **hws = clk_data->hws; 290 struct mtmips_clk_fixed *sclk; 291 size_t idx_start = priv->data->num_clk_base; 292 int ret, i; 293 294 for (i = 0; i < priv->data->num_clk_fixed; i++) { 295 int idx = idx_start + i; 296 297 sclk = &priv->data->clk_fixed[i]; 298 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, 299 sclk->parent, 0, 300 sclk->rate); 301 if (IS_ERR(sclk->hw)) { 302 ret = PTR_ERR(sclk->hw); 303 pr_err("Couldn't register fixed clock %d\n", idx); 304 goto err_clk_unreg; 305 } 306 307 hws[idx] = sclk->hw; 308 } 309 310 return 0; 311 312 err_clk_unreg: 313 while (--i >= 0) { 314 sclk = &priv->data->clk_fixed[i]; 315 clk_hw_unregister_fixed_rate(sclk->hw); 316 } 317 return ret; 318 } 319 320 #define CLK_FACTOR(_name, _parent, _mult, _div) \ 321 { \ 322 .name = _name, \ 323 .parent = _parent, \ 324 .mult = _mult, \ 325 .div = _div, \ 326 .flags = CLK_SET_RATE_PARENT \ 327 } 328 329 static struct mtmips_clk_factor rt2880_factor_clocks[] = { 330 CLK_FACTOR("bus", "cpu", 1, 2) 331 }; 332 333 static struct mtmips_clk_factor rt305x_factor_clocks[] = { 334 CLK_FACTOR("bus", "cpu", 1, 3) 335 }; 336 337 static struct mtmips_clk_factor mt7620_factor_clocks[] = { 338 CLK_FACTOR("sdhc", "bbppll", 1, 10) 339 }; 340 341 static struct mtmips_clk_factor mt76x8_factor_clocks[] = { 342 CLK_FACTOR("bus", "cpu", 1, 3), 343 CLK_FACTOR("sdhc", "bbppll", 1, 10) 344 }; 345 346 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, 347 struct mtmips_clk_priv *priv) 348 { 349 struct clk_hw **hws = clk_data->hws; 350 struct mtmips_clk_factor *sclk; 351 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; 352 int ret, i; 353 354 for (i = 0; i < priv->data->num_clk_factor; i++) { 355 int idx = idx_start + i; 356 357 sclk = &priv->data->clk_factor[i]; 358 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, 359 sclk->parent, sclk->flags, 360 sclk->mult, sclk->div); 361 if (IS_ERR(sclk->hw)) { 362 ret = PTR_ERR(sclk->hw); 363 pr_err("Couldn't register factor clock %d\n", idx); 364 goto err_clk_unreg; 365 } 366 367 hws[idx] = sclk->hw; 368 } 369 370 return 0; 371 372 err_clk_unreg: 373 while (--i >= 0) { 374 sclk = &priv->data->clk_factor[i]; 375 clk_hw_unregister_fixed_factor(sclk->hw); 376 } 377 return ret; 378 } 379 380 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) 381 { 382 return container_of(hw, struct mtmips_clk, hw); 383 } 384 385 static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw, 386 unsigned long parent_rate) 387 { 388 return 40000000; 389 } 390 391 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, 392 unsigned long parent_rate) 393 { 394 struct mtmips_clk *clk = to_mtmips_clk(hw); 395 struct regmap *sysc = clk->priv->sysc; 396 u32 val; 397 398 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val); 399 if (!(val & RT5350_CLKCFG0_XTAL_SEL)) 400 return 20000000; 401 402 return 40000000; 403 } 404 405 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, 406 unsigned long xtal_clk) 407 { 408 struct mtmips_clk *clk = to_mtmips_clk(hw); 409 struct regmap *sysc = clk->priv->sysc; 410 u32 t; 411 412 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 413 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK; 414 415 switch (t) { 416 case RT5350_SYSCFG0_CPUCLK_360: 417 return 360000000; 418 case RT5350_SYSCFG0_CPUCLK_320: 419 return 320000000; 420 case RT5350_SYSCFG0_CPUCLK_300: 421 return 300000000; 422 default: 423 BUG(); 424 } 425 } 426 427 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, 428 unsigned long parent_rate) 429 { 430 if (parent_rate == 320000000) 431 return parent_rate / 4; 432 433 return parent_rate / 3; 434 } 435 436 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, 437 unsigned long xtal_clk) 438 { 439 struct mtmips_clk *clk = to_mtmips_clk(hw); 440 struct regmap *sysc = clk->priv->sysc; 441 u32 t; 442 443 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 444 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK; 445 446 switch (t) { 447 case RT3352_SYSCFG0_CPUCLK_LOW: 448 return 384000000; 449 case RT3352_SYSCFG0_CPUCLK_HIGH: 450 return 400000000; 451 default: 452 BUG(); 453 } 454 } 455 456 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, 457 unsigned long xtal_clk) 458 { 459 struct mtmips_clk *clk = to_mtmips_clk(hw); 460 struct regmap *sysc = clk->priv->sysc; 461 u32 t; 462 463 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 464 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; 465 466 switch (t) { 467 case RT305X_SYSCFG_CPUCLK_LOW: 468 return 320000000; 469 case RT305X_SYSCFG_CPUCLK_HIGH: 470 return 384000000; 471 default: 472 BUG(); 473 } 474 } 475 476 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, 477 unsigned long xtal_clk) 478 { 479 struct mtmips_clk *clk = to_mtmips_clk(hw); 480 struct regmap *sysc = clk->priv->sysc; 481 u32 t; 482 483 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 484 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK; 485 486 switch (t) { 487 case RT3883_SYSCFG0_CPUCLK_250: 488 return 250000000; 489 case RT3883_SYSCFG0_CPUCLK_384: 490 return 384000000; 491 case RT3883_SYSCFG0_CPUCLK_480: 492 return 480000000; 493 case RT3883_SYSCFG0_CPUCLK_500: 494 return 500000000; 495 default: 496 BUG(); 497 } 498 } 499 500 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, 501 unsigned long parent_rate) 502 { 503 struct mtmips_clk *clk = to_mtmips_clk(hw); 504 struct regmap *sysc = clk->priv->sysc; 505 u32 ddr2; 506 u32 t; 507 508 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 509 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2; 510 511 switch (parent_rate) { 512 case 250000000: 513 return (ddr2) ? 125000000 : 83000000; 514 case 384000000: 515 return (ddr2) ? 128000000 : 96000000; 516 case 480000000: 517 return (ddr2) ? 160000000 : 120000000; 518 case 500000000: 519 return (ddr2) ? 166000000 : 125000000; 520 default: 521 WARN_ON_ONCE(parent_rate == 0); 522 return parent_rate / 4; 523 } 524 } 525 526 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, 527 unsigned long xtal_clk) 528 { 529 struct mtmips_clk *clk = to_mtmips_clk(hw); 530 struct regmap *sysc = clk->priv->sysc; 531 u32 t; 532 533 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 534 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK; 535 536 switch (t) { 537 case RT2880_CONFIG_CPUCLK_250: 538 return 250000000; 539 case RT2880_CONFIG_CPUCLK_266: 540 return 266000000; 541 case RT2880_CONFIG_CPUCLK_280: 542 return 280000000; 543 case RT2880_CONFIG_CPUCLK_300: 544 return 300000000; 545 default: 546 BUG(); 547 } 548 } 549 550 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) 551 { 552 u64 t; 553 554 t = ref_rate; 555 t *= mul; 556 t = div_u64(t, div); 557 558 return t; 559 } 560 561 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, 562 unsigned long parent_rate) 563 { 564 static const u32 clk_divider[] = { 2, 3, 4, 8 }; 565 struct mtmips_clk *clk = to_mtmips_clk(hw); 566 struct regmap *sysc = clk->priv->sysc; 567 unsigned long cpu_pll; 568 u32 t; 569 u32 mul; 570 u32 div; 571 572 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t); 573 if (t & CPLL_CFG0_BYPASS_REF_CLK) { 574 cpu_pll = parent_rate; 575 } else if ((t & CPLL_CFG0_SW_CFG) == 0) { 576 cpu_pll = 600000000; 577 } else { 578 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & 579 CPLL_CFG0_PLL_MULT_RATIO_MASK; 580 mul += 24; 581 if (t & CPLL_CFG0_LC_CURFCK) 582 mul *= 2; 583 584 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & 585 CPLL_CFG0_PLL_DIV_RATIO_MASK; 586 587 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider)); 588 589 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); 590 } 591 592 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t); 593 if (t & CPLL_CFG1_CPU_AUX1) 594 return parent_rate; 595 596 if (t & CPLL_CFG1_CPU_AUX0) 597 return 480000000; 598 599 return cpu_pll; 600 } 601 602 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, 603 unsigned long parent_rate) 604 { 605 struct mtmips_clk *clk = to_mtmips_clk(hw); 606 struct regmap *sysc = clk->priv->sysc; 607 u32 t; 608 u32 mul; 609 u32 div; 610 611 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 612 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; 613 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & 614 CPU_SYS_CLKCFG_CPU_FDIV_MASK; 615 616 return mt7620_calc_rate(parent_rate, mul, div); 617 } 618 619 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, 620 unsigned long parent_rate) 621 { 622 static const u32 ocp_dividers[16] = { 623 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, 624 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, 625 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, 626 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, 627 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, 628 }; 629 struct mtmips_clk *clk = to_mtmips_clk(hw); 630 struct regmap *sysc = clk->priv->sysc; 631 u32 t; 632 u32 ocp_ratio; 633 u32 div; 634 635 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 636 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & 637 CPU_SYS_CLKCFG_OCP_RATIO_MASK; 638 639 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers))) 640 return parent_rate; 641 642 div = ocp_dividers[ocp_ratio]; 643 644 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) 645 return parent_rate; 646 647 return parent_rate / div; 648 } 649 650 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, 651 unsigned long parent_rate) 652 { 653 struct mtmips_clk *clk = to_mtmips_clk(hw); 654 struct regmap *sysc = clk->priv->sysc; 655 u32 t; 656 657 regmap_read(sysc, SYSC_REG_CLKCFG0, &t); 658 if (t & CLKCFG0_PERI_CLK_SEL) 659 return parent_rate; 660 661 return 40000000; 662 } 663 664 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, 665 unsigned long parent_rate) 666 { 667 struct mtmips_clk *clk = to_mtmips_clk(hw); 668 struct regmap *sysc = clk->priv->sysc; 669 u32 t; 670 671 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); 672 if (t & MT7620_XTAL_FREQ_SEL) 673 return 40000000; 674 675 return 20000000; 676 } 677 678 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, 679 unsigned long xtal_clk) 680 { 681 if (xtal_clk == 40000000) 682 return 580000000; 683 684 return 575000000; 685 } 686 687 #define CLK_BASE(_name, _parent, _recalc) { \ 688 .init = &(const struct clk_init_data) { \ 689 .name = _name, \ 690 .ops = &(const struct clk_ops) { \ 691 .recalc_rate = _recalc, \ 692 }, \ 693 .parent_data = &(const struct clk_parent_data) { \ 694 .name = _parent, \ 695 .fw_name = _parent \ 696 }, \ 697 .num_parents = _parent ? 1 : 0 \ 698 }, \ 699 } 700 701 static struct mtmips_clk rt2880_clks_base[] = { 702 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 703 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } 704 }; 705 706 static struct mtmips_clk rt305x_clks_base[] = { 707 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 708 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } 709 }; 710 711 static struct mtmips_clk rt3352_clks_base[] = { 712 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 713 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) } 714 }; 715 716 static struct mtmips_clk rt3883_clks_base[] = { 717 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) }, 718 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, 719 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } 720 }; 721 722 static struct mtmips_clk rt5350_clks_base[] = { 723 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, 724 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) }, 725 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) } 726 }; 727 728 static struct mtmips_clk mt7620_clks_base[] = { 729 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 730 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) }, 731 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) }, 732 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) }, 733 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) } 734 }; 735 736 static struct mtmips_clk mt76x8_clks_base[] = { 737 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, 738 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) } 739 }; 740 741 static int mtmips_register_clocks(struct device_node *np, 742 struct clk_hw_onecell_data *clk_data, 743 struct mtmips_clk_priv *priv) 744 { 745 struct clk_hw **hws = clk_data->hws; 746 struct mtmips_clk *sclk; 747 int ret, i; 748 749 for (i = 0; i < priv->data->num_clk_base; i++) { 750 sclk = &priv->data->clk_base[i]; 751 sclk->priv = priv; 752 ret = of_clk_hw_register(np, &sclk->hw); 753 if (ret) { 754 pr_err("Couldn't register top clock %i\n", i); 755 goto err_clk_unreg; 756 } 757 758 hws[i] = &sclk->hw; 759 } 760 761 return 0; 762 763 err_clk_unreg: 764 while (--i >= 0) { 765 sclk = &priv->data->clk_base[i]; 766 clk_hw_unregister(&sclk->hw); 767 } 768 return ret; 769 } 770 771 static const struct mtmips_clk_data rt2880_clk_data = { 772 .clk_base = rt2880_clks_base, 773 .num_clk_base = ARRAY_SIZE(rt2880_clks_base), 774 .clk_fixed = NULL, 775 .num_clk_fixed = 0, 776 .clk_factor = rt2880_factor_clocks, 777 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks), 778 .clk_periph = rt2880_pherip_clks, 779 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks), 780 }; 781 782 static const struct mtmips_clk_data rt305x_clk_data = { 783 .clk_base = rt305x_clks_base, 784 .num_clk_base = ARRAY_SIZE(rt305x_clks_base), 785 .clk_fixed = NULL, 786 .num_clk_fixed = 0, 787 .clk_factor = rt305x_factor_clocks, 788 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 789 .clk_periph = rt305x_pherip_clks, 790 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks), 791 }; 792 793 static const struct mtmips_clk_data rt3352_clk_data = { 794 .clk_base = rt3352_clks_base, 795 .num_clk_base = ARRAY_SIZE(rt3352_clks_base), 796 .clk_fixed = rt3352_fixed_clocks, 797 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 798 .clk_factor = rt305x_factor_clocks, 799 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), 800 .clk_periph = rt5350_pherip_clks, 801 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 802 }; 803 804 static const struct mtmips_clk_data rt3883_clk_data = { 805 .clk_base = rt3883_clks_base, 806 .num_clk_base = ARRAY_SIZE(rt3883_clks_base), 807 .clk_fixed = rt3883_fixed_clocks, 808 .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks), 809 .clk_factor = NULL, 810 .num_clk_factor = 0, 811 .clk_periph = rt5350_pherip_clks, 812 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 813 }; 814 815 static const struct mtmips_clk_data rt5350_clk_data = { 816 .clk_base = rt5350_clks_base, 817 .num_clk_base = ARRAY_SIZE(rt5350_clks_base), 818 .clk_fixed = rt3352_fixed_clocks, 819 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), 820 .clk_factor = NULL, 821 .num_clk_factor = 0, 822 .clk_periph = rt5350_pherip_clks, 823 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), 824 }; 825 826 static const struct mtmips_clk_data mt7620_clk_data = { 827 .clk_base = mt7620_clks_base, 828 .num_clk_base = ARRAY_SIZE(mt7620_clks_base), 829 .clk_fixed = mt7620_fixed_clocks, 830 .num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks), 831 .clk_factor = mt7620_factor_clocks, 832 .num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks), 833 .clk_periph = mt7620_pherip_clks, 834 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks), 835 }; 836 837 static const struct mtmips_clk_data mt76x8_clk_data = { 838 .clk_base = mt76x8_clks_base, 839 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base), 840 .clk_fixed = mt76x8_fixed_clocks, 841 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks), 842 .clk_factor = mt76x8_factor_clocks, 843 .num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks), 844 .clk_periph = mt76x8_pherip_clks, 845 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks), 846 }; 847 848 static const struct of_device_id mtmips_of_match[] = { 849 { 850 .compatible = "ralink,rt2880-reset", 851 .data = NULL, 852 }, 853 { 854 .compatible = "ralink,rt2880-sysc", 855 .data = &rt2880_clk_data, 856 }, 857 { 858 .compatible = "ralink,rt3050-sysc", 859 .data = &rt305x_clk_data, 860 }, 861 { 862 .compatible = "ralink,rt3052-sysc", 863 .data = &rt305x_clk_data, 864 }, 865 { 866 .compatible = "ralink,rt3352-sysc", 867 .data = &rt3352_clk_data, 868 }, 869 { 870 .compatible = "ralink,rt3883-sysc", 871 .data = &rt3883_clk_data, 872 }, 873 { 874 .compatible = "ralink,rt5350-sysc", 875 .data = &rt5350_clk_data, 876 }, 877 { 878 .compatible = "ralink,mt7620-sysc", 879 .data = &mt7620_clk_data, 880 }, 881 { 882 .compatible = "ralink,mt7628-sysc", 883 .data = &mt76x8_clk_data, 884 }, 885 { 886 .compatible = "ralink,mt7688-sysc", 887 .data = &mt76x8_clk_data, 888 }, 889 {} 890 }; 891 892 static void __init mtmips_clk_regs_init(struct device_node *node, 893 struct mtmips_clk_priv *priv) 894 { 895 u32 t; 896 897 if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) 898 return; 899 900 /* 901 * When the CPU goes into sleep mode, the BUS 902 * clock will be too low for USB to function properly. 903 * Adjust the busses fractional divider to fix this 904 */ 905 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); 906 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); 907 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; 908 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); 909 } 910 911 static void __init mtmips_clk_init(struct device_node *node) 912 { 913 const struct of_device_id *match; 914 const struct mtmips_clk_data *data; 915 struct mtmips_clk_priv *priv; 916 struct clk_hw_onecell_data *clk_data; 917 int ret, i, count; 918 919 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 920 if (!priv) 921 return; 922 923 priv->sysc = syscon_node_to_regmap(node); 924 if (IS_ERR(priv->sysc)) { 925 pr_err("Could not get sysc syscon regmap\n"); 926 goto free_clk_priv; 927 } 928 929 mtmips_clk_regs_init(node, priv); 930 931 match = of_match_node(mtmips_of_match, node); 932 if (WARN_ON(!match)) 933 return; 934 935 data = match->data; 936 priv->data = data; 937 count = priv->data->num_clk_base + priv->data->num_clk_fixed + 938 priv->data->num_clk_factor + priv->data->num_clk_periph; 939 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); 940 if (!clk_data) 941 goto free_clk_priv; 942 943 ret = mtmips_register_clocks(node, clk_data, priv); 944 if (ret) { 945 pr_err("Couldn't register top clocks\n"); 946 goto free_clk_data; 947 } 948 949 ret = mtmips_register_fixed_clocks(clk_data, priv); 950 if (ret) { 951 pr_err("Couldn't register fixed clocks\n"); 952 goto unreg_clk_top; 953 } 954 955 ret = mtmips_register_factor_clocks(clk_data, priv); 956 if (ret) { 957 pr_err("Couldn't register factor clocks\n"); 958 goto unreg_clk_fixed; 959 } 960 961 ret = mtmips_register_pherip_clocks(node, clk_data, priv); 962 if (ret) { 963 pr_err("Couldn't register peripheral clocks\n"); 964 goto unreg_clk_factor; 965 } 966 967 clk_data->num = count; 968 969 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 970 if (ret) { 971 pr_err("Couldn't add clk hw provider\n"); 972 goto unreg_clk_periph; 973 } 974 975 return; 976 977 unreg_clk_periph: 978 for (i = 0; i < priv->data->num_clk_periph; i++) { 979 struct mtmips_clk *sclk = &priv->data->clk_periph[i]; 980 981 clk_hw_unregister(&sclk->hw); 982 } 983 984 unreg_clk_factor: 985 for (i = 0; i < priv->data->num_clk_factor; i++) { 986 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; 987 988 clk_hw_unregister_fixed_factor(sclk->hw); 989 } 990 991 unreg_clk_fixed: 992 for (i = 0; i < priv->data->num_clk_fixed; i++) { 993 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; 994 995 clk_hw_unregister_fixed_rate(sclk->hw); 996 } 997 998 unreg_clk_top: 999 for (i = 0; i < priv->data->num_clk_base; i++) { 1000 struct mtmips_clk *sclk = &priv->data->clk_base[i]; 1001 1002 clk_hw_unregister(&sclk->hw); 1003 } 1004 1005 free_clk_data: 1006 kfree(clk_data); 1007 1008 free_clk_priv: 1009 kfree(priv); 1010 } 1011 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); 1012 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); 1013 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); 1014 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); 1015 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); 1016 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); 1017 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); 1018 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); 1019 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); 1020 1021 struct mtmips_rst { 1022 struct reset_controller_dev rcdev; 1023 struct regmap *sysc; 1024 }; 1025 1026 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) 1027 { 1028 return container_of(dev, struct mtmips_rst, rcdev); 1029 } 1030 1031 static int mtmips_assert_device(struct reset_controller_dev *rcdev, 1032 unsigned long id) 1033 { 1034 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1035 struct regmap *sysc = data->sysc; 1036 1037 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); 1038 } 1039 1040 static int mtmips_deassert_device(struct reset_controller_dev *rcdev, 1041 unsigned long id) 1042 { 1043 struct mtmips_rst *data = to_mtmips_rst(rcdev); 1044 struct regmap *sysc = data->sysc; 1045 1046 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); 1047 } 1048 1049 static int mtmips_reset_device(struct reset_controller_dev *rcdev, 1050 unsigned long id) 1051 { 1052 int ret; 1053 1054 ret = mtmips_assert_device(rcdev, id); 1055 if (ret < 0) 1056 return ret; 1057 1058 return mtmips_deassert_device(rcdev, id); 1059 } 1060 1061 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, 1062 const struct of_phandle_args *reset_spec) 1063 { 1064 unsigned long id = reset_spec->args[0]; 1065 1066 if (id == 0 || id >= rcdev->nr_resets) 1067 return -EINVAL; 1068 1069 return id; 1070 } 1071 1072 static const struct reset_control_ops reset_ops = { 1073 .reset = mtmips_reset_device, 1074 .assert = mtmips_assert_device, 1075 .deassert = mtmips_deassert_device 1076 }; 1077 1078 static int mtmips_reset_init(struct device *dev, struct regmap *sysc) 1079 { 1080 struct mtmips_rst *rst_data; 1081 1082 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); 1083 if (!rst_data) 1084 return -ENOMEM; 1085 1086 rst_data->sysc = sysc; 1087 rst_data->rcdev.ops = &reset_ops; 1088 rst_data->rcdev.owner = THIS_MODULE; 1089 rst_data->rcdev.nr_resets = 32; 1090 rst_data->rcdev.of_reset_n_cells = 1; 1091 rst_data->rcdev.of_xlate = mtmips_rst_xlate; 1092 rst_data->rcdev.of_node = dev_of_node(dev); 1093 1094 return devm_reset_controller_register(dev, &rst_data->rcdev); 1095 } 1096 1097 static int mtmips_clk_probe(struct platform_device *pdev) 1098 { 1099 struct device_node *np = pdev->dev.of_node; 1100 struct device *dev = &pdev->dev; 1101 struct mtmips_clk_priv *priv; 1102 int ret; 1103 1104 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1105 if (!priv) 1106 return -ENOMEM; 1107 1108 priv->sysc = syscon_node_to_regmap(np); 1109 if (IS_ERR(priv->sysc)) 1110 return dev_err_probe(dev, PTR_ERR(priv->sysc), 1111 "Could not get sysc syscon regmap\n"); 1112 1113 ret = mtmips_reset_init(dev, priv->sysc); 1114 if (ret) 1115 return dev_err_probe(dev, ret, "Could not init reset controller\n"); 1116 1117 return 0; 1118 } 1119 1120 static struct platform_driver mtmips_clk_driver = { 1121 .probe = mtmips_clk_probe, 1122 .driver = { 1123 .name = "mtmips-clk", 1124 .of_match_table = mtmips_of_match, 1125 }, 1126 }; 1127 1128 static int __init mtmips_clk_reset_init(void) 1129 { 1130 return platform_driver_register(&mtmips_clk_driver); 1131 } 1132 arch_initcall(mtmips_clk_reset_init); 1133