1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,sm8650-videocc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 DT_BI_TCXO, 24 }; 25 26 enum { 27 P_BI_TCXO, 28 P_VIDEO_CC_PLL0_OUT_MAIN, 29 P_VIDEO_CC_PLL1_OUT_MAIN, 30 }; 31 32 static const struct pll_vco lucid_ole_vco[] = { 33 { 249600000, 2300000000, 0 }, 34 }; 35 36 static struct alpha_pll_config video_cc_pll0_config = { 37 .l = 0x25, 38 .alpha = 0x8000, 39 .config_ctl_val = 0x20485699, 40 .config_ctl_hi_val = 0x00182261, 41 .config_ctl_hi1_val = 0x82aa299c, 42 .test_ctl_val = 0x00000000, 43 .test_ctl_hi_val = 0x00000003, 44 .test_ctl_hi1_val = 0x00009000, 45 .test_ctl_hi2_val = 0x00000034, 46 .user_ctl_val = 0x00000000, 47 .user_ctl_hi_val = 0x00000005, 48 }; 49 50 static struct clk_alpha_pll video_cc_pll0 = { 51 .offset = 0x0, 52 .config = &video_cc_pll0_config, 53 .vco_table = lucid_ole_vco, 54 .num_vco = ARRAY_SIZE(lucid_ole_vco), 55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 56 .clkr = { 57 .hw.init = &(const struct clk_init_data) { 58 .name = "video_cc_pll0", 59 .parent_data = &(const struct clk_parent_data) { 60 .index = DT_BI_TCXO, 61 }, 62 .num_parents = 1, 63 .ops = &clk_alpha_pll_lucid_evo_ops, 64 }, 65 }, 66 }; 67 68 static struct alpha_pll_config video_cc_pll1_config = { 69 .l = 0x36, 70 .alpha = 0xb000, 71 .config_ctl_val = 0x20485699, 72 .config_ctl_hi_val = 0x00182261, 73 .config_ctl_hi1_val = 0x82aa299c, 74 .test_ctl_val = 0x00000000, 75 .test_ctl_hi_val = 0x00000003, 76 .test_ctl_hi1_val = 0x00009000, 77 .test_ctl_hi2_val = 0x00000034, 78 .user_ctl_val = 0x00000000, 79 .user_ctl_hi_val = 0x00000005, 80 }; 81 82 static struct clk_alpha_pll video_cc_pll1 = { 83 .offset = 0x1000, 84 .config = &video_cc_pll1_config, 85 .vco_table = lucid_ole_vco, 86 .num_vco = ARRAY_SIZE(lucid_ole_vco), 87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 88 .clkr = { 89 .hw.init = &(const struct clk_init_data) { 90 .name = "video_cc_pll1", 91 .parent_data = &(const struct clk_parent_data) { 92 .index = DT_BI_TCXO, 93 }, 94 .num_parents = 1, 95 .ops = &clk_alpha_pll_lucid_evo_ops, 96 }, 97 }, 98 }; 99 100 static const struct parent_map video_cc_parent_map_0[] = { 101 { P_BI_TCXO, 0 }, 102 { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, 103 }; 104 105 static const struct clk_parent_data video_cc_parent_data_0[] = { 106 { .index = DT_BI_TCXO }, 107 { .hw = &video_cc_pll0.clkr.hw }, 108 }; 109 110 static const struct parent_map video_cc_parent_map_1[] = { 111 { P_BI_TCXO, 0 }, 112 { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, 113 }; 114 115 static const struct clk_parent_data video_cc_parent_data_1[] = { 116 { .index = DT_BI_TCXO }, 117 { .hw = &video_cc_pll1.clkr.hw }, 118 }; 119 120 static const struct parent_map video_cc_parent_map_2[] = { 121 { P_BI_TCXO, 0 }, 122 }; 123 124 static const struct clk_parent_data video_cc_parent_data_2[] = { 125 { .index = DT_BI_TCXO }, 126 }; 127 128 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { 129 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 130 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 131 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 132 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 133 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 134 { } 135 }; 136 137 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = { 138 F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 139 F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 140 F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 141 F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 142 F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 143 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 144 { } 145 }; 146 147 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_x1e80100[] = { 148 F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 149 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 150 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 151 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 152 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 153 F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 154 { } 155 }; 156 157 static struct clk_rcg2 video_cc_mvs0_clk_src = { 158 .cmd_rcgr = 0x8000, 159 .mnd_width = 0, 160 .hid_width = 5, 161 .parent_map = video_cc_parent_map_0, 162 .freq_tbl = ftbl_video_cc_mvs0_clk_src, 163 .clkr.hw.init = &(const struct clk_init_data) { 164 .name = "video_cc_mvs0_clk_src", 165 .parent_data = video_cc_parent_data_0, 166 .num_parents = ARRAY_SIZE(video_cc_parent_data_0), 167 .flags = CLK_SET_RATE_PARENT, 168 .ops = &clk_rcg2_shared_ops, 169 }, 170 }; 171 172 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { 173 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 174 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 175 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 176 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 177 { } 178 }; 179 180 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { 181 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 182 F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 183 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 184 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 185 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 186 { } 187 }; 188 189 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_x1e80100[] = { 190 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 191 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 192 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 193 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 194 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 195 { } 196 }; 197 198 static struct clk_rcg2 video_cc_mvs1_clk_src = { 199 .cmd_rcgr = 0x8018, 200 .mnd_width = 0, 201 .hid_width = 5, 202 .parent_map = video_cc_parent_map_1, 203 .freq_tbl = ftbl_video_cc_mvs1_clk_src, 204 .clkr.hw.init = &(const struct clk_init_data) { 205 .name = "video_cc_mvs1_clk_src", 206 .parent_data = video_cc_parent_data_1, 207 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 208 .flags = CLK_SET_RATE_PARENT, 209 .ops = &clk_rcg2_shared_ops, 210 }, 211 }; 212 213 static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { 214 F(19200000, P_BI_TCXO, 1, 0, 0), 215 { } 216 }; 217 218 static struct clk_rcg2 video_cc_xo_clk_src = { 219 .cmd_rcgr = 0x810c, 220 .mnd_width = 0, 221 .hid_width = 5, 222 .parent_map = video_cc_parent_map_2, 223 .freq_tbl = ftbl_video_cc_xo_clk_src, 224 .clkr.hw.init = &(const struct clk_init_data) { 225 .name = "video_cc_xo_clk_src", 226 .parent_data = video_cc_parent_data_2, 227 .num_parents = ARRAY_SIZE(video_cc_parent_data_2), 228 .flags = CLK_SET_RATE_PARENT, 229 .ops = &clk_rcg2_shared_ops, 230 }, 231 }; 232 233 static struct clk_regmap_div video_cc_mvs0_div_clk_src = { 234 .reg = 0x80c4, 235 .shift = 0, 236 .width = 4, 237 .clkr.hw.init = &(const struct clk_init_data) { 238 .name = "video_cc_mvs0_div_clk_src", 239 .parent_hws = (const struct clk_hw*[]) { 240 &video_cc_mvs0_clk_src.clkr.hw, 241 }, 242 .num_parents = 1, 243 .flags = CLK_SET_RATE_PARENT, 244 .ops = &clk_regmap_div_ro_ops, 245 }, 246 }; 247 248 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { 249 .reg = 0x8070, 250 .shift = 0, 251 .width = 4, 252 .clkr.hw.init = &(const struct clk_init_data) { 253 .name = "video_cc_mvs0c_div2_div_clk_src", 254 .parent_hws = (const struct clk_hw*[]) { 255 &video_cc_mvs0_clk_src.clkr.hw, 256 }, 257 .num_parents = 1, 258 .flags = CLK_SET_RATE_PARENT, 259 .ops = &clk_regmap_div_ro_ops, 260 }, 261 }; 262 263 static struct clk_regmap_div video_cc_mvs1_div_clk_src = { 264 .reg = 0x80ec, 265 .shift = 0, 266 .width = 4, 267 .clkr.hw.init = &(const struct clk_init_data) { 268 .name = "video_cc_mvs1_div_clk_src", 269 .parent_hws = (const struct clk_hw*[]) { 270 &video_cc_mvs1_clk_src.clkr.hw, 271 }, 272 .num_parents = 1, 273 .flags = CLK_SET_RATE_PARENT, 274 .ops = &clk_regmap_div_ro_ops, 275 }, 276 }; 277 278 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { 279 .reg = 0x809c, 280 .shift = 0, 281 .width = 4, 282 .clkr.hw.init = &(const struct clk_init_data) { 283 .name = "video_cc_mvs1c_div2_div_clk_src", 284 .parent_hws = (const struct clk_hw*[]) { 285 &video_cc_mvs1_clk_src.clkr.hw, 286 }, 287 .num_parents = 1, 288 .flags = CLK_SET_RATE_PARENT, 289 .ops = &clk_regmap_div_ro_ops, 290 }, 291 }; 292 293 static struct clk_branch video_cc_mvs0_clk = { 294 .halt_reg = 0x80b8, 295 .halt_check = BRANCH_HALT_SKIP, 296 .hwcg_reg = 0x80b8, 297 .hwcg_bit = 1, 298 .clkr = { 299 .enable_reg = 0x80b8, 300 .enable_mask = BIT(0), 301 .hw.init = &(const struct clk_init_data) { 302 .name = "video_cc_mvs0_clk", 303 .parent_hws = (const struct clk_hw*[]) { 304 &video_cc_mvs0_div_clk_src.clkr.hw, 305 }, 306 .num_parents = 1, 307 .flags = CLK_SET_RATE_PARENT, 308 .ops = &clk_branch2_ops, 309 }, 310 }, 311 }; 312 313 static struct clk_branch video_cc_mvs0_shift_clk = { 314 .halt_reg = 0x8128, 315 .halt_check = BRANCH_HALT_VOTED, 316 .hwcg_reg = 0x8128, 317 .hwcg_bit = 1, 318 .clkr = { 319 .enable_reg = 0x8128, 320 .enable_mask = BIT(0), 321 .hw.init = &(const struct clk_init_data) { 322 .name = "video_cc_mvs0_shift_clk", 323 .parent_hws = (const struct clk_hw*[]) { 324 &video_cc_xo_clk_src.clkr.hw, 325 }, 326 .num_parents = 1, 327 .flags = CLK_SET_RATE_PARENT, 328 .ops = &clk_branch2_ops, 329 }, 330 }, 331 }; 332 333 static struct clk_branch video_cc_mvs0c_clk = { 334 .halt_reg = 0x8064, 335 .halt_check = BRANCH_HALT, 336 .clkr = { 337 .enable_reg = 0x8064, 338 .enable_mask = BIT(0), 339 .hw.init = &(const struct clk_init_data) { 340 .name = "video_cc_mvs0c_clk", 341 .parent_hws = (const struct clk_hw*[]) { 342 &video_cc_mvs0c_div2_div_clk_src.clkr.hw, 343 }, 344 .num_parents = 1, 345 .flags = CLK_SET_RATE_PARENT, 346 .ops = &clk_branch2_ops, 347 }, 348 }, 349 }; 350 351 static struct clk_branch video_cc_mvs0c_shift_clk = { 352 .halt_reg = 0x812c, 353 .halt_check = BRANCH_HALT_VOTED, 354 .hwcg_reg = 0x812c, 355 .hwcg_bit = 1, 356 .clkr = { 357 .enable_reg = 0x812c, 358 .enable_mask = BIT(0), 359 .hw.init = &(const struct clk_init_data) { 360 .name = "video_cc_mvs0c_shift_clk", 361 .parent_hws = (const struct clk_hw*[]) { 362 &video_cc_xo_clk_src.clkr.hw, 363 }, 364 .num_parents = 1, 365 .flags = CLK_SET_RATE_PARENT, 366 .ops = &clk_branch2_ops, 367 }, 368 }, 369 }; 370 371 static struct clk_branch video_cc_mvs1_clk = { 372 .halt_reg = 0x80e0, 373 .halt_check = BRANCH_HALT_SKIP, 374 .hwcg_reg = 0x80e0, 375 .hwcg_bit = 1, 376 .clkr = { 377 .enable_reg = 0x80e0, 378 .enable_mask = BIT(0), 379 .hw.init = &(const struct clk_init_data) { 380 .name = "video_cc_mvs1_clk", 381 .parent_hws = (const struct clk_hw*[]) { 382 &video_cc_mvs1_div_clk_src.clkr.hw, 383 }, 384 .num_parents = 1, 385 .flags = CLK_SET_RATE_PARENT, 386 .ops = &clk_branch2_ops, 387 }, 388 }, 389 }; 390 391 static struct clk_branch video_cc_mvs1_shift_clk = { 392 .halt_reg = 0x8130, 393 .halt_check = BRANCH_HALT_VOTED, 394 .hwcg_reg = 0x8130, 395 .hwcg_bit = 1, 396 .clkr = { 397 .enable_reg = 0x8130, 398 .enable_mask = BIT(0), 399 .hw.init = &(const struct clk_init_data) { 400 .name = "video_cc_mvs1_shift_clk", 401 .parent_hws = (const struct clk_hw*[]) { 402 &video_cc_xo_clk_src.clkr.hw, 403 }, 404 .num_parents = 1, 405 .flags = CLK_SET_RATE_PARENT, 406 .ops = &clk_branch2_ops, 407 }, 408 }, 409 }; 410 411 static struct clk_branch video_cc_mvs1c_clk = { 412 .halt_reg = 0x8090, 413 .halt_check = BRANCH_HALT, 414 .clkr = { 415 .enable_reg = 0x8090, 416 .enable_mask = BIT(0), 417 .hw.init = &(const struct clk_init_data) { 418 .name = "video_cc_mvs1c_clk", 419 .parent_hws = (const struct clk_hw*[]) { 420 &video_cc_mvs1c_div2_div_clk_src.clkr.hw, 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 .ops = &clk_branch2_ops, 425 }, 426 }, 427 }; 428 429 static struct clk_branch video_cc_mvs1c_shift_clk = { 430 .halt_reg = 0x8134, 431 .halt_check = BRANCH_HALT_VOTED, 432 .hwcg_reg = 0x8134, 433 .hwcg_bit = 1, 434 .clkr = { 435 .enable_reg = 0x8134, 436 .enable_mask = BIT(0), 437 .hw.init = &(const struct clk_init_data) { 438 .name = "video_cc_mvs1c_shift_clk", 439 .parent_hws = (const struct clk_hw*[]) { 440 &video_cc_xo_clk_src.clkr.hw, 441 }, 442 .num_parents = 1, 443 .flags = CLK_SET_RATE_PARENT, 444 .ops = &clk_branch2_ops, 445 }, 446 }, 447 }; 448 449 static struct gdsc video_cc_mvs0c_gdsc = { 450 .gdscr = 0x804c, 451 .en_rest_wait_val = 0x2, 452 .en_few_wait_val = 0x2, 453 .clk_dis_wait_val = 0x6, 454 .pd = { 455 .name = "video_cc_mvs0c_gdsc", 456 }, 457 .pwrsts = PWRSTS_OFF_ON, 458 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 459 }; 460 461 static struct gdsc video_cc_mvs0_gdsc = { 462 .gdscr = 0x80a4, 463 .en_rest_wait_val = 0x2, 464 .en_few_wait_val = 0x2, 465 .clk_dis_wait_val = 0x6, 466 .pd = { 467 .name = "video_cc_mvs0_gdsc", 468 }, 469 .pwrsts = PWRSTS_OFF_ON, 470 .parent = &video_cc_mvs0c_gdsc.pd, 471 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 472 }; 473 474 static struct gdsc video_cc_mvs1c_gdsc = { 475 .gdscr = 0x8078, 476 .en_rest_wait_val = 0x2, 477 .en_few_wait_val = 0x2, 478 .clk_dis_wait_val = 0x6, 479 .pd = { 480 .name = "video_cc_mvs1c_gdsc", 481 }, 482 .pwrsts = PWRSTS_OFF_ON, 483 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 484 }; 485 486 static struct gdsc video_cc_mvs1_gdsc = { 487 .gdscr = 0x80cc, 488 .en_rest_wait_val = 0x2, 489 .en_few_wait_val = 0x2, 490 .clk_dis_wait_val = 0x6, 491 .pd = { 492 .name = "video_cc_mvs1_gdsc", 493 }, 494 .pwrsts = PWRSTS_OFF_ON, 495 .parent = &video_cc_mvs1c_gdsc.pd, 496 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER, 497 }; 498 499 static struct clk_regmap *video_cc_sm8550_clocks[] = { 500 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, 501 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, 502 [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, 503 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, 504 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, 505 [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, 506 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, 507 [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, 508 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, 509 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, 510 [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, 511 [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, 512 [VIDEO_CC_XO_CLK_SRC] = NULL, 513 }; 514 515 static struct gdsc *video_cc_sm8550_gdscs[] = { 516 [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, 517 [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, 518 [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc, 519 [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, 520 }; 521 522 static const struct qcom_reset_map video_cc_sm8550_resets[] = { 523 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 }, 524 [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 }, 525 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 }, 526 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 }, 527 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, 528 [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, 529 [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, 530 [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, 531 }; 532 533 static struct clk_alpha_pll *video_cc_sm8550_plls[] = { 534 &video_cc_pll0, 535 &video_cc_pll1, 536 }; 537 538 static const u32 video_cc_sm8550_critical_cbcrs[] = { 539 0x80f4, /* VIDEO_CC_AHB_CLK */ 540 0x8124, /* VIDEO_CC_XO_CLK */ 541 0x8140, /* VIDEO_CC_SLEEP_CLK */ 542 }; 543 544 static const u32 video_cc_sm8650_critical_cbcrs[] = { 545 0x80f4, /* VIDEO_CC_AHB_CLK */ 546 0x8124, /* VIDEO_CC_XO_CLK */ 547 0x8150, /* VIDEO_CC_SLEEP_CLK */ 548 }; 549 550 static const struct regmap_config video_cc_sm8550_regmap_config = { 551 .reg_bits = 32, 552 .reg_stride = 4, 553 .val_bits = 32, 554 .max_register = 0x9f4c, 555 .fast_io = true, 556 }; 557 558 static struct qcom_cc_driver_data video_cc_sm8550_driver_data = { 559 .alpha_plls = video_cc_sm8550_plls, 560 .num_alpha_plls = ARRAY_SIZE(video_cc_sm8550_plls), 561 .clk_cbcrs = video_cc_sm8550_critical_cbcrs, 562 .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8550_critical_cbcrs), 563 }; 564 565 static const struct qcom_cc_desc video_cc_sm8550_desc = { 566 .config = &video_cc_sm8550_regmap_config, 567 .clks = video_cc_sm8550_clocks, 568 .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks), 569 .resets = video_cc_sm8550_resets, 570 .num_resets = ARRAY_SIZE(video_cc_sm8550_resets), 571 .gdscs = video_cc_sm8550_gdscs, 572 .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs), 573 .use_rpm = true, 574 .driver_data = &video_cc_sm8550_driver_data, 575 }; 576 577 static const struct of_device_id video_cc_sm8550_match_table[] = { 578 { .compatible = "qcom,sm8550-videocc" }, 579 { .compatible = "qcom,sm8650-videocc" }, 580 { .compatible = "qcom,x1e80100-videocc" }, 581 { } 582 }; 583 MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); 584 585 static int video_cc_sm8550_probe(struct platform_device *pdev) 586 { 587 if (of_device_is_compatible(pdev->dev.of_node, "qcom,x1e80100-videocc")) { 588 video_cc_pll0_config.l = 0x1e; 589 video_cc_pll0_config.alpha = 0x0000; 590 video_cc_pll1_config.l = 0x2b; 591 video_cc_pll1_config.alpha = 0xc000; 592 video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_x1e80100; 593 video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_x1e80100; 594 } 595 596 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { 597 video_cc_pll0_config.l = 0x1e; 598 video_cc_pll0_config.alpha = 0xa000; 599 video_cc_pll1_config.l = 0x2b; 600 video_cc_pll1_config.alpha = 0xc000; 601 video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650; 602 video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650; 603 video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr; 604 video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr; 605 video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; 606 video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; 607 video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; 608 609 video_cc_sm8550_driver_data.clk_cbcrs = video_cc_sm8650_critical_cbcrs; 610 video_cc_sm8550_driver_data.num_clk_cbcrs = 611 ARRAY_SIZE(video_cc_sm8650_critical_cbcrs); 612 } 613 614 return qcom_cc_probe(pdev, &video_cc_sm8550_desc); 615 } 616 617 static struct platform_driver video_cc_sm8550_driver = { 618 .probe = video_cc_sm8550_probe, 619 .driver = { 620 .name = "video_cc-sm8550", 621 .of_match_table = video_cc_sm8550_match_table, 622 }, 623 }; 624 625 module_platform_driver(video_cc_sm8550_driver); 626 627 MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver"); 628 MODULE_LICENSE("GPL"); 629