1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,videocc-sm8150.h> 12 13 #include "common.h" 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "reset.h" 19 #include "gdsc.h" 20 21 enum { 22 P_BI_TCXO, 23 P_VIDEO_PLL0_OUT_MAIN, 24 }; 25 26 static struct pll_vco trion_vco[] = { 27 { 249600000, 2000000000, 0 }, 28 }; 29 30 static struct alpha_pll_config video_pll0_config = { 31 .l = 0x14, 32 .alpha = 0xD555, 33 .config_ctl_val = 0x20485699, 34 .config_ctl_hi_val = 0x00002267, 35 .config_ctl_hi1_val = 0x00000024, 36 .user_ctl_val = 0x00000000, 37 .user_ctl_hi_val = 0x00000805, 38 .user_ctl_hi1_val = 0x000000D0, 39 }; 40 41 static struct clk_alpha_pll video_pll0 = { 42 .offset = 0x42c, 43 .vco_table = trion_vco, 44 .num_vco = ARRAY_SIZE(trion_vco), 45 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 46 .clkr = { 47 .hw.init = &(struct clk_init_data){ 48 .name = "video_pll0", 49 .parent_data = &(const struct clk_parent_data){ 50 .fw_name = "bi_tcxo", 51 }, 52 .num_parents = 1, 53 .ops = &clk_alpha_pll_trion_ops, 54 }, 55 }, 56 }; 57 58 static const struct parent_map video_cc_parent_map_0[] = { 59 { P_BI_TCXO, 0 }, 60 { P_VIDEO_PLL0_OUT_MAIN, 1 }, 61 }; 62 63 static const struct clk_parent_data video_cc_parent_data_0[] = { 64 { .fw_name = "bi_tcxo" }, 65 { .hw = &video_pll0.clkr.hw }, 66 }; 67 68 static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = { 69 F(19200000, P_BI_TCXO, 1, 0, 0), 70 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 71 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 72 F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 73 F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 74 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 75 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 76 { } 77 }; 78 79 static struct clk_rcg2 video_cc_iris_clk_src = { 80 .cmd_rcgr = 0x7f0, 81 .mnd_width = 0, 82 .hid_width = 5, 83 .parent_map = video_cc_parent_map_0, 84 .freq_tbl = ftbl_video_cc_iris_clk_src, 85 .clkr.hw.init = &(struct clk_init_data){ 86 .name = "video_cc_iris_clk_src", 87 .parent_data = video_cc_parent_data_0, 88 .num_parents = ARRAY_SIZE(video_cc_parent_data_0), 89 .flags = CLK_SET_RATE_PARENT, 90 .ops = &clk_rcg2_shared_ops, 91 }, 92 }; 93 94 static struct clk_branch video_cc_iris_ahb_clk = { 95 .halt_reg = 0x8f4, 96 .halt_check = BRANCH_VOTED, 97 .clkr = { 98 .enable_reg = 0x8f4, 99 .enable_mask = BIT(0), 100 .hw.init = &(struct clk_init_data){ 101 .name = "video_cc_iris_ahb_clk", 102 .parent_hws = (const struct clk_hw*[]){ 103 &video_cc_iris_clk_src.clkr.hw, 104 }, 105 .num_parents = 1, 106 .flags = CLK_SET_RATE_PARENT, 107 .ops = &clk_branch2_ops, 108 }, 109 }, 110 }; 111 112 static struct clk_branch video_cc_mvs0_core_clk = { 113 .halt_reg = 0x890, 114 .halt_check = BRANCH_VOTED, 115 .clkr = { 116 .enable_reg = 0x890, 117 .enable_mask = BIT(0), 118 .hw.init = &(struct clk_init_data){ 119 .name = "video_cc_mvs0_core_clk", 120 .parent_hws = (const struct clk_hw*[]){ 121 &video_cc_iris_clk_src.clkr.hw, 122 }, 123 .num_parents = 1, 124 .flags = CLK_SET_RATE_PARENT, 125 .ops = &clk_branch2_ops, 126 }, 127 }, 128 }; 129 130 static struct clk_branch video_cc_mvs1_core_clk = { 131 .halt_reg = 0x8d0, 132 .halt_check = BRANCH_VOTED, 133 .clkr = { 134 .enable_reg = 0x8d0, 135 .enable_mask = BIT(0), 136 .hw.init = &(struct clk_init_data){ 137 .name = "video_cc_mvs1_core_clk", 138 .parent_hws = (const struct clk_hw*[]){ 139 &video_cc_iris_clk_src.clkr.hw, 140 }, 141 .num_parents = 1, 142 .flags = CLK_SET_RATE_PARENT, 143 .ops = &clk_branch2_ops, 144 }, 145 }, 146 }; 147 148 static struct clk_branch video_cc_mvsc_core_clk = { 149 .halt_reg = 0x850, 150 .halt_check = BRANCH_HALT, 151 .clkr = { 152 .enable_reg = 0x850, 153 .enable_mask = BIT(0), 154 .hw.init = &(struct clk_init_data){ 155 .name = "video_cc_mvsc_core_clk", 156 .parent_hws = (const struct clk_hw*[]){ 157 &video_cc_iris_clk_src.clkr.hw, 158 }, 159 .num_parents = 1, 160 .flags = CLK_SET_RATE_PARENT, 161 .ops = &clk_branch2_ops, 162 }, 163 }, 164 }; 165 166 static struct gdsc venus_gdsc = { 167 .gdscr = 0x814, 168 .pd = { 169 .name = "venus_gdsc", 170 }, 171 .flags = 0, 172 .pwrsts = PWRSTS_OFF_ON, 173 }; 174 175 static struct gdsc vcodec0_gdsc = { 176 .gdscr = 0x874, 177 .pd = { 178 .name = "vcodec0_gdsc", 179 }, 180 .flags = HW_CTRL, 181 .pwrsts = PWRSTS_OFF_ON, 182 }; 183 184 static struct gdsc vcodec1_gdsc = { 185 .gdscr = 0x8b4, 186 .pd = { 187 .name = "vcodec1_gdsc", 188 }, 189 .flags = HW_CTRL, 190 .pwrsts = PWRSTS_OFF_ON, 191 }; 192 static struct clk_regmap *video_cc_sm8150_clocks[] = { 193 [VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr, 194 [VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr, 195 [VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr, 196 [VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr, 197 [VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr, 198 [VIDEO_CC_PLL0] = &video_pll0.clkr, 199 }; 200 201 static struct gdsc *video_cc_sm8150_gdscs[] = { 202 [VENUS_GDSC] = &venus_gdsc, 203 [VCODEC0_GDSC] = &vcodec0_gdsc, 204 [VCODEC1_GDSC] = &vcodec1_gdsc, 205 }; 206 207 static const struct regmap_config video_cc_sm8150_regmap_config = { 208 .reg_bits = 32, 209 .reg_stride = 4, 210 .val_bits = 32, 211 .max_register = 0xb94, 212 .fast_io = true, 213 }; 214 215 static const struct qcom_reset_map video_cc_sm8150_resets[] = { 216 [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 }, 217 }; 218 219 static const struct qcom_cc_desc video_cc_sm8150_desc = { 220 .config = &video_cc_sm8150_regmap_config, 221 .clks = video_cc_sm8150_clocks, 222 .num_clks = ARRAY_SIZE(video_cc_sm8150_clocks), 223 .resets = video_cc_sm8150_resets, 224 .num_resets = ARRAY_SIZE(video_cc_sm8150_resets), 225 .gdscs = video_cc_sm8150_gdscs, 226 .num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs), 227 }; 228 229 static const struct of_device_id video_cc_sm8150_match_table[] = { 230 { .compatible = "qcom,sm8150-videocc" }, 231 { } 232 }; 233 MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table); 234 235 static int video_cc_sm8150_probe(struct platform_device *pdev) 236 { 237 struct regmap *regmap; 238 239 regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc); 240 if (IS_ERR(regmap)) 241 return PTR_ERR(regmap); 242 243 clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config); 244 245 /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */ 246 regmap_update_bits(regmap, 0x984, 0x1, 0x1); 247 248 return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap); 249 } 250 251 static struct platform_driver video_cc_sm8150_driver = { 252 .probe = video_cc_sm8150_probe, 253 .driver = { 254 .name = "video_cc-sm8150", 255 .of_match_table = video_cc_sm8150_match_table, 256 }, 257 }; 258 259 static int __init video_cc_sm8150_init(void) 260 { 261 return platform_driver_register(&video_cc_sm8150_driver); 262 } 263 subsys_initcall(video_cc_sm8150_init); 264 265 static void __exit video_cc_sm8150_exit(void) 266 { 267 platform_driver_unregister(&video_cc_sm8150_driver); 268 } 269 module_exit(video_cc_sm8150_exit); 270 271 MODULE_LICENSE("GPL v2"); 272 MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver"); 273