1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,videocc-sc7180.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "common.h" 18 #include "gdsc.h" 19 20 enum { 21 P_BI_TCXO, 22 P_CHIP_SLEEP_CLK, 23 P_CORE_BI_PLL_TEST_SE, 24 P_VIDEO_PLL0_OUT_EVEN, 25 P_VIDEO_PLL0_OUT_MAIN, 26 P_VIDEO_PLL0_OUT_ODD, 27 }; 28 29 static const struct pll_vco fabia_vco[] = { 30 { 249600000, 2000000000, 0 }, 31 }; 32 33 static struct clk_alpha_pll video_pll0 = { 34 .offset = 0x42c, 35 .vco_table = fabia_vco, 36 .num_vco = ARRAY_SIZE(fabia_vco), 37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 38 .clkr = { 39 .hw.init = &(struct clk_init_data){ 40 .name = "video_pll0", 41 .parent_data = &(const struct clk_parent_data){ 42 .fw_name = "bi_tcxo", 43 }, 44 .num_parents = 1, 45 .ops = &clk_alpha_pll_fabia_ops, 46 }, 47 }, 48 }; 49 50 static const struct parent_map video_cc_parent_map_1[] = { 51 { P_BI_TCXO, 0 }, 52 { P_VIDEO_PLL0_OUT_MAIN, 1 }, 53 { P_CORE_BI_PLL_TEST_SE, 7 }, 54 }; 55 56 static const struct clk_parent_data video_cc_parent_data_1[] = { 57 { .fw_name = "bi_tcxo" }, 58 { .hw = &video_pll0.clkr.hw }, 59 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 60 }; 61 62 static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { 63 F(19200000, P_BI_TCXO, 1, 0, 0), 64 F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), 65 F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), 66 F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 67 F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 68 F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), 69 { } 70 }; 71 72 static struct clk_rcg2 video_cc_venus_clk_src = { 73 .cmd_rcgr = 0x7f0, 74 .mnd_width = 0, 75 .hid_width = 5, 76 .parent_map = video_cc_parent_map_1, 77 .freq_tbl = ftbl_video_cc_venus_clk_src, 78 .clkr.hw.init = &(struct clk_init_data){ 79 .name = "video_cc_venus_clk_src", 80 .parent_data = video_cc_parent_data_1, 81 .num_parents = 3, 82 .flags = CLK_SET_RATE_PARENT, 83 .ops = &clk_rcg2_shared_ops, 84 }, 85 }; 86 87 static struct clk_branch video_cc_vcodec0_axi_clk = { 88 .halt_reg = 0x9ec, 89 .halt_check = BRANCH_HALT, 90 .clkr = { 91 .enable_reg = 0x9ec, 92 .enable_mask = BIT(0), 93 .hw.init = &(struct clk_init_data){ 94 .name = "video_cc_vcodec0_axi_clk", 95 .ops = &clk_branch2_ops, 96 }, 97 }, 98 }; 99 100 static struct clk_branch video_cc_vcodec0_core_clk = { 101 .halt_reg = 0x890, 102 .halt_check = BRANCH_HALT, 103 .clkr = { 104 .enable_reg = 0x890, 105 .enable_mask = BIT(0), 106 .hw.init = &(struct clk_init_data){ 107 .name = "video_cc_vcodec0_core_clk", 108 .parent_data = &(const struct clk_parent_data){ 109 .hw = &video_cc_venus_clk_src.clkr.hw, 110 }, 111 .num_parents = 1, 112 .flags = CLK_SET_RATE_PARENT, 113 .ops = &clk_branch2_ops, 114 }, 115 }, 116 }; 117 118 static struct clk_branch video_cc_venus_ahb_clk = { 119 .halt_reg = 0xa4c, 120 .halt_check = BRANCH_HALT, 121 .clkr = { 122 .enable_reg = 0xa4c, 123 .enable_mask = BIT(0), 124 .hw.init = &(struct clk_init_data){ 125 .name = "video_cc_venus_ahb_clk", 126 .ops = &clk_branch2_ops, 127 }, 128 }, 129 }; 130 131 static struct clk_branch video_cc_venus_ctl_axi_clk = { 132 .halt_reg = 0x9cc, 133 .halt_check = BRANCH_HALT, 134 .clkr = { 135 .enable_reg = 0x9cc, 136 .enable_mask = BIT(0), 137 .hw.init = &(struct clk_init_data){ 138 .name = "video_cc_venus_ctl_axi_clk", 139 .ops = &clk_branch2_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_branch video_cc_venus_ctl_core_clk = { 145 .halt_reg = 0x850, 146 .halt_check = BRANCH_HALT, 147 .clkr = { 148 .enable_reg = 0x850, 149 .enable_mask = BIT(0), 150 .hw.init = &(struct clk_init_data){ 151 .name = "video_cc_venus_ctl_core_clk", 152 .parent_data = &(const struct clk_parent_data){ 153 .hw = &video_cc_venus_clk_src.clkr.hw, 154 }, 155 .num_parents = 1, 156 .flags = CLK_SET_RATE_PARENT, 157 .ops = &clk_branch2_ops, 158 }, 159 }, 160 }; 161 162 static struct gdsc venus_gdsc = { 163 .gdscr = 0x814, 164 .pd = { 165 .name = "venus_gdsc", 166 }, 167 .pwrsts = PWRSTS_OFF_ON, 168 }; 169 170 static struct gdsc vcodec0_gdsc = { 171 .gdscr = 0x874, 172 .pd = { 173 .name = "vcodec0_gdsc", 174 }, 175 .flags = HW_CTRL, 176 .pwrsts = PWRSTS_OFF_ON, 177 }; 178 179 static struct clk_regmap *video_cc_sc7180_clocks[] = { 180 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, 181 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, 182 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, 183 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, 184 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, 185 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, 186 [VIDEO_PLL0] = &video_pll0.clkr, 187 }; 188 189 static struct gdsc *video_cc_sc7180_gdscs[] = { 190 [VENUS_GDSC] = &venus_gdsc, 191 [VCODEC0_GDSC] = &vcodec0_gdsc, 192 }; 193 194 static const struct regmap_config video_cc_sc7180_regmap_config = { 195 .reg_bits = 32, 196 .reg_stride = 4, 197 .val_bits = 32, 198 .max_register = 0xb94, 199 .fast_io = true, 200 }; 201 202 static const struct qcom_cc_desc video_cc_sc7180_desc = { 203 .config = &video_cc_sc7180_regmap_config, 204 .clks = video_cc_sc7180_clocks, 205 .num_clks = ARRAY_SIZE(video_cc_sc7180_clocks), 206 .gdscs = video_cc_sc7180_gdscs, 207 .num_gdscs = ARRAY_SIZE(video_cc_sc7180_gdscs), 208 }; 209 210 static const struct of_device_id video_cc_sc7180_match_table[] = { 211 { .compatible = "qcom,sc7180-videocc" }, 212 { } 213 }; 214 MODULE_DEVICE_TABLE(of, video_cc_sc7180_match_table); 215 216 static int video_cc_sc7180_probe(struct platform_device *pdev) 217 { 218 struct regmap *regmap; 219 struct alpha_pll_config video_pll0_config = {}; 220 221 regmap = qcom_cc_map(pdev, &video_cc_sc7180_desc); 222 if (IS_ERR(regmap)) 223 return PTR_ERR(regmap); 224 225 video_pll0_config.l = 0x1f; 226 video_pll0_config.alpha = 0x4000; 227 video_pll0_config.user_ctl_val = 0x00000001; 228 video_pll0_config.user_ctl_hi_val = 0x00004805; 229 230 clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); 231 232 /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */ 233 regmap_update_bits(regmap, 0x984, 0x1, 0x1); 234 235 return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap); 236 } 237 238 static struct platform_driver video_cc_sc7180_driver = { 239 .probe = video_cc_sc7180_probe, 240 .driver = { 241 .name = "sc7180-videocc", 242 .of_match_table = video_cc_sc7180_match_table, 243 }, 244 }; 245 246 static int __init video_cc_sc7180_init(void) 247 { 248 return platform_driver_register(&video_cc_sc7180_driver); 249 } 250 subsys_initcall(video_cc_sc7180_init); 251 252 static void __exit video_cc_sc7180_exit(void) 253 { 254 platform_driver_unregister(&video_cc_sc7180_driver); 255 } 256 module_exit(video_cc_sc7180_exit); 257 258 MODULE_LICENSE("GPL v2"); 259 MODULE_DESCRIPTION("QTI VIDEOCC SC7180 Driver"); 260