1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 11 #include <dt-bindings/clock/qcom,glymur-videocc.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-pll.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-regmap-mux.h" 20 #include "common.h" 21 #include "gdsc.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO, 26 DT_BI_TCXO_AO, 27 DT_SLEEP_CLK, 28 }; 29 30 enum { 31 P_BI_TCXO, 32 P_SLEEP_CLK, 33 P_VIDEO_CC_PLL0_OUT_MAIN, 34 }; 35 36 static const struct pll_vco taycan_eko_t_vco[] = { 37 { 249600000, 2500000000, 0 }, 38 }; 39 40 /* 720.0 MHz Configuration */ 41 static const struct alpha_pll_config video_cc_pll0_config = { 42 .l = 0x25, 43 .alpha = 0x8000, 44 .config_ctl_val = 0x25c400e7, 45 .config_ctl_hi_val = 0x0a8060e0, 46 .config_ctl_hi1_val = 0xf51dea20, 47 .user_ctl_val = 0x00000008, 48 .user_ctl_hi_val = 0x00000002, 49 }; 50 51 static struct clk_alpha_pll video_cc_pll0 = { 52 .offset = 0x0, 53 .config = &video_cc_pll0_config, 54 .vco_table = taycan_eko_t_vco, 55 .num_vco = ARRAY_SIZE(taycan_eko_t_vco), 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 57 .clkr = { 58 .hw.init = &(const struct clk_init_data) { 59 .name = "video_cc_pll0", 60 .parent_data = &(const struct clk_parent_data) { 61 .index = DT_BI_TCXO, 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_taycan_eko_t_ops, 65 }, 66 }, 67 }; 68 69 static const struct parent_map video_cc_parent_map_0[] = { 70 { P_BI_TCXO, 0 }, 71 }; 72 73 static const struct clk_parent_data video_cc_parent_data_0[] = { 74 { .index = DT_BI_TCXO }, 75 }; 76 77 static const struct parent_map video_cc_parent_map_1[] = { 78 { P_BI_TCXO, 0 }, 79 { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, 80 }; 81 82 static const struct clk_parent_data video_cc_parent_data_1[] = { 83 { .index = DT_BI_TCXO }, 84 { .hw = &video_cc_pll0.clkr.hw }, 85 }; 86 87 static const struct parent_map video_cc_parent_map_2[] = { 88 { P_SLEEP_CLK, 0 }, 89 }; 90 91 static const struct clk_parent_data video_cc_parent_data_2[] = { 92 { .index = DT_SLEEP_CLK }, 93 }; 94 95 static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { 96 F(19200000, P_BI_TCXO, 1, 0, 0), 97 { } 98 }; 99 100 static struct clk_rcg2 video_cc_ahb_clk_src = { 101 .cmd_rcgr = 0x8018, 102 .mnd_width = 0, 103 .hid_width = 5, 104 .parent_map = video_cc_parent_map_0, 105 .freq_tbl = ftbl_video_cc_ahb_clk_src, 106 .clkr.hw.init = &(const struct clk_init_data) { 107 .name = "video_cc_ahb_clk_src", 108 .parent_data = video_cc_parent_data_0, 109 .num_parents = ARRAY_SIZE(video_cc_parent_data_0), 110 .flags = CLK_SET_RATE_PARENT, 111 .ops = &clk_rcg2_shared_ops, 112 }, 113 }; 114 115 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { 116 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 117 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 118 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 119 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 120 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 121 F(1965000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 122 { } 123 }; 124 125 static struct clk_rcg2 video_cc_mvs0_clk_src = { 126 .cmd_rcgr = 0x8000, 127 .mnd_width = 0, 128 .hid_width = 5, 129 .parent_map = video_cc_parent_map_1, 130 .freq_tbl = ftbl_video_cc_mvs0_clk_src, 131 .clkr.hw.init = &(const struct clk_init_data) { 132 .name = "video_cc_mvs0_clk_src", 133 .parent_data = video_cc_parent_data_1, 134 .num_parents = ARRAY_SIZE(video_cc_parent_data_1), 135 .flags = CLK_SET_RATE_PARENT, 136 .ops = &clk_rcg2_shared_ops, 137 }, 138 }; 139 140 static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = { 141 F(32000, P_SLEEP_CLK, 1, 0, 0), 142 { } 143 }; 144 145 static struct clk_rcg2 video_cc_sleep_clk_src = { 146 .cmd_rcgr = 0x8120, 147 .mnd_width = 0, 148 .hid_width = 5, 149 .parent_map = video_cc_parent_map_2, 150 .freq_tbl = ftbl_video_cc_sleep_clk_src, 151 .clkr.hw.init = &(const struct clk_init_data) { 152 .name = "video_cc_sleep_clk_src", 153 .parent_data = video_cc_parent_data_2, 154 .num_parents = ARRAY_SIZE(video_cc_parent_data_2), 155 .flags = CLK_SET_RATE_PARENT, 156 .ops = &clk_rcg2_shared_ops, 157 }, 158 }; 159 160 static struct clk_rcg2 video_cc_xo_clk_src = { 161 .cmd_rcgr = 0x80f8, 162 .mnd_width = 0, 163 .hid_width = 5, 164 .parent_map = video_cc_parent_map_0, 165 .freq_tbl = ftbl_video_cc_ahb_clk_src, 166 .clkr.hw.init = &(const struct clk_init_data) { 167 .name = "video_cc_xo_clk_src", 168 .parent_data = video_cc_parent_data_0, 169 .num_parents = ARRAY_SIZE(video_cc_parent_data_0), 170 .flags = CLK_SET_RATE_PARENT, 171 .ops = &clk_rcg2_shared_ops, 172 }, 173 }; 174 175 static struct clk_regmap_div video_cc_mvs0_div_clk_src = { 176 .reg = 0x809c, 177 .shift = 0, 178 .width = 4, 179 .clkr.hw.init = &(const struct clk_init_data) { 180 .name = "video_cc_mvs0_div_clk_src", 181 .parent_hws = (const struct clk_hw*[]) { 182 &video_cc_mvs0_clk_src.clkr.hw, 183 }, 184 .num_parents = 1, 185 .flags = CLK_SET_RATE_PARENT, 186 .ops = &clk_regmap_div_ro_ops, 187 }, 188 }; 189 190 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { 191 .reg = 0x8060, 192 .shift = 0, 193 .width = 4, 194 .clkr.hw.init = &(const struct clk_init_data) { 195 .name = "video_cc_mvs0c_div2_div_clk_src", 196 .parent_hws = (const struct clk_hw*[]) { 197 &video_cc_mvs0_clk_src.clkr.hw, 198 }, 199 .num_parents = 1, 200 .flags = CLK_SET_RATE_PARENT, 201 .ops = &clk_regmap_div_ro_ops, 202 }, 203 }; 204 205 static struct clk_regmap_div video_cc_mvs1_div_clk_src = { 206 .reg = 0x80d8, 207 .shift = 0, 208 .width = 4, 209 .clkr.hw.init = &(const struct clk_init_data) { 210 .name = "video_cc_mvs1_div_clk_src", 211 .parent_hws = (const struct clk_hw*[]) { 212 &video_cc_mvs0_clk_src.clkr.hw, 213 }, 214 .num_parents = 1, 215 .flags = CLK_SET_RATE_PARENT, 216 .ops = &clk_regmap_div_ro_ops, 217 }, 218 }; 219 220 static struct clk_branch video_cc_mvs0_clk = { 221 .halt_reg = 0x807c, 222 .halt_check = BRANCH_HALT_VOTED, 223 .hwcg_reg = 0x807c, 224 .hwcg_bit = 1, 225 .clkr = { 226 .enable_reg = 0x807c, 227 .enable_mask = BIT(0), 228 .hw.init = &(const struct clk_init_data) { 229 .name = "video_cc_mvs0_clk", 230 .parent_hws = (const struct clk_hw*[]) { 231 &video_cc_mvs0_div_clk_src.clkr.hw, 232 }, 233 .num_parents = 1, 234 .flags = CLK_SET_RATE_PARENT, 235 .ops = &clk_branch2_ops, 236 }, 237 }, 238 }; 239 240 static struct clk_branch video_cc_mvs0_freerun_clk = { 241 .halt_reg = 0x808c, 242 .halt_check = BRANCH_HALT, 243 .clkr = { 244 .enable_reg = 0x808c, 245 .enable_mask = BIT(0), 246 .hw.init = &(const struct clk_init_data) { 247 .name = "video_cc_mvs0_freerun_clk", 248 .parent_hws = (const struct clk_hw*[]) { 249 &video_cc_mvs0_div_clk_src.clkr.hw, 250 }, 251 .num_parents = 1, 252 .flags = CLK_SET_RATE_PARENT, 253 .ops = &clk_branch2_ops, 254 }, 255 }, 256 }; 257 258 static struct clk_branch video_cc_mvs0_shift_clk = { 259 .halt_reg = 0x8114, 260 .halt_check = BRANCH_HALT_VOTED, 261 .hwcg_reg = 0x8114, 262 .hwcg_bit = 1, 263 .clkr = { 264 .enable_reg = 0x8114, 265 .enable_mask = BIT(0), 266 .hw.init = &(const struct clk_init_data) { 267 .name = "video_cc_mvs0_shift_clk", 268 .parent_hws = (const struct clk_hw*[]) { 269 &video_cc_xo_clk_src.clkr.hw, 270 }, 271 .num_parents = 1, 272 .flags = CLK_SET_RATE_PARENT, 273 .ops = &clk_branch2_ops, 274 }, 275 }, 276 }; 277 278 static struct clk_branch video_cc_mvs0c_clk = { 279 .halt_reg = 0x804c, 280 .halt_check = BRANCH_HALT, 281 .clkr = { 282 .enable_reg = 0x804c, 283 .enable_mask = BIT(0), 284 .hw.init = &(const struct clk_init_data) { 285 .name = "video_cc_mvs0c_clk", 286 .parent_hws = (const struct clk_hw*[]) { 287 &video_cc_mvs0c_div2_div_clk_src.clkr.hw, 288 }, 289 .num_parents = 1, 290 .flags = CLK_SET_RATE_PARENT, 291 .ops = &clk_branch2_ops, 292 }, 293 }, 294 }; 295 296 static struct clk_branch video_cc_mvs0c_freerun_clk = { 297 .halt_reg = 0x805c, 298 .halt_check = BRANCH_HALT, 299 .clkr = { 300 .enable_reg = 0x805c, 301 .enable_mask = BIT(0), 302 .hw.init = &(const struct clk_init_data) { 303 .name = "video_cc_mvs0c_freerun_clk", 304 .parent_hws = (const struct clk_hw*[]) { 305 &video_cc_mvs0c_div2_div_clk_src.clkr.hw, 306 }, 307 .num_parents = 1, 308 .flags = CLK_SET_RATE_PARENT, 309 .ops = &clk_branch2_ops, 310 }, 311 }, 312 }; 313 314 static struct clk_branch video_cc_mvs0c_shift_clk = { 315 .halt_reg = 0x811c, 316 .halt_check = BRANCH_HALT_VOTED, 317 .hwcg_reg = 0x811c, 318 .hwcg_bit = 1, 319 .clkr = { 320 .enable_reg = 0x811c, 321 .enable_mask = BIT(0), 322 .hw.init = &(const struct clk_init_data) { 323 .name = "video_cc_mvs0c_shift_clk", 324 .parent_hws = (const struct clk_hw*[]) { 325 &video_cc_xo_clk_src.clkr.hw, 326 }, 327 .num_parents = 1, 328 .flags = CLK_SET_RATE_PARENT, 329 .ops = &clk_branch2_ops, 330 }, 331 }, 332 }; 333 334 static struct clk_branch video_cc_mvs1_clk = { 335 .halt_reg = 0x80b8, 336 .halt_check = BRANCH_HALT_VOTED, 337 .hwcg_reg = 0x80b8, 338 .hwcg_bit = 1, 339 .clkr = { 340 .enable_reg = 0x80b8, 341 .enable_mask = BIT(0), 342 .hw.init = &(const struct clk_init_data) { 343 .name = "video_cc_mvs1_clk", 344 .parent_hws = (const struct clk_hw*[]) { 345 &video_cc_mvs1_div_clk_src.clkr.hw, 346 }, 347 .num_parents = 1, 348 .flags = CLK_SET_RATE_PARENT, 349 .ops = &clk_branch2_ops, 350 }, 351 }, 352 }; 353 354 static struct clk_branch video_cc_mvs1_freerun_clk = { 355 .halt_reg = 0x80c8, 356 .halt_check = BRANCH_HALT, 357 .clkr = { 358 .enable_reg = 0x80c8, 359 .enable_mask = BIT(0), 360 .hw.init = &(const struct clk_init_data) { 361 .name = "video_cc_mvs1_freerun_clk", 362 .parent_hws = (const struct clk_hw*[]) { 363 &video_cc_mvs1_div_clk_src.clkr.hw, 364 }, 365 .num_parents = 1, 366 .flags = CLK_SET_RATE_PARENT, 367 .ops = &clk_branch2_ops, 368 }, 369 }, 370 }; 371 372 static struct clk_branch video_cc_mvs1_shift_clk = { 373 .halt_reg = 0x8118, 374 .halt_check = BRANCH_HALT_VOTED, 375 .hwcg_reg = 0x8118, 376 .hwcg_bit = 1, 377 .clkr = { 378 .enable_reg = 0x8118, 379 .enable_mask = BIT(0), 380 .hw.init = &(const struct clk_init_data) { 381 .name = "video_cc_mvs1_shift_clk", 382 .parent_hws = (const struct clk_hw*[]) { 383 &video_cc_xo_clk_src.clkr.hw, 384 }, 385 .num_parents = 1, 386 .flags = CLK_SET_RATE_PARENT, 387 .ops = &clk_branch2_ops, 388 }, 389 }, 390 }; 391 392 static struct gdsc video_cc_mvs0c_gdsc = { 393 .gdscr = 0x8034, 394 .en_rest_wait_val = 0x2, 395 .en_few_wait_val = 0x2, 396 .clk_dis_wait_val = 0x6, 397 .pd = { 398 .name = "video_cc_mvs0c_gdsc", 399 }, 400 .pwrsts = PWRSTS_OFF_ON, 401 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 402 }; 403 404 static struct gdsc video_cc_mvs0_gdsc = { 405 .gdscr = 0x8068, 406 .en_rest_wait_val = 0x2, 407 .en_few_wait_val = 0x2, 408 .clk_dis_wait_val = 0x6, 409 .pd = { 410 .name = "video_cc_mvs0_gdsc", 411 }, 412 .pwrsts = PWRSTS_OFF_ON, 413 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 414 .parent = &video_cc_mvs0c_gdsc.pd, 415 }; 416 417 static struct gdsc video_cc_mvs1_gdsc = { 418 .gdscr = 0x80a4, 419 .en_rest_wait_val = 0x2, 420 .en_few_wait_val = 0x2, 421 .clk_dis_wait_val = 0x6, 422 .pd = { 423 .name = "video_cc_mvs1_gdsc", 424 }, 425 .pwrsts = PWRSTS_OFF_ON, 426 .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 427 }; 428 429 static struct clk_regmap *video_cc_glymur_clocks[] = { 430 [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, 431 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, 432 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, 433 [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, 434 [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr, 435 [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, 436 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, 437 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, 438 [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr, 439 [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, 440 [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, 441 [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, 442 [VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr, 443 [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, 444 [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, 445 [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr, 446 [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, 447 }; 448 449 static struct gdsc *video_cc_glymur_gdscs[] = { 450 [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, 451 [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, 452 [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, 453 }; 454 455 static const struct qcom_reset_map video_cc_glymur_resets[] = { 456 [VIDEO_CC_INTERFACE_BCR] = { 0x80dc }, 457 [VIDEO_CC_MVS0_BCR] = { 0x8064 }, 458 [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 }, 459 [VIDEO_CC_MVS0C_BCR] = { 0x8030 }, 460 [VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x808c, 2 }, 461 [VIDEO_CC_MVS1_FREERUN_CLK_ARES] = { 0x80c8, 2 }, 462 [VIDEO_CC_MVS1_BCR] = { 0x80a0 }, 463 }; 464 465 static struct clk_alpha_pll *video_cc_glymur_plls[] = { 466 &video_cc_pll0, 467 }; 468 469 static const u32 video_cc_glymur_critical_cbcrs[] = { 470 0x80e0, /* VIDEO_CC_AHB_CLK */ 471 0x8138, /* VIDEO_CC_SLEEP_CLK */ 472 0x8110, /* VIDEO_CC_XO_CLK */ 473 }; 474 475 static const struct regmap_config video_cc_glymur_regmap_config = { 476 .reg_bits = 32, 477 .reg_stride = 4, 478 .val_bits = 32, 479 .max_register = 0x9f54, 480 .fast_io = true, 481 }; 482 483 static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap) 484 { 485 /* Update CTRL_IN register */ 486 regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); 487 } 488 489 static const struct qcom_cc_driver_data video_cc_glymur_driver_data = { 490 .alpha_plls = video_cc_glymur_plls, 491 .num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls), 492 .clk_cbcrs = video_cc_glymur_critical_cbcrs, 493 .num_clk_cbcrs = ARRAY_SIZE(video_cc_glymur_critical_cbcrs), 494 .clk_regs_configure = clk_glymur_regs_configure, 495 }; 496 497 static const struct qcom_cc_desc video_cc_glymur_desc = { 498 .config = &video_cc_glymur_regmap_config, 499 .clks = video_cc_glymur_clocks, 500 .num_clks = ARRAY_SIZE(video_cc_glymur_clocks), 501 .resets = video_cc_glymur_resets, 502 .num_resets = ARRAY_SIZE(video_cc_glymur_resets), 503 .gdscs = video_cc_glymur_gdscs, 504 .num_gdscs = ARRAY_SIZE(video_cc_glymur_gdscs), 505 .use_rpm = true, 506 .driver_data = &video_cc_glymur_driver_data, 507 }; 508 509 static const struct of_device_id video_cc_glymur_match_table[] = { 510 { .compatible = "qcom,glymur-videocc" }, 511 { } 512 }; 513 MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table); 514 515 static int video_cc_glymur_probe(struct platform_device *pdev) 516 { 517 return qcom_cc_probe(pdev, &video_cc_glymur_desc); 518 } 519 520 static struct platform_driver video_cc_glymur_driver = { 521 .probe = video_cc_glymur_probe, 522 .driver = { 523 .name = "videocc-glymur", 524 .of_match_table = video_cc_glymur_match_table, 525 }, 526 }; 527 528 module_platform_driver(video_cc_glymur_driver); 529 530 MODULE_DESCRIPTION("QTI VIDEOCC Glymur Driver"); 531 MODULE_LICENSE("GPL"); 532