1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,hawi-tcsrcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "common.h" 22 #include "reset.h" 23 24 enum { 25 DT_BI_TCXO_PAD, 26 }; 27 28 static struct clk_branch tcsr_pcie_0_clkref_en = { 29 .halt_reg = 0x4c, 30 .halt_check = BRANCH_HALT_DELAY, 31 .clkr = { 32 .enable_reg = 0x4c, 33 .enable_mask = BIT(0), 34 .hw.init = &(const struct clk_init_data) { 35 .name = "tcsr_pcie_0_clkref_en", 36 .parent_data = &(const struct clk_parent_data){ 37 .index = DT_BI_TCXO_PAD, 38 }, 39 .num_parents = 1, 40 .ops = &clk_branch2_ops, 41 }, 42 }, 43 }; 44 45 static struct clk_branch tcsr_pcie_1_clkref_en = { 46 .halt_reg = 0x0, 47 .halt_check = BRANCH_HALT_DELAY, 48 .clkr = { 49 .enable_reg = 0x0, 50 .enable_mask = BIT(0), 51 .hw.init = &(const struct clk_init_data) { 52 .name = "tcsr_pcie_1_clkref_en", 53 .parent_data = &(const struct clk_parent_data){ 54 .index = DT_BI_TCXO_PAD, 55 }, 56 .num_parents = 1, 57 .ops = &clk_branch2_ops, 58 }, 59 }, 60 }; 61 62 static struct clk_branch tcsr_ufs_clkref_en = { 63 .halt_reg = 0x10, 64 .halt_check = BRANCH_HALT_DELAY, 65 .clkr = { 66 .enable_reg = 0x10, 67 .enable_mask = BIT(0), 68 .hw.init = &(const struct clk_init_data) { 69 .name = "tcsr_ufs_clkref_en", 70 .parent_data = &(const struct clk_parent_data){ 71 .index = DT_BI_TCXO_PAD, 72 }, 73 .num_parents = 1, 74 .ops = &clk_branch2_ops, 75 }, 76 }, 77 }; 78 79 static struct clk_branch tcsr_usb2_clkref_en = { 80 .halt_reg = 0x18, 81 .halt_check = BRANCH_HALT_DELAY, 82 .clkr = { 83 .enable_reg = 0x18, 84 .enable_mask = BIT(0), 85 .hw.init = &(const struct clk_init_data) { 86 .name = "tcsr_usb2_clkref_en", 87 .parent_data = &(const struct clk_parent_data){ 88 .index = DT_BI_TCXO_PAD, 89 }, 90 .num_parents = 1, 91 .ops = &clk_branch2_ops, 92 }, 93 }, 94 }; 95 96 static struct clk_branch tcsr_usb3_clkref_en = { 97 .halt_reg = 0x8, 98 .halt_check = BRANCH_HALT_DELAY, 99 .clkr = { 100 .enable_reg = 0x8, 101 .enable_mask = BIT(0), 102 .hw.init = &(const struct clk_init_data) { 103 .name = "tcsr_usb3_clkref_en", 104 .parent_data = &(const struct clk_parent_data){ 105 .index = DT_BI_TCXO_PAD, 106 }, 107 .num_parents = 1, 108 .ops = &clk_branch2_ops, 109 }, 110 }, 111 }; 112 113 static struct clk_regmap *tcsr_cc_hawi_clocks[] = { 114 [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, 115 [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, 116 [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, 117 [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, 118 [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, 119 }; 120 121 static const struct regmap_config tcsr_cc_hawi_regmap_config = { 122 .reg_bits = 32, 123 .reg_stride = 4, 124 .val_bits = 32, 125 .max_register = 0x4c, 126 .fast_io = true, 127 }; 128 129 static const struct qcom_cc_desc tcsr_cc_hawi_desc = { 130 .config = &tcsr_cc_hawi_regmap_config, 131 .clks = tcsr_cc_hawi_clocks, 132 .num_clks = ARRAY_SIZE(tcsr_cc_hawi_clocks), 133 }; 134 135 static const struct of_device_id tcsr_cc_hawi_match_table[] = { 136 { .compatible = "qcom,hawi-tcsrcc" }, 137 { } 138 }; 139 MODULE_DEVICE_TABLE(of, tcsr_cc_hawi_match_table); 140 141 static int tcsr_cc_hawi_probe(struct platform_device *pdev) 142 { 143 return qcom_cc_probe(pdev, &tcsr_cc_hawi_desc); 144 } 145 146 static struct platform_driver tcsr_cc_hawi_driver = { 147 .probe = tcsr_cc_hawi_probe, 148 .driver = { 149 .name = "tcsrcc-hawi", 150 .of_match_table = tcsr_cc_hawi_match_table, 151 }, 152 }; 153 154 module_platform_driver(tcsr_cc_hawi_driver); 155 156 MODULE_DESCRIPTION("QTI TCSRCC HAWI Driver"); 157 MODULE_LICENSE("GPL"); 158