1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/regmap.h> 11 #include <linux/phy.h> 12 #include <linux/mdio.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/consumer.h> 15 16 #include <dt-bindings/clock/qcom,qca8k-nsscc.h> 17 #include <dt-bindings/reset/qcom,qca8k-nsscc.h> 18 19 #include "clk-branch.h" 20 #include "clk-rcg.h" 21 #include "clk-regmap.h" 22 #include "clk-regmap-divider.h" 23 #include "clk-regmap-mux.h" 24 #include "common.h" 25 #include "reset.h" 26 27 #define QCA8K_CLK_REG_BASE 0x800000 28 #define QCA8K_HIGH_ADDR_PREFIX 0x18 29 #define QCA8K_LOW_ADDR_PREFIX 0x10 30 #define QCA8K_CFG_PAGE_REG 0xc 31 #define QCA8K_CLK_REG_MASK GENMASK(4, 0) 32 #define QCA8K_CLK_PHY_ADDR_MASK GENMASK(7, 5) 33 #define QCA8K_CLK_PAGE_MASK GENMASK(23, 8) 34 #define QCA8K_REG_DATA_UPPER_16_BITS BIT(1) 35 36 enum { 37 DT_XO, 38 DT_UNIPHY0_RX_CLK, 39 DT_UNIPHY0_TX_CLK, 40 DT_UNIPHY1_RX_CLK, 41 DT_UNIPHY1_TX_CLK, 42 DT_UNIPHY1_RX312P5M_CLK, 43 DT_UNIPHY1_TX312P5M_CLK, 44 }; 45 46 enum { 47 P_XO, 48 P_UNIPHY0_RX, 49 P_UNIPHY0_TX, 50 P_UNIPHY1_RX, 51 P_UNIPHY1_TX, 52 P_UNIPHY1_RX312P5M, 53 P_UNIPHY1_TX312P5M, 54 P_MAC4_RX_DIV, 55 P_MAC4_TX_DIV, 56 P_MAC5_RX_DIV, 57 P_MAC5_TX_DIV, 58 }; 59 60 static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_data[] = { 61 { .index = DT_XO }, 62 { .index = DT_UNIPHY1_TX312P5M_CLK }, 63 }; 64 65 static const struct parent_map nss_cc_uniphy1_tx312p5m_map[] = { 66 { P_XO, 0 }, 67 { P_UNIPHY1_TX312P5M, 1 }, 68 }; 69 70 static struct clk_rcg2 nss_cc_switch_core_clk_src = { 71 .cmd_rcgr = 0x0, 72 .hid_width = 5, 73 .parent_map = nss_cc_uniphy1_tx312p5m_map, 74 .clkr.hw.init = &(const struct clk_init_data) { 75 .name = "nss_cc_switch_core_clk_src", 76 .parent_data = nss_cc_uniphy1_tx312p5m_data, 77 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data), 78 .ops = &clk_rcg2_mux_closest_ops, 79 }, 80 }; 81 82 static struct clk_branch nss_cc_switch_core_clk = { 83 .halt_reg = 0x8, 84 .halt_check = BRANCH_HALT, 85 .clkr = { 86 .enable_reg = 0x8, 87 .enable_mask = BIT(0), 88 .hw.init = &(const struct clk_init_data) { 89 .name = "nss_cc_switch_core_clk", 90 .parent_hws = (const struct clk_hw *[]) { 91 &nss_cc_switch_core_clk_src.clkr.hw, 92 }, 93 .num_parents = 1, 94 .flags = CLK_SET_RATE_PARENT, 95 .ops = &clk_branch2_prepare_ops, 96 }, 97 }, 98 }; 99 100 static struct clk_branch nss_cc_apb_bridge_clk = { 101 .halt_reg = 0x10, 102 .halt_check = BRANCH_HALT, 103 .clkr = { 104 .enable_reg = 0x10, 105 .enable_mask = BIT(0), 106 .hw.init = &(const struct clk_init_data) { 107 .name = "nss_cc_apb_bridge_clk", 108 .parent_hws = (const struct clk_hw *[]) { 109 &nss_cc_switch_core_clk_src.clkr.hw, 110 }, 111 .num_parents = 1, 112 .flags = CLK_SET_RATE_PARENT, 113 .ops = &clk_branch2_prepare_ops, 114 }, 115 }, 116 }; 117 118 static const struct clk_parent_data nss_cc_uniphy1_tx_data[] = { 119 { .index = DT_XO }, 120 { .index = DT_UNIPHY1_TX_CLK }, 121 }; 122 123 static const struct parent_map nss_cc_uniphy1_tx_map[] = { 124 { P_XO, 0 }, 125 { P_UNIPHY1_TX, 2 }, 126 }; 127 128 static struct clk_rcg2 nss_cc_mac0_tx_clk_src = { 129 .cmd_rcgr = 0x14, 130 .hid_width = 5, 131 .parent_map = nss_cc_uniphy1_tx_map, 132 .clkr.hw.init = &(const struct clk_init_data) { 133 .name = "nss_cc_mac0_tx_clk_src", 134 .parent_data = nss_cc_uniphy1_tx_data, 135 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx_data), 136 .flags = CLK_SET_RATE_PARENT, 137 .ops = &clk_rcg2_mux_closest_ops, 138 }, 139 }; 140 141 static struct clk_regmap_div nss_cc_mac0_tx_div_clk_src = { 142 .reg = 0x1c, 143 .shift = 0, 144 .width = 4, 145 .clkr = { 146 .hw.init = &(const struct clk_init_data) { 147 .name = "nss_cc_mac0_tx_div_clk_src", 148 .parent_hws = (const struct clk_hw *[]) { 149 &nss_cc_mac0_tx_clk_src.clkr.hw, 150 }, 151 .num_parents = 1, 152 .flags = CLK_SET_RATE_PARENT, 153 .ops = &clk_regmap_div_ops, 154 }, 155 }, 156 }; 157 158 static struct clk_branch nss_cc_mac0_tx_clk = { 159 .halt_reg = 0x20, 160 .halt_check = BRANCH_HALT, 161 .clkr = { 162 .enable_reg = 0x20, 163 .enable_mask = BIT(0), 164 .hw.init = &(const struct clk_init_data) { 165 .name = "nss_cc_mac0_tx_clk", 166 .parent_hws = (const struct clk_hw *[]) { 167 &nss_cc_mac0_tx_div_clk_src.clkr.hw, 168 }, 169 .num_parents = 1, 170 .flags = CLK_SET_RATE_PARENT, 171 .ops = &clk_branch2_prepare_ops, 172 }, 173 }, 174 }; 175 176 static struct clk_branch nss_cc_mac0_tx_srds1_clk = { 177 .halt_reg = 0x24, 178 .halt_check = BRANCH_HALT, 179 .clkr = { 180 .enable_reg = 0x24, 181 .enable_mask = BIT(0), 182 .hw.init = &(const struct clk_init_data) { 183 .name = "nss_cc_mac0_tx_srds1_clk", 184 .parent_hws = (const struct clk_hw *[]) { 185 &nss_cc_mac0_tx_div_clk_src.clkr.hw, 186 }, 187 .num_parents = 1, 188 .flags = CLK_SET_RATE_PARENT, 189 .ops = &clk_branch2_prepare_ops, 190 }, 191 }, 192 }; 193 194 static const struct clk_parent_data nss_cc_uniphy1_rx_tx_data[] = { 195 { .index = DT_XO }, 196 { .index = DT_UNIPHY1_RX_CLK }, 197 { .index = DT_UNIPHY1_TX_CLK }, 198 }; 199 200 static const struct parent_map nss_cc_uniphy1_rx_tx_map[] = { 201 { P_XO, 0 }, 202 { P_UNIPHY1_RX, 1 }, 203 { P_UNIPHY1_TX, 2 }, 204 }; 205 206 static struct clk_rcg2 nss_cc_mac0_rx_clk_src = { 207 .cmd_rcgr = 0x28, 208 .hid_width = 5, 209 .parent_map = nss_cc_uniphy1_rx_tx_map, 210 .clkr.hw.init = &(const struct clk_init_data) { 211 .name = "nss_cc_mac0_rx_clk_src", 212 .parent_data = nss_cc_uniphy1_rx_tx_data, 213 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx_data), 214 .flags = CLK_SET_RATE_PARENT, 215 .ops = &clk_rcg2_mux_closest_ops, 216 }, 217 }; 218 219 static struct clk_regmap_div nss_cc_mac0_rx_div_clk_src = { 220 .reg = 0x30, 221 .shift = 0, 222 .width = 4, 223 .clkr = { 224 .hw.init = &(const struct clk_init_data) { 225 .name = "nss_cc_mac0_rx_div_clk_src", 226 .parent_hws = (const struct clk_hw *[]) { 227 &nss_cc_mac0_rx_clk_src.clkr.hw, 228 }, 229 .num_parents = 1, 230 .flags = CLK_SET_RATE_PARENT, 231 .ops = &clk_regmap_div_ops, 232 }, 233 }, 234 }; 235 236 static struct clk_branch nss_cc_mac0_rx_clk = { 237 .halt_reg = 0x34, 238 .halt_check = BRANCH_HALT, 239 .clkr = { 240 .enable_reg = 0x34, 241 .enable_mask = BIT(0), 242 .hw.init = &(const struct clk_init_data) { 243 .name = "nss_cc_mac0_rx_clk", 244 .parent_hws = (const struct clk_hw *[]) { 245 &nss_cc_mac0_rx_div_clk_src.clkr.hw, 246 }, 247 .num_parents = 1, 248 .flags = CLK_SET_RATE_PARENT, 249 .ops = &clk_branch2_prepare_ops, 250 }, 251 }, 252 }; 253 254 static struct clk_branch nss_cc_mac0_rx_srds1_clk = { 255 .halt_reg = 0x3c, 256 .halt_check = BRANCH_HALT, 257 .clkr = { 258 .enable_reg = 0x3c, 259 .enable_mask = BIT(0), 260 .hw.init = &(const struct clk_init_data) { 261 .name = "nss_cc_mac0_rx_srds1_clk", 262 .parent_hws = (const struct clk_hw *[]) { 263 &nss_cc_mac0_rx_div_clk_src.clkr.hw, 264 }, 265 .num_parents = 1, 266 .flags = CLK_SET_RATE_PARENT, 267 .ops = &clk_branch2_prepare_ops, 268 }, 269 }, 270 }; 271 272 static const struct clk_parent_data nss_cc_uniphy1_rx_tx312p5m_data[] = { 273 { .index = DT_XO }, 274 { .index = DT_UNIPHY1_TX312P5M_CLK }, 275 { .index = DT_UNIPHY1_RX312P5M_CLK }, 276 }; 277 278 static const struct parent_map nss_cc_uniphy1_rx_tx312p5m_map[] = { 279 { P_XO, 0 }, 280 { P_UNIPHY1_TX312P5M, 6 }, 281 { P_UNIPHY1_RX312P5M, 7 }, 282 }; 283 284 static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_25[] = { 285 C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), 286 C(P_UNIPHY1_RX312P5M, 12.5, 0, 0), 287 }; 288 289 static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_125[] = { 290 C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), 291 C(P_UNIPHY1_RX312P5M, 2.5, 0, 0), 292 }; 293 294 static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_312p5[] = { 295 C(P_UNIPHY1_TX312P5M, 1, 0, 0), 296 C(P_UNIPHY1_RX312P5M, 1, 0, 0), 297 }; 298 299 static const struct freq_multi_tbl ftbl_nss_cc_mac1_tx_clk_src[] = { 300 FM(25000000, ftbl_nss_cc_mac1_tx_clk_src_25), 301 FMS(50000000, P_XO, 1, 0, 0), 302 FM(125000000, ftbl_nss_cc_mac1_tx_clk_src_125), 303 FM(312500000, ftbl_nss_cc_mac1_tx_clk_src_312p5), 304 { } 305 }; 306 307 static struct clk_rcg2 nss_cc_mac1_tx_clk_src = { 308 .cmd_rcgr = 0x40, 309 .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, 310 .hid_width = 5, 311 .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, 312 .clkr.hw.init = &(const struct clk_init_data) { 313 .name = "nss_cc_mac1_tx_clk_src", 314 .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, 315 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), 316 .ops = &clk_rcg2_fm_ops, 317 }, 318 }; 319 320 static struct clk_regmap_div nss_cc_mac1_tx_div_clk_src = { 321 .reg = 0x48, 322 .shift = 0, 323 .width = 4, 324 .clkr = { 325 .hw.init = &(const struct clk_init_data) { 326 .name = "nss_cc_mac1_tx_div_clk_src", 327 .parent_hws = (const struct clk_hw *[]) { 328 &nss_cc_mac1_tx_clk_src.clkr.hw, 329 }, 330 .num_parents = 1, 331 .flags = CLK_SET_RATE_PARENT, 332 .ops = &clk_regmap_div_ops, 333 }, 334 }, 335 }; 336 337 static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src = { 338 .reg = 0x4c, 339 .shift = 0, 340 .width = 4, 341 .clkr = { 342 .hw.init = &(const struct clk_init_data) { 343 .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src", 344 .parent_hws = (const struct clk_hw *[]) { 345 &nss_cc_mac1_tx_clk_src.clkr.hw, 346 }, 347 .num_parents = 1, 348 .flags = CLK_SET_RATE_PARENT, 349 .ops = &clk_regmap_div_ops, 350 }, 351 }, 352 }; 353 354 static struct clk_branch nss_cc_mac1_srds1_ch0_rx_clk = { 355 .halt_reg = 0x50, 356 .halt_check = BRANCH_HALT, 357 .clkr = { 358 .enable_reg = 0x50, 359 .enable_mask = BIT(0), 360 .hw.init = &(const struct clk_init_data) { 361 .name = "nss_cc_mac1_srds1_ch0_rx_clk", 362 .parent_hws = (const struct clk_hw *[]) { 363 &nss_cc_mac1_tx_div_clk_src.clkr.hw, 364 }, 365 .num_parents = 1, 366 .flags = CLK_SET_RATE_PARENT, 367 .ops = &clk_branch2_prepare_ops, 368 }, 369 }, 370 }; 371 372 static struct clk_branch nss_cc_mac1_tx_clk = { 373 .halt_reg = 0x54, 374 .halt_check = BRANCH_HALT, 375 .clkr = { 376 .enable_reg = 0x54, 377 .enable_mask = BIT(0), 378 .hw.init = &(const struct clk_init_data) { 379 .name = "nss_cc_mac1_tx_clk", 380 .parent_hws = (const struct clk_hw *[]) { 381 &nss_cc_mac1_tx_div_clk_src.clkr.hw, 382 }, 383 .num_parents = 1, 384 .flags = CLK_SET_RATE_PARENT, 385 .ops = &clk_branch2_prepare_ops, 386 }, 387 }, 388 }; 389 390 static struct clk_branch nss_cc_mac1_gephy0_tx_clk = { 391 .halt_reg = 0x58, 392 .halt_check = BRANCH_HALT, 393 .clkr = { 394 .enable_reg = 0x58, 395 .enable_mask = BIT(0), 396 .hw.init = &(const struct clk_init_data) { 397 .name = "nss_cc_mac1_gephy0_tx_clk", 398 .parent_hws = (const struct clk_hw *[]) { 399 &nss_cc_mac1_tx_div_clk_src.clkr.hw, 400 }, 401 .num_parents = 1, 402 .flags = CLK_SET_RATE_PARENT, 403 .ops = &clk_branch2_prepare_ops, 404 }, 405 }, 406 }; 407 408 static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_rx_clk = { 409 .halt_reg = 0x5c, 410 .halt_check = BRANCH_HALT, 411 .clkr = { 412 .enable_reg = 0x5c, 413 .enable_mask = BIT(0), 414 .hw.init = &(const struct clk_init_data) { 415 .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_clk", 416 .parent_hws = (const struct clk_hw *[]) { 417 &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr.hw, 418 }, 419 .num_parents = 1, 420 .flags = CLK_SET_RATE_PARENT, 421 .ops = &clk_branch2_prepare_ops, 422 }, 423 }, 424 }; 425 426 static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_prx_data[] = { 427 { .index = DT_XO }, 428 { .index = DT_UNIPHY1_TX312P5M_CLK }, 429 }; 430 431 static const struct parent_map nss_cc_uniphy1_tx312p5m_prx_map[] = { 432 { P_XO, 0 }, 433 { P_UNIPHY1_TX312P5M, 6 }, 434 }; 435 436 static const struct freq_tbl ftbl_nss_cc_mac1_rx_clk_src[] = { 437 F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0), 438 F(50000000, P_XO, 1, 0, 0), 439 F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0), 440 F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0), 441 { } 442 }; 443 444 static struct clk_rcg2 nss_cc_mac1_rx_clk_src = { 445 .cmd_rcgr = 0x60, 446 .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, 447 .hid_width = 5, 448 .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, 449 .clkr.hw.init = &(const struct clk_init_data) { 450 .name = "nss_cc_mac1_rx_clk_src", 451 .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, 452 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), 453 .ops = &clk_rcg2_ops, 454 }, 455 }; 456 457 static struct clk_regmap_div nss_cc_mac1_rx_div_clk_src = { 458 .reg = 0x68, 459 .shift = 0, 460 .width = 4, 461 .clkr = { 462 .hw.init = &(const struct clk_init_data) { 463 .name = "nss_cc_mac1_rx_div_clk_src", 464 .parent_hws = (const struct clk_hw *[]) { 465 &nss_cc_mac1_rx_clk_src.clkr.hw, 466 }, 467 .num_parents = 1, 468 .flags = CLK_SET_RATE_PARENT, 469 .ops = &clk_regmap_div_ops, 470 }, 471 }, 472 }; 473 474 static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src = { 475 .reg = 0x6c, 476 .shift = 0, 477 .width = 4, 478 .clkr = { 479 .hw.init = &(const struct clk_init_data) { 480 .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src", 481 .parent_hws = (const struct clk_hw *[]) { 482 &nss_cc_mac1_rx_clk_src.clkr.hw, 483 }, 484 .num_parents = 1, 485 .flags = CLK_SET_RATE_PARENT, 486 .ops = &clk_regmap_div_ops, 487 }, 488 }, 489 }; 490 491 static struct clk_branch nss_cc_mac1_srds1_ch0_tx_clk = { 492 .halt_reg = 0x70, 493 .halt_check = BRANCH_HALT, 494 .clkr = { 495 .enable_reg = 0x70, 496 .enable_mask = BIT(0), 497 .hw.init = &(const struct clk_init_data) { 498 .name = "nss_cc_mac1_srds1_ch0_tx_clk", 499 .parent_hws = (const struct clk_hw *[]) { 500 &nss_cc_mac1_rx_div_clk_src.clkr.hw, 501 }, 502 .num_parents = 1, 503 .flags = CLK_SET_RATE_PARENT, 504 .ops = &clk_branch2_prepare_ops, 505 }, 506 }, 507 }; 508 509 static struct clk_branch nss_cc_mac1_rx_clk = { 510 .halt_reg = 0x74, 511 .halt_check = BRANCH_HALT, 512 .clkr = { 513 .enable_reg = 0x74, 514 .enable_mask = BIT(0), 515 .hw.init = &(const struct clk_init_data) { 516 .name = "nss_cc_mac1_rx_clk", 517 .parent_hws = (const struct clk_hw *[]) { 518 &nss_cc_mac1_rx_div_clk_src.clkr.hw, 519 }, 520 .num_parents = 1, 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_branch2_prepare_ops, 523 }, 524 }, 525 }; 526 527 static struct clk_branch nss_cc_mac1_gephy0_rx_clk = { 528 .halt_reg = 0x78, 529 .halt_check = BRANCH_HALT, 530 .clkr = { 531 .enable_reg = 0x78, 532 .enable_mask = BIT(0), 533 .hw.init = &(const struct clk_init_data) { 534 .name = "nss_cc_mac1_gephy0_rx_clk", 535 .parent_hws = (const struct clk_hw *[]) { 536 &nss_cc_mac1_rx_div_clk_src.clkr.hw, 537 }, 538 .num_parents = 1, 539 .flags = CLK_SET_RATE_PARENT, 540 .ops = &clk_branch2_prepare_ops, 541 }, 542 }, 543 }; 544 545 static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_tx_clk = { 546 .halt_reg = 0x7c, 547 .halt_check = BRANCH_HALT, 548 .clkr = { 549 .enable_reg = 0x7c, 550 .enable_mask = BIT(0), 551 .hw.init = &(const struct clk_init_data) { 552 .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_clk", 553 .parent_hws = (const struct clk_hw *[]) { 554 &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr.hw, 555 }, 556 .num_parents = 1, 557 .flags = CLK_SET_RATE_PARENT, 558 .ops = &clk_branch2_prepare_ops, 559 }, 560 }, 561 }; 562 563 static struct clk_rcg2 nss_cc_mac2_tx_clk_src = { 564 .cmd_rcgr = 0x80, 565 .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, 566 .hid_width = 5, 567 .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, 568 .clkr.hw.init = &(const struct clk_init_data) { 569 .name = "nss_cc_mac2_tx_clk_src", 570 .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, 571 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), 572 .ops = &clk_rcg2_fm_ops, 573 }, 574 }; 575 576 static struct clk_regmap_div nss_cc_mac2_tx_div_clk_src = { 577 .reg = 0x88, 578 .shift = 0, 579 .width = 4, 580 .clkr = { 581 .hw.init = &(const struct clk_init_data) { 582 .name = "nss_cc_mac2_tx_div_clk_src", 583 .parent_hws = (const struct clk_hw *[]) { 584 &nss_cc_mac2_tx_clk_src.clkr.hw, 585 }, 586 .num_parents = 1, 587 .flags = CLK_SET_RATE_PARENT, 588 .ops = &clk_regmap_div_ops, 589 }, 590 }, 591 }; 592 593 static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src = { 594 .reg = 0x8c, 595 .shift = 0, 596 .width = 4, 597 .clkr = { 598 .hw.init = &(const struct clk_init_data) { 599 .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src", 600 .parent_hws = (const struct clk_hw *[]) { 601 &nss_cc_mac2_tx_clk_src.clkr.hw, 602 }, 603 .num_parents = 1, 604 .flags = CLK_SET_RATE_PARENT, 605 .ops = &clk_regmap_div_ops, 606 }, 607 }, 608 }; 609 610 static struct clk_branch nss_cc_mac2_srds1_ch1_rx_clk = { 611 .halt_reg = 0x90, 612 .halt_check = BRANCH_HALT, 613 .clkr = { 614 .enable_reg = 0x90, 615 .enable_mask = BIT(0), 616 .hw.init = &(const struct clk_init_data) { 617 .name = "nss_cc_mac2_srds1_ch1_rx_clk", 618 .parent_hws = (const struct clk_hw *[]) { 619 &nss_cc_mac2_tx_div_clk_src.clkr.hw, 620 }, 621 .num_parents = 1, 622 .flags = CLK_SET_RATE_PARENT, 623 .ops = &clk_branch2_prepare_ops, 624 }, 625 }, 626 }; 627 628 static struct clk_branch nss_cc_mac2_tx_clk = { 629 .halt_reg = 0x94, 630 .halt_check = BRANCH_HALT, 631 .clkr = { 632 .enable_reg = 0x94, 633 .enable_mask = BIT(0), 634 .hw.init = &(const struct clk_init_data) { 635 .name = "nss_cc_mac2_tx_clk", 636 .parent_hws = (const struct clk_hw *[]) { 637 &nss_cc_mac2_tx_div_clk_src.clkr.hw, 638 }, 639 .num_parents = 1, 640 .flags = CLK_SET_RATE_PARENT, 641 .ops = &clk_branch2_prepare_ops, 642 }, 643 }, 644 }; 645 646 static struct clk_branch nss_cc_mac2_gephy1_tx_clk = { 647 .halt_reg = 0x98, 648 .halt_check = BRANCH_HALT, 649 .clkr = { 650 .enable_reg = 0x98, 651 .enable_mask = BIT(0), 652 .hw.init = &(const struct clk_init_data) { 653 .name = "nss_cc_mac2_gephy1_tx_clk", 654 .parent_hws = (const struct clk_hw *[]) { 655 &nss_cc_mac2_tx_div_clk_src.clkr.hw, 656 }, 657 .num_parents = 1, 658 .flags = CLK_SET_RATE_PARENT, 659 .ops = &clk_branch2_prepare_ops, 660 }, 661 }, 662 }; 663 664 static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_rx_clk = { 665 .halt_reg = 0x9c, 666 .halt_check = BRANCH_HALT, 667 .clkr = { 668 .enable_reg = 0x9c, 669 .enable_mask = BIT(0), 670 .hw.init = &(const struct clk_init_data) { 671 .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_clk", 672 .parent_hws = (const struct clk_hw *[]) { 673 &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr.hw, 674 }, 675 .num_parents = 1, 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_branch2_prepare_ops, 678 }, 679 }, 680 }; 681 682 static struct clk_rcg2 nss_cc_mac2_rx_clk_src = { 683 .cmd_rcgr = 0xa0, 684 .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, 685 .hid_width = 5, 686 .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, 687 .clkr.hw.init = &(const struct clk_init_data) { 688 .name = "nss_cc_mac2_rx_clk_src", 689 .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, 690 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), 691 .ops = &clk_rcg2_ops, 692 }, 693 }; 694 695 static struct clk_regmap_div nss_cc_mac2_rx_div_clk_src = { 696 .reg = 0xa8, 697 .shift = 0, 698 .width = 4, 699 .clkr = { 700 .hw.init = &(const struct clk_init_data) { 701 .name = "nss_cc_mac2_rx_div_clk_src", 702 .parent_hws = (const struct clk_hw *[]) { 703 &nss_cc_mac2_rx_clk_src.clkr.hw, 704 }, 705 .num_parents = 1, 706 .flags = CLK_SET_RATE_PARENT, 707 .ops = &clk_regmap_div_ops, 708 }, 709 }, 710 }; 711 712 static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src = { 713 .reg = 0xac, 714 .shift = 0, 715 .width = 4, 716 .clkr = { 717 .hw.init = &(const struct clk_init_data) { 718 .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src", 719 .parent_hws = (const struct clk_hw *[]) { 720 &nss_cc_mac2_rx_clk_src.clkr.hw, 721 }, 722 .num_parents = 1, 723 .flags = CLK_SET_RATE_PARENT, 724 .ops = &clk_regmap_div_ops, 725 }, 726 }, 727 }; 728 729 static struct clk_branch nss_cc_mac2_srds1_ch1_tx_clk = { 730 .halt_reg = 0xb0, 731 .halt_check = BRANCH_HALT, 732 .clkr = { 733 .enable_reg = 0xb0, 734 .enable_mask = BIT(0), 735 .hw.init = &(const struct clk_init_data) { 736 .name = "nss_cc_mac2_srds1_ch1_tx_clk", 737 .parent_hws = (const struct clk_hw *[]) { 738 &nss_cc_mac2_rx_div_clk_src.clkr.hw, 739 }, 740 .num_parents = 1, 741 .flags = CLK_SET_RATE_PARENT, 742 .ops = &clk_branch2_prepare_ops, 743 }, 744 }, 745 }; 746 747 static struct clk_branch nss_cc_mac2_rx_clk = { 748 .halt_reg = 0xb4, 749 .halt_check = BRANCH_HALT, 750 .clkr = { 751 .enable_reg = 0xb4, 752 .enable_mask = BIT(0), 753 .hw.init = &(const struct clk_init_data) { 754 .name = "nss_cc_mac2_rx_clk", 755 .parent_hws = (const struct clk_hw *[]) { 756 &nss_cc_mac2_rx_div_clk_src.clkr.hw, 757 }, 758 .num_parents = 1, 759 .flags = CLK_SET_RATE_PARENT, 760 .ops = &clk_branch2_prepare_ops, 761 }, 762 }, 763 }; 764 765 static struct clk_branch nss_cc_mac2_gephy1_rx_clk = { 766 .halt_reg = 0xb8, 767 .halt_check = BRANCH_HALT, 768 .clkr = { 769 .enable_reg = 0xb8, 770 .enable_mask = BIT(0), 771 .hw.init = &(const struct clk_init_data) { 772 .name = "nss_cc_mac2_gephy1_rx_clk", 773 .parent_hws = (const struct clk_hw *[]) { 774 &nss_cc_mac2_rx_div_clk_src.clkr.hw, 775 }, 776 .num_parents = 1, 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_branch2_prepare_ops, 779 }, 780 }, 781 }; 782 783 static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_tx_clk = { 784 .halt_reg = 0xbc, 785 .halt_check = BRANCH_HALT, 786 .clkr = { 787 .enable_reg = 0xbc, 788 .enable_mask = BIT(0), 789 .hw.init = &(const struct clk_init_data) { 790 .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_clk", 791 .parent_hws = (const struct clk_hw *[]) { 792 &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr.hw, 793 }, 794 .num_parents = 1, 795 .flags = CLK_SET_RATE_PARENT, 796 .ops = &clk_branch2_prepare_ops, 797 }, 798 }, 799 }; 800 801 static struct clk_rcg2 nss_cc_mac3_tx_clk_src = { 802 .cmd_rcgr = 0xc0, 803 .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, 804 .hid_width = 5, 805 .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, 806 .clkr.hw.init = &(const struct clk_init_data) { 807 .name = "nss_cc_mac3_tx_clk_src", 808 .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, 809 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), 810 .ops = &clk_rcg2_fm_ops, 811 }, 812 }; 813 814 static struct clk_regmap_div nss_cc_mac3_tx_div_clk_src = { 815 .reg = 0xc8, 816 .shift = 0, 817 .width = 4, 818 .clkr = { 819 .hw.init = &(const struct clk_init_data) { 820 .name = "nss_cc_mac3_tx_div_clk_src", 821 .parent_hws = (const struct clk_hw *[]) { 822 &nss_cc_mac3_tx_clk_src.clkr.hw, 823 }, 824 .num_parents = 1, 825 .flags = CLK_SET_RATE_PARENT, 826 .ops = &clk_regmap_div_ops, 827 }, 828 }, 829 }; 830 831 static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src = { 832 .reg = 0xcc, 833 .shift = 0, 834 .width = 4, 835 .clkr = { 836 .hw.init = &(const struct clk_init_data) { 837 .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src", 838 .parent_hws = (const struct clk_hw *[]) { 839 &nss_cc_mac3_tx_clk_src.clkr.hw, 840 }, 841 .num_parents = 1, 842 .flags = CLK_SET_RATE_PARENT, 843 .ops = &clk_regmap_div_ops, 844 }, 845 }, 846 }; 847 848 static struct clk_branch nss_cc_mac3_srds1_ch2_rx_clk = { 849 .halt_reg = 0xd0, 850 .halt_check = BRANCH_HALT, 851 .clkr = { 852 .enable_reg = 0xd0, 853 .enable_mask = BIT(0), 854 .hw.init = &(const struct clk_init_data) { 855 .name = "nss_cc_mac3_srds1_ch2_rx_clk", 856 .parent_hws = (const struct clk_hw *[]) { 857 &nss_cc_mac3_tx_div_clk_src.clkr.hw, 858 }, 859 .num_parents = 1, 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_branch2_prepare_ops, 862 }, 863 }, 864 }; 865 866 static struct clk_branch nss_cc_mac3_tx_clk = { 867 .halt_reg = 0xd4, 868 .halt_check = BRANCH_HALT, 869 .clkr = { 870 .enable_reg = 0xd4, 871 .enable_mask = BIT(0), 872 .hw.init = &(const struct clk_init_data) { 873 .name = "nss_cc_mac3_tx_clk", 874 .parent_hws = (const struct clk_hw *[]) { 875 &nss_cc_mac3_tx_div_clk_src.clkr.hw, 876 }, 877 .num_parents = 1, 878 .flags = CLK_SET_RATE_PARENT, 879 .ops = &clk_branch2_prepare_ops, 880 }, 881 }, 882 }; 883 884 static struct clk_branch nss_cc_mac3_gephy2_tx_clk = { 885 .halt_reg = 0xd8, 886 .halt_check = BRANCH_HALT, 887 .clkr = { 888 .enable_reg = 0xd8, 889 .enable_mask = BIT(0), 890 .hw.init = &(const struct clk_init_data) { 891 .name = "nss_cc_mac3_gephy2_tx_clk", 892 .parent_hws = (const struct clk_hw *[]) { 893 &nss_cc_mac3_tx_div_clk_src.clkr.hw, 894 }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT, 897 .ops = &clk_branch2_prepare_ops, 898 }, 899 }, 900 }; 901 902 static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_rx_clk = { 903 .halt_reg = 0xdc, 904 .halt_check = BRANCH_HALT, 905 .clkr = { 906 .enable_reg = 0xdc, 907 .enable_mask = BIT(0), 908 .hw.init = &(const struct clk_init_data) { 909 .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_clk", 910 .parent_hws = (const struct clk_hw *[]) { 911 &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr.hw, 912 }, 913 .num_parents = 1, 914 .flags = CLK_SET_RATE_PARENT, 915 .ops = &clk_branch2_prepare_ops, 916 }, 917 }, 918 }; 919 920 static struct clk_rcg2 nss_cc_mac3_rx_clk_src = { 921 .cmd_rcgr = 0xe0, 922 .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, 923 .hid_width = 5, 924 .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, 925 .clkr.hw.init = &(const struct clk_init_data) { 926 .name = "nss_cc_mac3_rx_clk_src", 927 .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, 928 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), 929 .ops = &clk_rcg2_ops, 930 }, 931 }; 932 933 static struct clk_regmap_div nss_cc_mac3_rx_div_clk_src = { 934 .reg = 0xe8, 935 .shift = 0, 936 .width = 4, 937 .clkr = { 938 .hw.init = &(const struct clk_init_data) { 939 .name = "nss_cc_mac3_rx_div_clk_src", 940 .parent_hws = (const struct clk_hw *[]) { 941 &nss_cc_mac3_rx_clk_src.clkr.hw, 942 }, 943 .num_parents = 1, 944 .flags = CLK_SET_RATE_PARENT, 945 .ops = &clk_regmap_div_ops, 946 }, 947 }, 948 }; 949 950 static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src = { 951 .reg = 0xec, 952 .shift = 0, 953 .width = 4, 954 .clkr = { 955 .hw.init = &(const struct clk_init_data) { 956 .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src", 957 .parent_hws = (const struct clk_hw *[]) { 958 &nss_cc_mac3_rx_clk_src.clkr.hw, 959 }, 960 .num_parents = 1, 961 .flags = CLK_SET_RATE_PARENT, 962 .ops = &clk_regmap_div_ops, 963 }, 964 }, 965 }; 966 967 static struct clk_branch nss_cc_mac3_srds1_ch2_tx_clk = { 968 .halt_reg = 0xf0, 969 .halt_check = BRANCH_HALT, 970 .clkr = { 971 .enable_reg = 0xf0, 972 .enable_mask = BIT(0), 973 .hw.init = &(const struct clk_init_data) { 974 .name = "nss_cc_mac3_srds1_ch2_tx_clk", 975 .parent_hws = (const struct clk_hw *[]) { 976 &nss_cc_mac3_rx_div_clk_src.clkr.hw, 977 }, 978 .num_parents = 1, 979 .flags = CLK_SET_RATE_PARENT, 980 .ops = &clk_branch2_prepare_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_branch nss_cc_mac3_rx_clk = { 986 .halt_reg = 0xf4, 987 .halt_check = BRANCH_HALT, 988 .clkr = { 989 .enable_reg = 0xf4, 990 .enable_mask = BIT(0), 991 .hw.init = &(const struct clk_init_data) { 992 .name = "nss_cc_mac3_rx_clk", 993 .parent_hws = (const struct clk_hw *[]) { 994 &nss_cc_mac3_rx_div_clk_src.clkr.hw, 995 }, 996 .num_parents = 1, 997 .flags = CLK_SET_RATE_PARENT, 998 .ops = &clk_branch2_prepare_ops, 999 }, 1000 }, 1001 }; 1002 1003 static struct clk_branch nss_cc_mac3_gephy2_rx_clk = { 1004 .halt_reg = 0xf8, 1005 .halt_check = BRANCH_HALT, 1006 .clkr = { 1007 .enable_reg = 0xf8, 1008 .enable_mask = BIT(0), 1009 .hw.init = &(const struct clk_init_data) { 1010 .name = "nss_cc_mac3_gephy2_rx_clk", 1011 .parent_hws = (const struct clk_hw *[]) { 1012 &nss_cc_mac3_rx_div_clk_src.clkr.hw, 1013 }, 1014 .num_parents = 1, 1015 .flags = CLK_SET_RATE_PARENT, 1016 .ops = &clk_branch2_prepare_ops, 1017 }, 1018 }, 1019 }; 1020 1021 static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_tx_clk = { 1022 .halt_reg = 0xfc, 1023 .halt_check = BRANCH_HALT, 1024 .clkr = { 1025 .enable_reg = 0xfc, 1026 .enable_mask = BIT(0), 1027 .hw.init = &(const struct clk_init_data) { 1028 .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_clk", 1029 .parent_hws = (const struct clk_hw *[]) { 1030 &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr.hw, 1031 }, 1032 .num_parents = 1, 1033 .flags = CLK_SET_RATE_PARENT, 1034 .ops = &clk_branch2_prepare_ops, 1035 }, 1036 }, 1037 }; 1038 1039 static const struct clk_parent_data nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data[] = { 1040 { .index = DT_XO }, 1041 { .index = DT_UNIPHY0_RX_CLK }, 1042 { .index = DT_UNIPHY1_TX312P5M_CLK }, 1043 { .index = DT_UNIPHY1_RX312P5M_CLK }, 1044 }; 1045 1046 static const struct parent_map nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map[] = { 1047 { P_XO, 0 }, 1048 { P_UNIPHY0_RX, 1 }, 1049 { P_UNIPHY1_TX312P5M, 3 }, 1050 { P_UNIPHY1_RX312P5M, 7 }, 1051 }; 1052 1053 static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_25[] = { 1054 C(P_UNIPHY0_RX, 12.5, 0, 0), 1055 C(P_UNIPHY0_RX, 5, 0, 0), 1056 C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), 1057 C(P_UNIPHY1_RX312P5M, 12.5, 0, 0), 1058 }; 1059 1060 static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_125[] = { 1061 C(P_UNIPHY0_RX, 1, 0, 0), 1062 C(P_UNIPHY0_RX, 2.5, 0, 0), 1063 C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), 1064 C(P_UNIPHY1_RX312P5M, 2.5, 0, 0), 1065 }; 1066 1067 static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_312p5[] = { 1068 C(P_UNIPHY0_RX, 1, 0, 0), 1069 C(P_UNIPHY1_TX312P5M, 1, 0, 0), 1070 C(P_UNIPHY1_RX312P5M, 1, 0, 0), 1071 }; 1072 1073 static const struct freq_multi_tbl ftbl_nss_cc_mac4_tx_clk_src[] = { 1074 FM(25000000, ftbl_nss_cc_mac4_tx_clk_src_25), 1075 FMS(50000000, P_XO, 1, 0, 0), 1076 FM(125000000, ftbl_nss_cc_mac4_tx_clk_src_125), 1077 FM(312500000, ftbl_nss_cc_mac4_tx_clk_src_312p5), 1078 { } 1079 }; 1080 1081 static struct clk_rcg2 nss_cc_mac4_tx_clk_src = { 1082 .cmd_rcgr = 0x100, 1083 .freq_multi_tbl = ftbl_nss_cc_mac4_tx_clk_src, 1084 .hid_width = 5, 1085 .parent_map = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map, 1086 .clkr.hw.init = &(const struct clk_init_data) { 1087 .name = "nss_cc_mac4_tx_clk_src", 1088 .parent_data = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data, 1089 .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data), 1090 .ops = &clk_rcg2_fm_ops, 1091 }, 1092 }; 1093 1094 static struct clk_regmap_div nss_cc_mac4_tx_div_clk_src = { 1095 .reg = 0x108, 1096 .shift = 0, 1097 .width = 4, 1098 .clkr = { 1099 .hw.init = &(const struct clk_init_data) { 1100 .name = "nss_cc_mac4_tx_div_clk_src", 1101 .parent_hws = (const struct clk_hw *[]) { 1102 &nss_cc_mac4_tx_clk_src.clkr.hw, 1103 }, 1104 .num_parents = 1, 1105 .flags = CLK_SET_RATE_PARENT, 1106 .ops = &clk_regmap_div_ops, 1107 }, 1108 }, 1109 }; 1110 1111 static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src = { 1112 .reg = 0x10c, 1113 .shift = 0, 1114 .width = 4, 1115 .clkr = { 1116 .hw.init = &(const struct clk_init_data) { 1117 .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src", 1118 .parent_hws = (const struct clk_hw *[]) { 1119 &nss_cc_mac4_tx_clk_src.clkr.hw, 1120 }, 1121 .num_parents = 1, 1122 .flags = CLK_SET_RATE_PARENT, 1123 .ops = &clk_regmap_div_ops, 1124 }, 1125 }, 1126 }; 1127 1128 static struct clk_branch nss_cc_mac4_srds1_ch3_rx_clk = { 1129 .halt_reg = 0x110, 1130 .halt_check = BRANCH_HALT, 1131 .clkr = { 1132 .enable_reg = 0x110, 1133 .enable_mask = BIT(0), 1134 .hw.init = &(const struct clk_init_data) { 1135 .name = "nss_cc_mac4_srds1_ch3_rx_clk", 1136 .parent_hws = (const struct clk_hw *[]) { 1137 &nss_cc_mac4_tx_div_clk_src.clkr.hw, 1138 }, 1139 .num_parents = 1, 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_branch2_prepare_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch nss_cc_mac4_tx_clk = { 1147 .halt_reg = 0x114, 1148 .halt_check = BRANCH_HALT, 1149 .clkr = { 1150 .enable_reg = 0x114, 1151 .enable_mask = BIT(0), 1152 .hw.init = &(const struct clk_init_data) { 1153 .name = "nss_cc_mac4_tx_clk", 1154 .parent_hws = (const struct clk_hw *[]) { 1155 &nss_cc_mac4_tx_div_clk_src.clkr.hw, 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 .ops = &clk_branch2_prepare_ops, 1160 }, 1161 }, 1162 }; 1163 1164 static struct clk_branch nss_cc_mac4_gephy3_tx_clk = { 1165 .halt_reg = 0x118, 1166 .halt_check = BRANCH_HALT, 1167 .clkr = { 1168 .enable_reg = 0x118, 1169 .enable_mask = BIT(0), 1170 .hw.init = &(const struct clk_init_data) { 1171 .name = "nss_cc_mac4_gephy3_tx_clk", 1172 .parent_hws = (const struct clk_hw *[]) { 1173 &nss_cc_mac4_tx_div_clk_src.clkr.hw, 1174 }, 1175 .num_parents = 1, 1176 .flags = CLK_SET_RATE_PARENT, 1177 .ops = &clk_branch2_prepare_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_rx_clk = { 1183 .halt_reg = 0x11c, 1184 .halt_check = BRANCH_HALT, 1185 .clkr = { 1186 .enable_reg = 0x11c, 1187 .enable_mask = BIT(0), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_clk", 1190 .parent_hws = (const struct clk_hw *[]) { 1191 &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr.hw, 1192 }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_prepare_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static const struct clk_parent_data nss_cc_uniphy0_tx_uniphy1_tx312p5m_data[] = { 1201 { .index = DT_XO }, 1202 { .index = DT_UNIPHY0_TX_CLK }, 1203 { .index = DT_UNIPHY1_TX312P5M_CLK }, 1204 }; 1205 1206 static const struct parent_map nss_cc_uniphy0_tx_uniphy1_tx312p5m_map[] = { 1207 { P_XO, 0 }, 1208 { P_UNIPHY0_TX, 2 }, 1209 { P_UNIPHY1_TX312P5M, 3 }, 1210 }; 1211 1212 static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_25[] = { 1213 C(P_UNIPHY0_TX, 12.5, 0, 0), 1214 C(P_UNIPHY0_TX, 5, 0, 0), 1215 C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), 1216 }; 1217 1218 static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_125[] = { 1219 C(P_UNIPHY0_TX, 1, 0, 0), 1220 C(P_UNIPHY0_TX, 2.5, 0, 0), 1221 C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), 1222 }; 1223 1224 static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_312p5[] = { 1225 C(P_UNIPHY0_TX, 1, 0, 0), 1226 C(P_UNIPHY1_TX312P5M, 1, 0, 0), 1227 }; 1228 1229 static const struct freq_multi_tbl ftbl_nss_cc_mac4_rx_clk_src[] = { 1230 FM(25000000, ftbl_nss_cc_mac4_rx_clk_src_25), 1231 FMS(50000000, P_XO, 1, 0, 0), 1232 FM(125000000, ftbl_nss_cc_mac4_rx_clk_src_125), 1233 FM(312500000, ftbl_nss_cc_mac4_rx_clk_src_312p5), 1234 { } 1235 }; 1236 1237 static struct clk_rcg2 nss_cc_mac4_rx_clk_src = { 1238 .cmd_rcgr = 0x120, 1239 .freq_multi_tbl = ftbl_nss_cc_mac4_rx_clk_src, 1240 .hid_width = 5, 1241 .parent_map = nss_cc_uniphy0_tx_uniphy1_tx312p5m_map, 1242 .clkr.hw.init = &(const struct clk_init_data) { 1243 .name = "nss_cc_mac4_rx_clk_src", 1244 .parent_data = nss_cc_uniphy0_tx_uniphy1_tx312p5m_data, 1245 .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_uniphy1_tx312p5m_data), 1246 .ops = &clk_rcg2_fm_ops, 1247 }, 1248 }; 1249 1250 static struct clk_regmap_div nss_cc_mac4_rx_div_clk_src = { 1251 .reg = 0x128, 1252 .shift = 0, 1253 .width = 4, 1254 .clkr = { 1255 .hw.init = &(const struct clk_init_data) { 1256 .name = "nss_cc_mac4_rx_div_clk_src", 1257 .parent_hws = (const struct clk_hw *[]) { 1258 &nss_cc_mac4_rx_clk_src.clkr.hw, 1259 }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_regmap_div_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src = { 1268 .reg = 0x12c, 1269 .shift = 0, 1270 .width = 4, 1271 .clkr = { 1272 .hw.init = &(const struct clk_init_data) { 1273 .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src", 1274 .parent_hws = (const struct clk_hw *[]) { 1275 &nss_cc_mac4_rx_clk_src.clkr.hw, 1276 }, 1277 .num_parents = 1, 1278 .flags = CLK_SET_RATE_PARENT, 1279 .ops = &clk_regmap_div_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch nss_cc_mac4_srds1_ch3_tx_clk = { 1285 .halt_reg = 0x130, 1286 .halt_check = BRANCH_HALT, 1287 .clkr = { 1288 .enable_reg = 0x130, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(const struct clk_init_data) { 1291 .name = "nss_cc_mac4_srds1_ch3_tx_clk", 1292 .parent_hws = (const struct clk_hw *[]) { 1293 &nss_cc_mac4_rx_div_clk_src.clkr.hw, 1294 }, 1295 .num_parents = 1, 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_branch2_prepare_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_branch nss_cc_mac4_rx_clk = { 1303 .halt_reg = 0x134, 1304 .halt_check = BRANCH_HALT, 1305 .clkr = { 1306 .enable_reg = 0x134, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(const struct clk_init_data) { 1309 .name = "nss_cc_mac4_rx_clk", 1310 .parent_hws = (const struct clk_hw *[]) { 1311 &nss_cc_mac4_rx_div_clk_src.clkr.hw, 1312 }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 .ops = &clk_branch2_prepare_ops, 1316 }, 1317 }, 1318 }; 1319 1320 static struct clk_branch nss_cc_mac4_gephy3_rx_clk = { 1321 .halt_reg = 0x138, 1322 .halt_check = BRANCH_HALT, 1323 .clkr = { 1324 .enable_reg = 0x138, 1325 .enable_mask = BIT(0), 1326 .hw.init = &(const struct clk_init_data) { 1327 .name = "nss_cc_mac4_gephy3_rx_clk", 1328 .parent_hws = (const struct clk_hw *[]) { 1329 &nss_cc_mac4_rx_div_clk_src.clkr.hw, 1330 }, 1331 .num_parents = 1, 1332 .flags = CLK_SET_RATE_PARENT, 1333 .ops = &clk_branch2_prepare_ops, 1334 }, 1335 }, 1336 }; 1337 1338 static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_tx_clk = { 1339 .halt_reg = 0x13c, 1340 .halt_check = BRANCH_HALT, 1341 .clkr = { 1342 .enable_reg = 0x13c, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(const struct clk_init_data) { 1345 .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_clk", 1346 .parent_hws = (const struct clk_hw *[]) { 1347 &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr.hw, 1348 }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_prepare_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static const struct clk_parent_data nss_cc_uniphy0_tx_data[] = { 1357 { .index = DT_XO }, 1358 { .index = DT_UNIPHY0_TX_CLK }, 1359 }; 1360 1361 static const struct parent_map nss_cc_uniphy0_tx_map[] = { 1362 { P_XO, 0 }, 1363 { P_UNIPHY0_TX, 2 }, 1364 }; 1365 1366 static struct clk_rcg2 nss_cc_mac5_tx_clk_src = { 1367 .cmd_rcgr = 0x140, 1368 .hid_width = 5, 1369 .parent_map = nss_cc_uniphy0_tx_map, 1370 .clkr.hw.init = &(const struct clk_init_data) { 1371 .name = "nss_cc_mac5_tx_clk_src", 1372 .parent_data = nss_cc_uniphy0_tx_data, 1373 .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_data), 1374 .flags = CLK_SET_RATE_PARENT, 1375 .ops = &clk_rcg2_mux_closest_ops, 1376 }, 1377 }; 1378 1379 static struct clk_regmap_div nss_cc_mac5_tx_div_clk_src = { 1380 .reg = 0x148, 1381 .shift = 0, 1382 .width = 4, 1383 .clkr = { 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "nss_cc_mac5_tx_div_clk_src", 1386 .parent_hws = (const struct clk_hw *[]) { 1387 &nss_cc_mac5_tx_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_regmap_div_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch nss_cc_mac5_tx_clk = { 1397 .halt_reg = 0x14c, 1398 .halt_check = BRANCH_HALT, 1399 .clkr = { 1400 .enable_reg = 0x14c, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "nss_cc_mac5_tx_clk", 1404 .parent_hws = (const struct clk_hw *[]) { 1405 &nss_cc_mac5_tx_div_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_prepare_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static const struct clk_parent_data nss_cc_uniphy0_rx_tx_data[] = { 1415 { .index = DT_XO }, 1416 { .index = DT_UNIPHY0_RX_CLK }, 1417 { .index = DT_UNIPHY0_TX_CLK }, 1418 }; 1419 1420 static const struct parent_map nss_cc_uniphy0_rx_tx_map[] = { 1421 { P_XO, 0 }, 1422 { P_UNIPHY0_RX, 1 }, 1423 { P_UNIPHY0_TX, 2 }, 1424 }; 1425 1426 static struct clk_rcg2 nss_cc_mac5_rx_clk_src = { 1427 .cmd_rcgr = 0x154, 1428 .hid_width = 5, 1429 .parent_map = nss_cc_uniphy0_rx_tx_map, 1430 .clkr.hw.init = &(const struct clk_init_data) { 1431 .name = "nss_cc_mac5_rx_clk_src", 1432 .parent_data = nss_cc_uniphy0_rx_tx_data, 1433 .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_tx_data), 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_rcg2_mux_closest_ops, 1436 }, 1437 }; 1438 1439 static struct clk_regmap_div nss_cc_mac5_rx_div_clk_src = { 1440 .reg = 0x15c, 1441 .shift = 0, 1442 .width = 4, 1443 .clkr = { 1444 .hw.init = &(const struct clk_init_data) { 1445 .name = "nss_cc_mac5_rx_div_clk_src", 1446 .parent_hws = (const struct clk_hw *[]) { 1447 &nss_cc_mac5_rx_clk_src.clkr.hw, 1448 }, 1449 .num_parents = 1, 1450 .flags = CLK_SET_RATE_PARENT, 1451 .ops = &clk_regmap_div_ops, 1452 }, 1453 }, 1454 }; 1455 1456 static struct clk_branch nss_cc_mac5_rx_clk = { 1457 .halt_reg = 0x160, 1458 .halt_check = BRANCH_HALT, 1459 .clkr = { 1460 .enable_reg = 0x160, 1461 .enable_mask = BIT(0), 1462 .hw.init = &(const struct clk_init_data) { 1463 .name = "nss_cc_mac5_rx_clk", 1464 .parent_hws = (const struct clk_hw *[]) { 1465 &nss_cc_mac5_rx_div_clk_src.clkr.hw, 1466 }, 1467 .num_parents = 1, 1468 .flags = CLK_SET_RATE_PARENT, 1469 .ops = &clk_branch2_prepare_ops, 1470 }, 1471 }, 1472 }; 1473 1474 static const struct parent_map nss_cc_mac4_rx_div_mac5_tx_div_map[] = { 1475 { P_MAC4_RX_DIV, 0 }, 1476 { P_MAC5_TX_DIV, 1 }, 1477 }; 1478 1479 static struct clk_regmap_mux nss_cc_mac5_tx_srds0_clk_src = { 1480 .reg = 0x300, 1481 .shift = 0, 1482 .width = 1, 1483 .parent_map = nss_cc_mac4_rx_div_mac5_tx_div_map, 1484 .clkr = { 1485 .hw.init = &(const struct clk_init_data) { 1486 .name = "nss_cc_mac5_tx_srds0_clk_src", 1487 .parent_hws = (const struct clk_hw *[]) { 1488 &nss_cc_mac4_rx_div_clk_src.clkr.hw, 1489 &nss_cc_mac5_tx_div_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 2, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_regmap_mux_closest_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch nss_cc_mac5_tx_srds0_clk = { 1499 .halt_reg = 0x150, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x150, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "nss_cc_mac5_tx_srds0_clk", 1506 .parent_hws = (const struct clk_hw *[]) { 1507 &nss_cc_mac5_tx_srds0_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_prepare_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static const struct parent_map nss_cc_mac4_tx_div_mac5_rx_div_map[] = { 1517 { P_MAC4_TX_DIV, 0 }, 1518 { P_MAC5_RX_DIV, 1 }, 1519 }; 1520 1521 static struct clk_regmap_mux nss_cc_mac5_rx_srds0_clk_src = { 1522 .reg = 0x300, 1523 .shift = 1, 1524 .width = 1, 1525 .parent_map = nss_cc_mac4_tx_div_mac5_rx_div_map, 1526 .clkr = { 1527 .hw.init = &(const struct clk_init_data) { 1528 .name = "nss_cc_mac5_rx_srds0_clk_src", 1529 .parent_hws = (const struct clk_hw *[]) { 1530 &nss_cc_mac4_tx_div_clk_src.clkr.hw, 1531 &nss_cc_mac5_rx_div_clk_src.clkr.hw, 1532 }, 1533 .num_parents = 2, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_regmap_mux_closest_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch nss_cc_mac5_rx_srds0_clk = { 1541 .halt_reg = 0x164, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0x164, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(const struct clk_init_data) { 1547 .name = "nss_cc_mac5_rx_srds0_clk", 1548 .parent_hws = (const struct clk_hw *[]) { 1549 &nss_cc_mac5_rx_srds0_clk_src.clkr.hw, 1550 }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_prepare_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static const struct parent_map nss_cc_uniphy1_tx312p5m_map2[] = { 1559 { P_XO, 0 }, 1560 { P_UNIPHY1_TX312P5M, 2 }, 1561 }; 1562 1563 static const struct freq_tbl ftbl_nss_cc_ahb_clk_src[] = { 1564 F(50000000, P_XO, 1, 0, 0), 1565 F(104170000, P_UNIPHY1_TX312P5M, 3, 0, 0), 1566 { } 1567 }; 1568 1569 static struct clk_rcg2 nss_cc_ahb_clk_src = { 1570 .cmd_rcgr = 0x168, 1571 .freq_tbl = ftbl_nss_cc_ahb_clk_src, 1572 .hid_width = 5, 1573 .parent_map = nss_cc_uniphy1_tx312p5m_map2, 1574 .clkr.hw.init = &(const struct clk_init_data) { 1575 .name = "nss_cc_ahb_clk_src", 1576 .parent_data = nss_cc_uniphy1_tx312p5m_data, 1577 .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data), 1578 .ops = &clk_rcg2_ops, 1579 }, 1580 }; 1581 1582 static struct clk_branch nss_cc_ahb_clk = { 1583 .halt_reg = 0x170, 1584 .halt_check = BRANCH_HALT, 1585 .clkr = { 1586 .enable_reg = 0x170, 1587 .enable_mask = BIT(0), 1588 .hw.init = &(const struct clk_init_data) { 1589 .name = "nss_cc_ahb_clk", 1590 .parent_hws = (const struct clk_hw *[]) { 1591 &nss_cc_ahb_clk_src.clkr.hw, 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_prepare_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch nss_cc_sec_ctrl_ahb_clk = { 1601 .halt_reg = 0x174, 1602 .halt_check = BRANCH_HALT, 1603 .clkr = { 1604 .enable_reg = 0x174, 1605 .enable_mask = BIT(0), 1606 .hw.init = &(const struct clk_init_data) { 1607 .name = "nss_cc_sec_ctrl_ahb_clk", 1608 .parent_hws = (const struct clk_hw *[]) { 1609 &nss_cc_ahb_clk_src.clkr.hw, 1610 }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_prepare_ops, 1614 }, 1615 }, 1616 }; 1617 1618 static struct clk_branch nss_cc_tlmm_clk = { 1619 .halt_reg = 0x178, 1620 .halt_check = BRANCH_HALT, 1621 .clkr = { 1622 .enable_reg = 0x178, 1623 .enable_mask = BIT(0), 1624 .hw.init = &(const struct clk_init_data) { 1625 .name = "nss_cc_tlmm_clk", 1626 .parent_hws = (const struct clk_hw *[]) { 1627 &nss_cc_ahb_clk_src.clkr.hw, 1628 }, 1629 .num_parents = 1, 1630 .flags = CLK_SET_RATE_PARENT, 1631 .ops = &clk_branch2_prepare_ops, 1632 }, 1633 }, 1634 }; 1635 1636 static struct clk_branch nss_cc_tlmm_ahb_clk = { 1637 .halt_reg = 0x190, 1638 .halt_check = BRANCH_HALT, 1639 .clkr = { 1640 .enable_reg = 0x190, 1641 .enable_mask = BIT(0), 1642 .hw.init = &(const struct clk_init_data) { 1643 .name = "nss_cc_tlmm_ahb_clk", 1644 .parent_hws = (const struct clk_hw *[]) { 1645 &nss_cc_ahb_clk_src.clkr.hw, 1646 }, 1647 .num_parents = 1, 1648 .flags = CLK_SET_RATE_PARENT, 1649 .ops = &clk_branch2_prepare_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch nss_cc_cnoc_ahb_clk = { 1655 .halt_reg = 0x194, 1656 .halt_check = BRANCH_HALT, 1657 .clkr = { 1658 .enable_reg = 0x194, 1659 .enable_mask = BIT(0), 1660 .hw.init = &(const struct clk_init_data) { 1661 .name = "nss_cc_cnoc_ahb_clk", 1662 .parent_hws = (const struct clk_hw *[]) { 1663 &nss_cc_ahb_clk_src.clkr.hw, 1664 }, 1665 .num_parents = 1, 1666 .flags = CLK_SET_RATE_PARENT, 1667 .ops = &clk_branch2_prepare_ops, 1668 }, 1669 }, 1670 }; 1671 1672 static struct clk_branch nss_cc_mdio_ahb_clk = { 1673 .halt_reg = 0x198, 1674 .halt_check = BRANCH_HALT, 1675 .clkr = { 1676 .enable_reg = 0x198, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(const struct clk_init_data) { 1679 .name = "nss_cc_mdio_ahb_clk", 1680 .parent_hws = (const struct clk_hw *[]) { 1681 &nss_cc_ahb_clk_src.clkr.hw, 1682 }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_prepare_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch nss_cc_mdio_master_ahb_clk = { 1691 .halt_reg = 0x19c, 1692 .halt_check = BRANCH_HALT, 1693 .clkr = { 1694 .enable_reg = 0x19c, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(const struct clk_init_data) { 1697 .name = "nss_cc_mdio_master_ahb_clk", 1698 .parent_hws = (const struct clk_hw *[]) { 1699 &nss_cc_ahb_clk_src.clkr.hw, 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_prepare_ops, 1704 }, 1705 }, 1706 }; 1707 1708 static const struct clk_parent_data nss_cc_xo_data[] = { 1709 { .index = DT_XO }, 1710 }; 1711 1712 static const struct parent_map nss_cc_xo_map[] = { 1713 { P_XO, 0 }, 1714 }; 1715 1716 static const struct freq_tbl ftbl_nss_cc_sys_clk_src[] = { 1717 F(25000000, P_XO, 2, 0, 0), 1718 { } 1719 }; 1720 1721 static struct clk_rcg2 nss_cc_sys_clk_src = { 1722 .cmd_rcgr = 0x1a0, 1723 .freq_tbl = ftbl_nss_cc_sys_clk_src, 1724 .hid_width = 5, 1725 .parent_map = nss_cc_xo_map, 1726 .clkr.hw.init = &(const struct clk_init_data) { 1727 .name = "nss_cc_sys_clk_src", 1728 .parent_data = nss_cc_xo_data, 1729 .num_parents = ARRAY_SIZE(nss_cc_xo_data), 1730 .ops = &clk_rcg2_ops, 1731 }, 1732 }; 1733 1734 static struct clk_branch nss_cc_srds0_sys_clk = { 1735 .halt_reg = 0x1a8, 1736 .halt_check = BRANCH_HALT, 1737 .clkr = { 1738 .enable_reg = 0x1a8, 1739 .enable_mask = BIT(0), 1740 .hw.init = &(const struct clk_init_data) { 1741 .name = "nss_cc_srds0_sys_clk", 1742 .parent_hws = (const struct clk_hw *[]) { 1743 &nss_cc_sys_clk_src.clkr.hw, 1744 }, 1745 .num_parents = 1, 1746 .ops = &clk_branch2_prepare_ops, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch nss_cc_srds1_sys_clk = { 1752 .halt_reg = 0x1ac, 1753 .halt_check = BRANCH_HALT, 1754 .clkr = { 1755 .enable_reg = 0x1ac, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(const struct clk_init_data) { 1758 .name = "nss_cc_srds1_sys_clk", 1759 .parent_hws = (const struct clk_hw *[]) { 1760 &nss_cc_sys_clk_src.clkr.hw, 1761 }, 1762 .num_parents = 1, 1763 .ops = &clk_branch2_prepare_ops, 1764 }, 1765 }, 1766 }; 1767 1768 static struct clk_branch nss_cc_gephy0_sys_clk = { 1769 .halt_reg = 0x1b0, 1770 .halt_check = BRANCH_HALT, 1771 .clkr = { 1772 .enable_reg = 0x1b0, 1773 .enable_mask = BIT(0), 1774 .hw.init = &(const struct clk_init_data) { 1775 .name = "nss_cc_gephy0_sys_clk", 1776 .parent_hws = (const struct clk_hw *[]) { 1777 &nss_cc_sys_clk_src.clkr.hw, 1778 }, 1779 .num_parents = 1, 1780 .ops = &clk_branch2_prepare_ops, 1781 }, 1782 }, 1783 }; 1784 1785 static struct clk_branch nss_cc_gephy1_sys_clk = { 1786 .halt_reg = 0x1b4, 1787 .halt_check = BRANCH_HALT, 1788 .clkr = { 1789 .enable_reg = 0x1b4, 1790 .enable_mask = BIT(0), 1791 .hw.init = &(const struct clk_init_data) { 1792 .name = "nss_cc_gephy1_sys_clk", 1793 .parent_hws = (const struct clk_hw *[]) { 1794 &nss_cc_sys_clk_src.clkr.hw, 1795 }, 1796 .num_parents = 1, 1797 .ops = &clk_branch2_prepare_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch nss_cc_gephy2_sys_clk = { 1803 .halt_reg = 0x1b8, 1804 .halt_check = BRANCH_HALT, 1805 .clkr = { 1806 .enable_reg = 0x1b8, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(const struct clk_init_data) { 1809 .name = "nss_cc_gephy2_sys_clk", 1810 .parent_hws = (const struct clk_hw *[]) { 1811 &nss_cc_sys_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .ops = &clk_branch2_prepare_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch nss_cc_gephy3_sys_clk = { 1820 .halt_reg = 0x1bc, 1821 .halt_check = BRANCH_HALT, 1822 .clkr = { 1823 .enable_reg = 0x1bc, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(const struct clk_init_data) { 1826 .name = "nss_cc_gephy3_sys_clk", 1827 .parent_hws = (const struct clk_hw *[]) { 1828 &nss_cc_sys_clk_src.clkr.hw, 1829 }, 1830 .num_parents = 1, 1831 .ops = &clk_branch2_prepare_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_regmap *nss_cc_qca8k_clocks[] = { 1837 [NSS_CC_SWITCH_CORE_CLK_SRC] = &nss_cc_switch_core_clk_src.clkr, 1838 [NSS_CC_SWITCH_CORE_CLK] = &nss_cc_switch_core_clk.clkr, 1839 [NSS_CC_APB_BRIDGE_CLK] = &nss_cc_apb_bridge_clk.clkr, 1840 [NSS_CC_MAC0_TX_CLK_SRC] = &nss_cc_mac0_tx_clk_src.clkr, 1841 [NSS_CC_MAC0_TX_DIV_CLK_SRC] = &nss_cc_mac0_tx_div_clk_src.clkr, 1842 [NSS_CC_MAC0_TX_CLK] = &nss_cc_mac0_tx_clk.clkr, 1843 [NSS_CC_MAC0_TX_SRDS1_CLK] = &nss_cc_mac0_tx_srds1_clk.clkr, 1844 [NSS_CC_MAC0_RX_CLK_SRC] = &nss_cc_mac0_rx_clk_src.clkr, 1845 [NSS_CC_MAC0_RX_DIV_CLK_SRC] = &nss_cc_mac0_rx_div_clk_src.clkr, 1846 [NSS_CC_MAC0_RX_CLK] = &nss_cc_mac0_rx_clk.clkr, 1847 [NSS_CC_MAC0_RX_SRDS1_CLK] = &nss_cc_mac0_rx_srds1_clk.clkr, 1848 [NSS_CC_MAC1_TX_CLK_SRC] = &nss_cc_mac1_tx_clk_src.clkr, 1849 [NSS_CC_MAC1_TX_DIV_CLK_SRC] = &nss_cc_mac1_tx_div_clk_src.clkr, 1850 [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC] = 1851 &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr, 1852 [NSS_CC_MAC1_SRDS1_CH0_RX_CLK] = &nss_cc_mac1_srds1_ch0_rx_clk.clkr, 1853 [NSS_CC_MAC1_TX_CLK] = &nss_cc_mac1_tx_clk.clkr, 1854 [NSS_CC_MAC1_GEPHY0_TX_CLK] = &nss_cc_mac1_gephy0_tx_clk.clkr, 1855 [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_rx_clk.clkr, 1856 [NSS_CC_MAC1_RX_CLK_SRC] = &nss_cc_mac1_rx_clk_src.clkr, 1857 [NSS_CC_MAC1_RX_DIV_CLK_SRC] = &nss_cc_mac1_rx_div_clk_src.clkr, 1858 [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC] = 1859 &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr, 1860 [NSS_CC_MAC1_SRDS1_CH0_TX_CLK] = &nss_cc_mac1_srds1_ch0_tx_clk.clkr, 1861 [NSS_CC_MAC1_RX_CLK] = &nss_cc_mac1_rx_clk.clkr, 1862 [NSS_CC_MAC1_GEPHY0_RX_CLK] = &nss_cc_mac1_gephy0_rx_clk.clkr, 1863 [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_tx_clk.clkr, 1864 [NSS_CC_MAC2_TX_CLK_SRC] = &nss_cc_mac2_tx_clk_src.clkr, 1865 [NSS_CC_MAC2_TX_DIV_CLK_SRC] = &nss_cc_mac2_tx_div_clk_src.clkr, 1866 [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC] = 1867 &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr, 1868 [NSS_CC_MAC2_SRDS1_CH1_RX_CLK] = &nss_cc_mac2_srds1_ch1_rx_clk.clkr, 1869 [NSS_CC_MAC2_TX_CLK] = &nss_cc_mac2_tx_clk.clkr, 1870 [NSS_CC_MAC2_GEPHY1_TX_CLK] = &nss_cc_mac2_gephy1_tx_clk.clkr, 1871 [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_rx_clk.clkr, 1872 [NSS_CC_MAC2_RX_CLK_SRC] = &nss_cc_mac2_rx_clk_src.clkr, 1873 [NSS_CC_MAC2_RX_DIV_CLK_SRC] = &nss_cc_mac2_rx_div_clk_src.clkr, 1874 [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC] = 1875 &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr, 1876 [NSS_CC_MAC2_SRDS1_CH1_TX_CLK] = &nss_cc_mac2_srds1_ch1_tx_clk.clkr, 1877 [NSS_CC_MAC2_RX_CLK] = &nss_cc_mac2_rx_clk.clkr, 1878 [NSS_CC_MAC2_GEPHY1_RX_CLK] = &nss_cc_mac2_gephy1_rx_clk.clkr, 1879 [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_tx_clk.clkr, 1880 [NSS_CC_MAC3_TX_CLK_SRC] = &nss_cc_mac3_tx_clk_src.clkr, 1881 [NSS_CC_MAC3_TX_DIV_CLK_SRC] = &nss_cc_mac3_tx_div_clk_src.clkr, 1882 [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC] = 1883 &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr, 1884 [NSS_CC_MAC3_SRDS1_CH2_RX_CLK] = &nss_cc_mac3_srds1_ch2_rx_clk.clkr, 1885 [NSS_CC_MAC3_TX_CLK] = &nss_cc_mac3_tx_clk.clkr, 1886 [NSS_CC_MAC3_GEPHY2_TX_CLK] = &nss_cc_mac3_gephy2_tx_clk.clkr, 1887 [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_rx_clk.clkr, 1888 [NSS_CC_MAC3_RX_CLK_SRC] = &nss_cc_mac3_rx_clk_src.clkr, 1889 [NSS_CC_MAC3_RX_DIV_CLK_SRC] = &nss_cc_mac3_rx_div_clk_src.clkr, 1890 [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC] = 1891 &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr, 1892 [NSS_CC_MAC3_SRDS1_CH2_TX_CLK] = &nss_cc_mac3_srds1_ch2_tx_clk.clkr, 1893 [NSS_CC_MAC3_RX_CLK] = &nss_cc_mac3_rx_clk.clkr, 1894 [NSS_CC_MAC3_GEPHY2_RX_CLK] = &nss_cc_mac3_gephy2_rx_clk.clkr, 1895 [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_tx_clk.clkr, 1896 [NSS_CC_MAC4_TX_CLK_SRC] = &nss_cc_mac4_tx_clk_src.clkr, 1897 [NSS_CC_MAC4_TX_DIV_CLK_SRC] = &nss_cc_mac4_tx_div_clk_src.clkr, 1898 [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC] = 1899 &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr, 1900 [NSS_CC_MAC4_SRDS1_CH3_RX_CLK] = &nss_cc_mac4_srds1_ch3_rx_clk.clkr, 1901 [NSS_CC_MAC4_TX_CLK] = &nss_cc_mac4_tx_clk.clkr, 1902 [NSS_CC_MAC4_GEPHY3_TX_CLK] = &nss_cc_mac4_gephy3_tx_clk.clkr, 1903 [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_rx_clk.clkr, 1904 [NSS_CC_MAC4_RX_CLK_SRC] = &nss_cc_mac4_rx_clk_src.clkr, 1905 [NSS_CC_MAC4_RX_DIV_CLK_SRC] = &nss_cc_mac4_rx_div_clk_src.clkr, 1906 [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC] = 1907 &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr, 1908 [NSS_CC_MAC4_SRDS1_CH3_TX_CLK] = &nss_cc_mac4_srds1_ch3_tx_clk.clkr, 1909 [NSS_CC_MAC4_RX_CLK] = &nss_cc_mac4_rx_clk.clkr, 1910 [NSS_CC_MAC4_GEPHY3_RX_CLK] = &nss_cc_mac4_gephy3_rx_clk.clkr, 1911 [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_tx_clk.clkr, 1912 [NSS_CC_MAC5_TX_CLK_SRC] = &nss_cc_mac5_tx_clk_src.clkr, 1913 [NSS_CC_MAC5_TX_DIV_CLK_SRC] = &nss_cc_mac5_tx_div_clk_src.clkr, 1914 [NSS_CC_MAC5_TX_SRDS0_CLK] = &nss_cc_mac5_tx_srds0_clk.clkr, 1915 [NSS_CC_MAC5_TX_CLK] = &nss_cc_mac5_tx_clk.clkr, 1916 [NSS_CC_MAC5_RX_CLK_SRC] = &nss_cc_mac5_rx_clk_src.clkr, 1917 [NSS_CC_MAC5_RX_DIV_CLK_SRC] = &nss_cc_mac5_rx_div_clk_src.clkr, 1918 [NSS_CC_MAC5_RX_SRDS0_CLK] = &nss_cc_mac5_rx_srds0_clk.clkr, 1919 [NSS_CC_MAC5_RX_CLK] = &nss_cc_mac5_rx_clk.clkr, 1920 [NSS_CC_MAC5_TX_SRDS0_CLK_SRC] = &nss_cc_mac5_tx_srds0_clk_src.clkr, 1921 [NSS_CC_MAC5_RX_SRDS0_CLK_SRC] = &nss_cc_mac5_rx_srds0_clk_src.clkr, 1922 [NSS_CC_AHB_CLK_SRC] = &nss_cc_ahb_clk_src.clkr, 1923 [NSS_CC_AHB_CLK] = &nss_cc_ahb_clk.clkr, 1924 [NSS_CC_SEC_CTRL_AHB_CLK] = &nss_cc_sec_ctrl_ahb_clk.clkr, 1925 [NSS_CC_TLMM_CLK] = &nss_cc_tlmm_clk.clkr, 1926 [NSS_CC_TLMM_AHB_CLK] = &nss_cc_tlmm_ahb_clk.clkr, 1927 [NSS_CC_CNOC_AHB_CLK] = &nss_cc_cnoc_ahb_clk.clkr, 1928 [NSS_CC_MDIO_AHB_CLK] = &nss_cc_mdio_ahb_clk.clkr, 1929 [NSS_CC_MDIO_MASTER_AHB_CLK] = &nss_cc_mdio_master_ahb_clk.clkr, 1930 [NSS_CC_SYS_CLK_SRC] = &nss_cc_sys_clk_src.clkr, 1931 [NSS_CC_SRDS0_SYS_CLK] = &nss_cc_srds0_sys_clk.clkr, 1932 [NSS_CC_SRDS1_SYS_CLK] = &nss_cc_srds1_sys_clk.clkr, 1933 [NSS_CC_GEPHY0_SYS_CLK] = &nss_cc_gephy0_sys_clk.clkr, 1934 [NSS_CC_GEPHY1_SYS_CLK] = &nss_cc_gephy1_sys_clk.clkr, 1935 [NSS_CC_GEPHY2_SYS_CLK] = &nss_cc_gephy2_sys_clk.clkr, 1936 [NSS_CC_GEPHY3_SYS_CLK] = &nss_cc_gephy3_sys_clk.clkr, 1937 }; 1938 1939 static const struct qcom_reset_map nss_cc_qca8k_resets[] = { 1940 [NSS_CC_SWITCH_CORE_ARES] = { 0xc, 2 }, 1941 [NSS_CC_APB_BRIDGE_ARES] = { 0x10, 2 }, 1942 [NSS_CC_MAC0_TX_ARES] = { 0x20, 2 }, 1943 [NSS_CC_MAC0_TX_SRDS1_ARES] = { 0x24, 2 }, 1944 [NSS_CC_MAC0_RX_ARES] = { 0x34, 2 }, 1945 [NSS_CC_MAC0_RX_SRDS1_ARES] = { 0x3c, 2 }, 1946 [NSS_CC_MAC1_SRDS1_CH0_RX_ARES] = { 0x50, 2 }, 1947 [NSS_CC_MAC1_TX_ARES] = { 0x54, 2 }, 1948 [NSS_CC_MAC1_GEPHY0_TX_ARES] = { 0x58, 2 }, 1949 [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES] = { 0x5c, 2 }, 1950 [NSS_CC_MAC1_SRDS1_CH0_TX_ARES] = { 0x70, 2 }, 1951 [NSS_CC_MAC1_RX_ARES] = { 0x74, 2 }, 1952 [NSS_CC_MAC1_GEPHY0_RX_ARES] = { 0x78, 2 }, 1953 [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES] = { 0x7c, 2 }, 1954 [NSS_CC_MAC2_SRDS1_CH1_RX_ARES] = { 0x90, 2 }, 1955 [NSS_CC_MAC2_TX_ARES] = { 0x94, 2 }, 1956 [NSS_CC_MAC2_GEPHY1_TX_ARES] = { 0x98, 2 }, 1957 [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES] = { 0x9c, 2 }, 1958 [NSS_CC_MAC2_SRDS1_CH1_TX_ARES] = { 0xb0, 2 }, 1959 [NSS_CC_MAC2_RX_ARES] = { 0xb4, 2 }, 1960 [NSS_CC_MAC2_GEPHY1_RX_ARES] = { 0xb8, 2 }, 1961 [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES] = { 0xbc, 2 }, 1962 [NSS_CC_MAC3_SRDS1_CH2_RX_ARES] = { 0xd0, 2 }, 1963 [NSS_CC_MAC3_TX_ARES] = { 0xd4, 2 }, 1964 [NSS_CC_MAC3_GEPHY2_TX_ARES] = { 0xd8, 2 }, 1965 [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES] = { 0xdc, 2 }, 1966 [NSS_CC_MAC3_SRDS1_CH2_TX_ARES] = { 0xf0, 2 }, 1967 [NSS_CC_MAC3_RX_ARES] = { 0xf4, 2 }, 1968 [NSS_CC_MAC3_GEPHY2_RX_ARES] = { 0xf8, 2 }, 1969 [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES] = { 0xfc, 2 }, 1970 [NSS_CC_MAC4_SRDS1_CH3_RX_ARES] = { 0x110, 2 }, 1971 [NSS_CC_MAC4_TX_ARES] = { 0x114, 2 }, 1972 [NSS_CC_MAC4_GEPHY3_TX_ARES] = { 0x118, 2 }, 1973 [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES] = { 0x11c, 2 }, 1974 [NSS_CC_MAC4_SRDS1_CH3_TX_ARES] = { 0x130, 2 }, 1975 [NSS_CC_MAC4_RX_ARES] = { 0x134, 2 }, 1976 [NSS_CC_MAC4_GEPHY3_RX_ARES] = { 0x138, 2 }, 1977 [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES] = { 0x13c, 2 }, 1978 [NSS_CC_MAC5_TX_ARES] = { 0x14c, 2 }, 1979 [NSS_CC_MAC5_TX_SRDS0_ARES] = { 0x150, 2 }, 1980 [NSS_CC_MAC5_RX_ARES] = { 0x160, 2 }, 1981 [NSS_CC_MAC5_RX_SRDS0_ARES] = { 0x164, 2 }, 1982 [NSS_CC_AHB_ARES] = { 0x170, 2 }, 1983 [NSS_CC_SEC_CTRL_AHB_ARES] = { 0x174, 2 }, 1984 [NSS_CC_TLMM_ARES] = { 0x178, 2 }, 1985 [NSS_CC_TLMM_AHB_ARES] = { 0x190, 2 }, 1986 [NSS_CC_CNOC_AHB_ARES] = { 0x194, 2 }, /* reset CNOC AHB & APB */ 1987 [NSS_CC_MDIO_AHB_ARES] = { 0x198, 2 }, 1988 [NSS_CC_MDIO_MASTER_AHB_ARES] = { 0x19c, 2 }, 1989 [NSS_CC_SRDS0_SYS_ARES] = { 0x1a8, 2 }, 1990 [NSS_CC_SRDS1_SYS_ARES] = { 0x1ac, 2 }, 1991 [NSS_CC_GEPHY0_SYS_ARES] = { 0x1b0, 2 }, 1992 [NSS_CC_GEPHY1_SYS_ARES] = { 0x1b4, 2 }, 1993 [NSS_CC_GEPHY2_SYS_ARES] = { 0x1b8, 2 }, 1994 [NSS_CC_GEPHY3_SYS_ARES] = { 0x1bc, 2 }, 1995 [NSS_CC_SEC_CTRL_ARES] = { 0x1c8, 2 }, 1996 [NSS_CC_SEC_CTRL_SENSE_ARES] = { 0x1d0, 2 }, 1997 [NSS_CC_SLEEP_ARES] = { 0x1e0, 2 }, 1998 [NSS_CC_DEBUG_ARES] = { 0x1e8, 2 }, 1999 [NSS_CC_GEPHY0_ARES] = { 0x304, 0 }, 2000 [NSS_CC_GEPHY1_ARES] = { 0x304, 1 }, 2001 [NSS_CC_GEPHY2_ARES] = { 0x304, 2 }, 2002 [NSS_CC_GEPHY3_ARES] = { 0x304, 3 }, 2003 [NSS_CC_DSP_ARES] = { 0x304, 4 }, 2004 [NSS_CC_GEPHY_FULL_ARES] = { .reg = 0x304, .bitmask = GENMASK(4, 0) }, 2005 [NSS_CC_GLOBAL_ARES] = { 0x308, 0 }, 2006 [NSS_CC_XPCS_ARES] = { 0x30c, 0 }, 2007 }; 2008 2009 /* For each read/write operation of clock register, there are three MDIO frames 2010 * sent to the device. 2011 * 2012 * 1. The high address part[23:8] of register is packaged into the first MDIO frame 2013 * for selecting page. 2014 * 2. The low address part[7:0] of register is packaged into the second MDIO frame 2015 * with the low 16bit data to read/write. 2016 * 3. The low address part[7:0] of register is packaged into the last MDIO frame 2017 * with the high 16bit data to read/write. 2018 * 2019 * The clause22 MDIO frame format used by device is as below. 2020 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2021 * | ST| OP| ADDR | REG | TA| DATA | 2022 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2023 */ 2024 static inline void convert_reg_to_mii_addr(u32 regaddr, u16 *reg, u16 *phy_addr, u16 *page) 2025 { 2026 *reg = FIELD_GET(QCA8K_CLK_REG_MASK, regaddr); 2027 *phy_addr = FIELD_GET(QCA8K_CLK_PHY_ADDR_MASK, regaddr) | QCA8K_LOW_ADDR_PREFIX; 2028 *page = FIELD_GET(QCA8K_CLK_PAGE_MASK, regaddr); 2029 } 2030 2031 static int qca8k_mii_read(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 *val) 2032 { 2033 int ret, data; 2034 2035 ret = __mdiobus_read(bus, switch_phy_id, reg); 2036 if (ret >= 0) { 2037 data = ret; 2038 2039 ret = __mdiobus_read(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS)); 2040 if (ret >= 0) 2041 *val = data | ret << 16; 2042 } 2043 2044 if (ret < 0) 2045 dev_err_ratelimited(&bus->dev, "fail to read qca8k mii register\n"); 2046 2047 return ret < 0 ? ret : 0; 2048 } 2049 2050 static void qca8k_mii_write(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 val) 2051 { 2052 int ret; 2053 2054 ret = __mdiobus_write(bus, switch_phy_id, reg, lower_16_bits(val)); 2055 if (ret >= 0) 2056 ret = __mdiobus_write(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS), 2057 upper_16_bits(val)); 2058 2059 if (ret < 0) 2060 dev_err_ratelimited(&bus->dev, "fail to write qca8k mii register\n"); 2061 } 2062 2063 static int qca8k_mii_page_set(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u16 page) 2064 { 2065 int ret; 2066 2067 ret = __mdiobus_write(bus, switch_phy_id, reg, page); 2068 if (ret < 0) 2069 dev_err_ratelimited(&bus->dev, "fail to set page\n"); 2070 2071 return ret; 2072 } 2073 2074 static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val) 2075 { 2076 struct mii_bus *bus = context; 2077 u16 reg, phy_addr, page; 2078 int ret; 2079 2080 regaddr += QCA8K_CLK_REG_BASE; 2081 convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); 2082 2083 mutex_lock(&bus->mdio_lock); 2084 ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); 2085 if (ret < 0) 2086 goto qca8k_read_exit; 2087 2088 ret = qca8k_mii_read(bus, phy_addr, reg, val); 2089 2090 qca8k_read_exit: 2091 mutex_unlock(&bus->mdio_lock); 2092 return ret; 2093 }; 2094 2095 static int qca8k_regmap_write(void *context, unsigned int regaddr, unsigned int val) 2096 { 2097 struct mii_bus *bus = context; 2098 u16 reg, phy_addr, page; 2099 int ret; 2100 2101 regaddr += QCA8K_CLK_REG_BASE; 2102 convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); 2103 2104 mutex_lock(&bus->mdio_lock); 2105 ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); 2106 if (ret < 0) 2107 goto qca8k_write_exit; 2108 2109 qca8k_mii_write(bus, phy_addr, reg, val); 2110 2111 qca8k_write_exit: 2112 mutex_unlock(&bus->mdio_lock); 2113 return ret; 2114 }; 2115 2116 static int qca8k_regmap_update_bits(void *context, unsigned int regaddr, 2117 unsigned int mask, unsigned int value) 2118 { 2119 struct mii_bus *bus = context; 2120 u16 reg, phy_addr, page; 2121 int ret; 2122 u32 val; 2123 2124 regaddr += QCA8K_CLK_REG_BASE; 2125 convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); 2126 2127 mutex_lock(&bus->mdio_lock); 2128 ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); 2129 if (ret < 0) 2130 goto qca8k_update_exit; 2131 2132 ret = qca8k_mii_read(bus, phy_addr, reg, &val); 2133 if (ret < 0) 2134 goto qca8k_update_exit; 2135 2136 val &= ~mask; 2137 val |= value; 2138 qca8k_mii_write(bus, phy_addr, reg, val); 2139 2140 qca8k_update_exit: 2141 mutex_unlock(&bus->mdio_lock); 2142 return ret; 2143 } 2144 2145 static const struct regmap_config nss_cc_qca8k_regmap_config = { 2146 .reg_bits = 12, 2147 .reg_stride = 4, 2148 .val_bits = 32, 2149 .max_register = 0x30c, 2150 .reg_read = qca8k_regmap_read, 2151 .reg_write = qca8k_regmap_write, 2152 .reg_update_bits = qca8k_regmap_update_bits, 2153 .disable_locking = true, 2154 }; 2155 2156 static const struct qcom_cc_desc nss_cc_qca8k_desc = { 2157 .config = &nss_cc_qca8k_regmap_config, 2158 .clks = nss_cc_qca8k_clocks, 2159 .num_clks = ARRAY_SIZE(nss_cc_qca8k_clocks), 2160 .resets = nss_cc_qca8k_resets, 2161 .num_resets = ARRAY_SIZE(nss_cc_qca8k_resets), 2162 }; 2163 2164 /* 2165 * The reference clock of QCA8k NSSCC needs to be enabled to make sure 2166 * the GPIO reset taking effect. 2167 */ 2168 static int nss_cc_qca8k_clock_enable_and_reset(struct device *dev) 2169 { 2170 struct gpio_desc *gpiod; 2171 struct clk *clk; 2172 2173 clk = devm_clk_get_enabled(dev, NULL); 2174 if (IS_ERR(clk)) 2175 return PTR_ERR(clk); 2176 2177 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 2178 if (IS_ERR(gpiod)) { 2179 return PTR_ERR(gpiod); 2180 } else if (gpiod) { 2181 msleep(100); 2182 gpiod_set_value_cansleep(gpiod, 0); 2183 } 2184 2185 return 0; 2186 } 2187 2188 static int nss_cc_qca8k_probe(struct mdio_device *mdiodev) 2189 { 2190 struct regmap *regmap; 2191 int ret; 2192 2193 ret = nss_cc_qca8k_clock_enable_and_reset(&mdiodev->dev); 2194 if (ret) 2195 return dev_err_probe(&mdiodev->dev, ret, "Fail to reset NSSCC\n"); 2196 2197 regmap = devm_regmap_init(&mdiodev->dev, NULL, mdiodev->bus, nss_cc_qca8k_desc.config); 2198 if (IS_ERR(regmap)) 2199 return dev_err_probe(&mdiodev->dev, PTR_ERR(regmap), "Failed to init regmap\n"); 2200 2201 return qcom_cc_really_probe(&mdiodev->dev, &nss_cc_qca8k_desc, regmap); 2202 } 2203 2204 static const struct of_device_id nss_cc_qca8k_match_table[] = { 2205 { .compatible = "qcom,qca8084-nsscc" }, 2206 { } 2207 }; 2208 MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table); 2209 2210 static struct mdio_driver nss_cc_qca8k_driver = { 2211 .mdiodrv.driver = { 2212 .name = "qcom,qca8k-nsscc", 2213 .of_match_table = nss_cc_qca8k_match_table, 2214 }, 2215 .probe = nss_cc_qca8k_probe, 2216 }; 2217 2218 mdio_module_driver(nss_cc_qca8k_driver); 2219 2220 MODULE_DESCRIPTION("QCOM NSS_CC QCA8K Driver"); 2221 MODULE_LICENSE("GPL"); 2222