1 /*x 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 #include <linux/clk.h> 25 26 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-regmap-divider.h" 31 #include "clk-alpha-pll.h" 32 #include "clk-rcg.h" 33 #include "clk-branch.h" 34 #include "reset.h" 35 36 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 37 38 enum { 39 P_XO, 40 P_MMPLL0, 41 P_GPLL0, 42 P_GPLL0_DIV, 43 P_MMPLL1, 44 P_MMPLL9, 45 P_MMPLL2, 46 P_MMPLL8, 47 P_MMPLL3, 48 P_DSI0PLL, 49 P_DSI1PLL, 50 P_MMPLL5, 51 P_HDMIPLL, 52 P_DSI0PLL_BYTE, 53 P_DSI1PLL_BYTE, 54 P_MMPLL4, 55 }; 56 57 static const struct parent_map mmss_xo_hdmi_map[] = { 58 { P_XO, 0 }, 59 { P_HDMIPLL, 1 } 60 }; 61 62 static const char * const mmss_xo_hdmi[] = { 63 "xo", 64 "hdmipll" 65 }; 66 67 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 68 { P_XO, 0 }, 69 { P_DSI0PLL, 1 }, 70 { P_DSI1PLL, 2 } 71 }; 72 73 static const char * const mmss_xo_dsi0pll_dsi1pll[] = { 74 "xo", 75 "dsi0pll", 76 "dsi1pll" 77 }; 78 79 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 80 { P_XO, 0 }, 81 { P_GPLL0, 5 }, 82 { P_GPLL0_DIV, 6 } 83 }; 84 85 static const char * const mmss_xo_gpll0_gpll0_div[] = { 86 "xo", 87 "gpll0", 88 "gpll0_div" 89 }; 90 91 static const struct parent_map mmss_xo_dsibyte_map[] = { 92 { P_XO, 0 }, 93 { P_DSI0PLL_BYTE, 1 }, 94 { P_DSI1PLL_BYTE, 2 } 95 }; 96 97 static const char * const mmss_xo_dsibyte[] = { 98 "xo", 99 "dsi0pllbyte", 100 "dsi1pllbyte" 101 }; 102 103 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 104 { P_XO, 0 }, 105 { P_MMPLL0, 1 }, 106 { P_GPLL0, 5 }, 107 { P_GPLL0_DIV, 6 } 108 }; 109 110 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { 111 "xo", 112 "mmpll0", 113 "gpll0", 114 "gpll0_div" 115 }; 116 117 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 118 { P_XO, 0 }, 119 { P_MMPLL0, 1 }, 120 { P_MMPLL1, 2 }, 121 { P_GPLL0, 5 }, 122 { P_GPLL0_DIV, 6 } 123 }; 124 125 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 126 "xo", 127 "mmpll0", 128 "mmpll1", 129 "gpll0", 130 "gpll0_div" 131 }; 132 133 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { 134 { P_XO, 0 }, 135 { P_MMPLL0, 1 }, 136 { P_MMPLL3, 3 }, 137 { P_GPLL0, 5 }, 138 { P_GPLL0_DIV, 6 } 139 }; 140 141 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { 142 "xo", 143 "mmpll0", 144 "mmpll3", 145 "gpll0", 146 "gpll0_div" 147 }; 148 149 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 150 { P_XO, 0 }, 151 { P_MMPLL0, 1 }, 152 { P_MMPLL5, 2 }, 153 { P_GPLL0, 5 }, 154 { P_GPLL0_DIV, 6 } 155 }; 156 157 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 158 "xo", 159 "mmpll0", 160 "mmpll5", 161 "gpll0", 162 "gpll0_div" 163 }; 164 165 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { 166 { P_XO, 0 }, 167 { P_MMPLL0, 1 }, 168 { P_MMPLL4, 3 }, 169 { P_GPLL0, 5 }, 170 { P_GPLL0_DIV, 6 } 171 }; 172 173 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { 174 "xo", 175 "mmpll0", 176 "mmpll4", 177 "gpll0", 178 "gpll0_div" 179 }; 180 181 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { 182 { P_XO, 0 }, 183 { P_MMPLL0, 1 }, 184 { P_MMPLL9, 2 }, 185 { P_MMPLL2, 3 }, 186 { P_MMPLL8, 4 }, 187 { P_GPLL0, 5 } 188 }; 189 190 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { 191 "xo", 192 "mmpll0", 193 "mmpll9", 194 "mmpll2", 195 "mmpll8", 196 "gpll0" 197 }; 198 199 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { 200 { P_XO, 0 }, 201 { P_MMPLL0, 1 }, 202 { P_MMPLL9, 2 }, 203 { P_MMPLL2, 3 }, 204 { P_MMPLL8, 4 }, 205 { P_GPLL0, 5 }, 206 { P_GPLL0_DIV, 6 } 207 }; 208 209 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { 210 "xo", 211 "mmpll0", 212 "mmpll9", 213 "mmpll2", 214 "mmpll8", 215 "gpll0", 216 "gpll0_div" 217 }; 218 219 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { 220 { P_XO, 0 }, 221 { P_MMPLL0, 1 }, 222 { P_MMPLL1, 2 }, 223 { P_MMPLL4, 3 }, 224 { P_MMPLL3, 4 }, 225 { P_GPLL0, 5 }, 226 { P_GPLL0_DIV, 6 } 227 }; 228 229 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { 230 "xo", 231 "mmpll0", 232 "mmpll1", 233 "mmpll4", 234 "mmpll3", 235 "gpll0", 236 "gpll0_div" 237 }; 238 239 static struct clk_fixed_factor gpll0_div = { 240 .mult = 1, 241 .div = 2, 242 .hw.init = &(struct clk_init_data){ 243 .name = "gpll0_div", 244 .parent_names = (const char *[]){ "gpll0" }, 245 .num_parents = 1, 246 .ops = &clk_fixed_factor_ops, 247 }, 248 }; 249 250 static struct pll_vco mmpll_p_vco[] = { 251 { 250000000, 500000000, 3 }, 252 { 500000000, 1000000000, 2 }, 253 { 1000000000, 1500000000, 1 }, 254 { 1500000000, 2000000000, 0 }, 255 }; 256 257 static struct pll_vco mmpll_gfx_vco[] = { 258 { 400000000, 1000000000, 2 }, 259 { 1000000000, 1500000000, 1 }, 260 { 1500000000, 2000000000, 0 }, 261 }; 262 263 static struct pll_vco mmpll_t_vco[] = { 264 { 500000000, 1500000000, 0 }, 265 }; 266 267 static struct clk_alpha_pll mmpll0_early = { 268 .offset = 0x0, 269 .vco_table = mmpll_p_vco, 270 .num_vco = ARRAY_SIZE(mmpll_p_vco), 271 .clkr = { 272 .enable_reg = 0x100, 273 .enable_mask = BIT(0), 274 .hw.init = &(struct clk_init_data){ 275 .name = "mmpll0_early", 276 .parent_names = (const char *[]){ "xo" }, 277 .num_parents = 1, 278 .ops = &clk_alpha_pll_ops, 279 }, 280 }, 281 }; 282 283 static struct clk_alpha_pll_postdiv mmpll0 = { 284 .offset = 0x0, 285 .width = 4, 286 .clkr.hw.init = &(struct clk_init_data){ 287 .name = "mmpll0", 288 .parent_names = (const char *[]){ "mmpll0_early" }, 289 .num_parents = 1, 290 .ops = &clk_alpha_pll_postdiv_ops, 291 .flags = CLK_SET_RATE_PARENT, 292 }, 293 }; 294 295 static struct clk_alpha_pll mmpll1_early = { 296 .offset = 0x30, 297 .vco_table = mmpll_p_vco, 298 .num_vco = ARRAY_SIZE(mmpll_p_vco), 299 .clkr = { 300 .enable_reg = 0x100, 301 .enable_mask = BIT(1), 302 .hw.init = &(struct clk_init_data){ 303 .name = "mmpll1_early", 304 .parent_names = (const char *[]){ "xo" }, 305 .num_parents = 1, 306 .ops = &clk_alpha_pll_ops, 307 } 308 }, 309 }; 310 311 static struct clk_alpha_pll_postdiv mmpll1 = { 312 .offset = 0x30, 313 .width = 4, 314 .clkr.hw.init = &(struct clk_init_data){ 315 .name = "mmpll1", 316 .parent_names = (const char *[]){ "mmpll1_early" }, 317 .num_parents = 1, 318 .ops = &clk_alpha_pll_postdiv_ops, 319 .flags = CLK_SET_RATE_PARENT, 320 }, 321 }; 322 323 static struct clk_alpha_pll mmpll2_early = { 324 .offset = 0x4100, 325 .vco_table = mmpll_gfx_vco, 326 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 327 .clkr.hw.init = &(struct clk_init_data){ 328 .name = "mmpll2_early", 329 .parent_names = (const char *[]){ "xo" }, 330 .num_parents = 1, 331 .ops = &clk_alpha_pll_ops, 332 }, 333 }; 334 335 static struct clk_alpha_pll_postdiv mmpll2 = { 336 .offset = 0x4100, 337 .width = 4, 338 .clkr.hw.init = &(struct clk_init_data){ 339 .name = "mmpll2", 340 .parent_names = (const char *[]){ "mmpll2_early" }, 341 .num_parents = 1, 342 .ops = &clk_alpha_pll_postdiv_ops, 343 .flags = CLK_SET_RATE_PARENT, 344 }, 345 }; 346 347 static struct clk_alpha_pll mmpll3_early = { 348 .offset = 0x60, 349 .vco_table = mmpll_p_vco, 350 .num_vco = ARRAY_SIZE(mmpll_p_vco), 351 .clkr.hw.init = &(struct clk_init_data){ 352 .name = "mmpll3_early", 353 .parent_names = (const char *[]){ "xo" }, 354 .num_parents = 1, 355 .ops = &clk_alpha_pll_ops, 356 }, 357 }; 358 359 static struct clk_alpha_pll_postdiv mmpll3 = { 360 .offset = 0x60, 361 .width = 4, 362 .clkr.hw.init = &(struct clk_init_data){ 363 .name = "mmpll3", 364 .parent_names = (const char *[]){ "mmpll3_early" }, 365 .num_parents = 1, 366 .ops = &clk_alpha_pll_postdiv_ops, 367 .flags = CLK_SET_RATE_PARENT, 368 }, 369 }; 370 371 static struct clk_alpha_pll mmpll4_early = { 372 .offset = 0x90, 373 .vco_table = mmpll_t_vco, 374 .num_vco = ARRAY_SIZE(mmpll_t_vco), 375 .clkr.hw.init = &(struct clk_init_data){ 376 .name = "mmpll4_early", 377 .parent_names = (const char *[]){ "xo" }, 378 .num_parents = 1, 379 .ops = &clk_alpha_pll_ops, 380 }, 381 }; 382 383 static struct clk_alpha_pll_postdiv mmpll4 = { 384 .offset = 0x90, 385 .width = 2, 386 .clkr.hw.init = &(struct clk_init_data){ 387 .name = "mmpll4", 388 .parent_names = (const char *[]){ "mmpll4_early" }, 389 .num_parents = 1, 390 .ops = &clk_alpha_pll_postdiv_ops, 391 .flags = CLK_SET_RATE_PARENT, 392 }, 393 }; 394 395 static struct clk_alpha_pll mmpll5_early = { 396 .offset = 0xc0, 397 .vco_table = mmpll_p_vco, 398 .num_vco = ARRAY_SIZE(mmpll_p_vco), 399 .clkr.hw.init = &(struct clk_init_data){ 400 .name = "mmpll5_early", 401 .parent_names = (const char *[]){ "xo" }, 402 .num_parents = 1, 403 .ops = &clk_alpha_pll_ops, 404 }, 405 }; 406 407 static struct clk_alpha_pll_postdiv mmpll5 = { 408 .offset = 0xc0, 409 .width = 4, 410 .clkr.hw.init = &(struct clk_init_data){ 411 .name = "mmpll5", 412 .parent_names = (const char *[]){ "mmpll5_early" }, 413 .num_parents = 1, 414 .ops = &clk_alpha_pll_postdiv_ops, 415 .flags = CLK_SET_RATE_PARENT, 416 }, 417 }; 418 419 static struct clk_alpha_pll mmpll8_early = { 420 .offset = 0x4130, 421 .vco_table = mmpll_gfx_vco, 422 .num_vco = ARRAY_SIZE(mmpll_gfx_vco), 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "mmpll8_early", 425 .parent_names = (const char *[]){ "xo" }, 426 .num_parents = 1, 427 .ops = &clk_alpha_pll_ops, 428 }, 429 }; 430 431 static struct clk_alpha_pll_postdiv mmpll8 = { 432 .offset = 0x4130, 433 .width = 4, 434 .clkr.hw.init = &(struct clk_init_data){ 435 .name = "mmpll8", 436 .parent_names = (const char *[]){ "mmpll8_early" }, 437 .num_parents = 1, 438 .ops = &clk_alpha_pll_postdiv_ops, 439 .flags = CLK_SET_RATE_PARENT, 440 }, 441 }; 442 443 static struct clk_alpha_pll mmpll9_early = { 444 .offset = 0x4200, 445 .vco_table = mmpll_t_vco, 446 .num_vco = ARRAY_SIZE(mmpll_t_vco), 447 .clkr.hw.init = &(struct clk_init_data){ 448 .name = "mmpll9_early", 449 .parent_names = (const char *[]){ "xo" }, 450 .num_parents = 1, 451 .ops = &clk_alpha_pll_ops, 452 }, 453 }; 454 455 static struct clk_alpha_pll_postdiv mmpll9 = { 456 .offset = 0x4200, 457 .width = 2, 458 .clkr.hw.init = &(struct clk_init_data){ 459 .name = "mmpll9", 460 .parent_names = (const char *[]){ "mmpll9_early" }, 461 .num_parents = 1, 462 .ops = &clk_alpha_pll_postdiv_ops, 463 .flags = CLK_SET_RATE_PARENT, 464 }, 465 }; 466 467 static const struct freq_tbl ftbl_ahb_clk_src[] = { 468 F(19200000, P_XO, 1, 0, 0), 469 F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 470 F(80000000, P_MMPLL0, 10, 0, 0), 471 { } 472 }; 473 474 static struct clk_rcg2 ahb_clk_src = { 475 .cmd_rcgr = 0x5000, 476 .hid_width = 5, 477 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 478 .freq_tbl = ftbl_ahb_clk_src, 479 .clkr.hw.init = &(struct clk_init_data){ 480 .name = "ahb_clk_src", 481 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 482 .num_parents = 4, 483 .ops = &clk_rcg2_ops, 484 }, 485 }; 486 487 static const struct freq_tbl ftbl_axi_clk_src[] = { 488 F(19200000, P_XO, 1, 0, 0), 489 F(75000000, P_GPLL0_DIV, 4, 0, 0), 490 F(100000000, P_GPLL0, 6, 0, 0), 491 F(171430000, P_GPLL0, 3.5, 0, 0), 492 F(200000000, P_GPLL0, 3, 0, 0), 493 F(320000000, P_MMPLL0, 2.5, 0, 0), 494 F(400000000, P_MMPLL0, 2, 0, 0), 495 { } 496 }; 497 498 static struct clk_rcg2 axi_clk_src = { 499 .cmd_rcgr = 0x5040, 500 .hid_width = 5, 501 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 502 .freq_tbl = ftbl_axi_clk_src, 503 .clkr.hw.init = &(struct clk_init_data){ 504 .name = "axi_clk_src", 505 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 506 .num_parents = 5, 507 .ops = &clk_rcg2_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 maxi_clk_src = { 512 .cmd_rcgr = 0x5090, 513 .hid_width = 5, 514 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 515 .freq_tbl = ftbl_axi_clk_src, 516 .clkr.hw.init = &(struct clk_init_data){ 517 .name = "maxi_clk_src", 518 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 519 .num_parents = 5, 520 .ops = &clk_rcg2_ops, 521 }, 522 }; 523 524 static struct clk_rcg2 gfx3d_clk_src = { 525 .cmd_rcgr = 0x4000, 526 .hid_width = 5, 527 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, 528 .clkr.hw.init = &(struct clk_init_data){ 529 .name = "gfx3d_clk_src", 530 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, 531 .num_parents = 6, 532 .ops = &clk_gfx3d_ops, 533 .flags = CLK_SET_RATE_PARENT, 534 }, 535 }; 536 537 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 538 F(19200000, P_XO, 1, 0, 0), 539 { } 540 }; 541 542 static struct clk_rcg2 rbbmtimer_clk_src = { 543 .cmd_rcgr = 0x4090, 544 .hid_width = 5, 545 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 546 .freq_tbl = ftbl_rbbmtimer_clk_src, 547 .clkr.hw.init = &(struct clk_init_data){ 548 .name = "rbbmtimer_clk_src", 549 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 550 .num_parents = 4, 551 .ops = &clk_rcg2_ops, 552 }, 553 }; 554 555 static struct clk_rcg2 isense_clk_src = { 556 .cmd_rcgr = 0x4010, 557 .hid_width = 5, 558 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "isense_clk_src", 561 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, 562 .num_parents = 7, 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 568 F(19200000, P_XO, 1, 0, 0), 569 F(50000000, P_GPLL0, 12, 0, 0), 570 { } 571 }; 572 573 static struct clk_rcg2 rbcpr_clk_src = { 574 .cmd_rcgr = 0x4060, 575 .hid_width = 5, 576 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 577 .freq_tbl = ftbl_rbcpr_clk_src, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "rbcpr_clk_src", 580 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, 581 .num_parents = 4, 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static const struct freq_tbl ftbl_video_core_clk_src[] = { 587 F(75000000, P_GPLL0_DIV, 4, 0, 0), 588 F(150000000, P_GPLL0, 4, 0, 0), 589 F(346666667, P_MMPLL3, 3, 0, 0), 590 F(520000000, P_MMPLL3, 2, 0, 0), 591 { } 592 }; 593 594 static struct clk_rcg2 video_core_clk_src = { 595 .cmd_rcgr = 0x1000, 596 .mnd_width = 8, 597 .hid_width = 5, 598 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 599 .freq_tbl = ftbl_video_core_clk_src, 600 .clkr.hw.init = &(struct clk_init_data){ 601 .name = "video_core_clk_src", 602 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 603 .num_parents = 5, 604 .ops = &clk_rcg2_ops, 605 }, 606 }; 607 608 static struct clk_rcg2 video_subcore0_clk_src = { 609 .cmd_rcgr = 0x1060, 610 .mnd_width = 8, 611 .hid_width = 5, 612 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 613 .freq_tbl = ftbl_video_core_clk_src, 614 .clkr.hw.init = &(struct clk_init_data){ 615 .name = "video_subcore0_clk_src", 616 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 617 .num_parents = 5, 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 video_subcore1_clk_src = { 623 .cmd_rcgr = 0x1080, 624 .mnd_width = 8, 625 .hid_width = 5, 626 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map, 627 .freq_tbl = ftbl_video_core_clk_src, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "video_subcore1_clk_src", 630 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, 631 .num_parents = 5, 632 .ops = &clk_rcg2_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 pclk0_clk_src = { 637 .cmd_rcgr = 0x2000, 638 .mnd_width = 8, 639 .hid_width = 5, 640 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "pclk0_clk_src", 643 .parent_names = mmss_xo_dsi0pll_dsi1pll, 644 .num_parents = 3, 645 .ops = &clk_pixel_ops, 646 .flags = CLK_SET_RATE_PARENT, 647 }, 648 }; 649 650 static struct clk_rcg2 pclk1_clk_src = { 651 .cmd_rcgr = 0x2020, 652 .mnd_width = 8, 653 .hid_width = 5, 654 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 655 .clkr.hw.init = &(struct clk_init_data){ 656 .name = "pclk1_clk_src", 657 .parent_names = mmss_xo_dsi0pll_dsi1pll, 658 .num_parents = 3, 659 .ops = &clk_pixel_ops, 660 .flags = CLK_SET_RATE_PARENT, 661 }, 662 }; 663 664 static const struct freq_tbl ftbl_mdp_clk_src[] = { 665 F(85714286, P_GPLL0, 7, 0, 0), 666 F(100000000, P_GPLL0, 6, 0, 0), 667 F(150000000, P_GPLL0, 4, 0, 0), 668 F(171428571, P_GPLL0, 3.5, 0, 0), 669 F(200000000, P_GPLL0, 3, 0, 0), 670 F(275000000, P_MMPLL5, 3, 0, 0), 671 F(300000000, P_GPLL0, 2, 0, 0), 672 F(330000000, P_MMPLL5, 2.5, 0, 0), 673 F(412500000, P_MMPLL5, 2, 0, 0), 674 { } 675 }; 676 677 static struct clk_rcg2 mdp_clk_src = { 678 .cmd_rcgr = 0x2040, 679 .hid_width = 5, 680 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 681 .freq_tbl = ftbl_mdp_clk_src, 682 .clkr.hw.init = &(struct clk_init_data){ 683 .name = "mdp_clk_src", 684 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 685 .num_parents = 5, 686 .ops = &clk_rcg2_ops, 687 }, 688 }; 689 690 static struct freq_tbl extpclk_freq_tbl[] = { 691 { .src = P_HDMIPLL }, 692 { } 693 }; 694 695 static struct clk_rcg2 extpclk_clk_src = { 696 .cmd_rcgr = 0x2060, 697 .hid_width = 5, 698 .parent_map = mmss_xo_hdmi_map, 699 .freq_tbl = extpclk_freq_tbl, 700 .clkr.hw.init = &(struct clk_init_data){ 701 .name = "extpclk_clk_src", 702 .parent_names = mmss_xo_hdmi, 703 .num_parents = 2, 704 .ops = &clk_byte_ops, 705 .flags = CLK_SET_RATE_PARENT, 706 }, 707 }; 708 709 static struct freq_tbl ftbl_mdss_vsync_clk[] = { 710 F(19200000, P_XO, 1, 0, 0), 711 { } 712 }; 713 714 static struct clk_rcg2 vsync_clk_src = { 715 .cmd_rcgr = 0x2080, 716 .hid_width = 5, 717 .parent_map = mmss_xo_gpll0_gpll0_div_map, 718 .freq_tbl = ftbl_mdss_vsync_clk, 719 .clkr.hw.init = &(struct clk_init_data){ 720 .name = "vsync_clk_src", 721 .parent_names = mmss_xo_gpll0_gpll0_div, 722 .num_parents = 3, 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct freq_tbl ftbl_mdss_hdmi_clk[] = { 728 F(19200000, P_XO, 1, 0, 0), 729 { } 730 }; 731 732 static struct clk_rcg2 hdmi_clk_src = { 733 .cmd_rcgr = 0x2100, 734 .hid_width = 5, 735 .parent_map = mmss_xo_gpll0_gpll0_div_map, 736 .freq_tbl = ftbl_mdss_hdmi_clk, 737 .clkr.hw.init = &(struct clk_init_data){ 738 .name = "hdmi_clk_src", 739 .parent_names = mmss_xo_gpll0_gpll0_div, 740 .num_parents = 3, 741 .ops = &clk_rcg2_ops, 742 }, 743 }; 744 745 static struct clk_rcg2 byte0_clk_src = { 746 .cmd_rcgr = 0x2120, 747 .hid_width = 5, 748 .parent_map = mmss_xo_dsibyte_map, 749 .clkr.hw.init = &(struct clk_init_data){ 750 .name = "byte0_clk_src", 751 .parent_names = mmss_xo_dsibyte, 752 .num_parents = 3, 753 .ops = &clk_byte2_ops, 754 .flags = CLK_SET_RATE_PARENT, 755 }, 756 }; 757 758 static struct clk_rcg2 byte1_clk_src = { 759 .cmd_rcgr = 0x2140, 760 .hid_width = 5, 761 .parent_map = mmss_xo_dsibyte_map, 762 .clkr.hw.init = &(struct clk_init_data){ 763 .name = "byte1_clk_src", 764 .parent_names = mmss_xo_dsibyte, 765 .num_parents = 3, 766 .ops = &clk_byte2_ops, 767 .flags = CLK_SET_RATE_PARENT, 768 }, 769 }; 770 771 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 772 F(19200000, P_XO, 1, 0, 0), 773 { } 774 }; 775 776 static struct clk_rcg2 esc0_clk_src = { 777 .cmd_rcgr = 0x2160, 778 .hid_width = 5, 779 .parent_map = mmss_xo_dsibyte_map, 780 .freq_tbl = ftbl_mdss_esc0_1_clk, 781 .clkr.hw.init = &(struct clk_init_data){ 782 .name = "esc0_clk_src", 783 .parent_names = mmss_xo_dsibyte, 784 .num_parents = 3, 785 .ops = &clk_rcg2_ops, 786 }, 787 }; 788 789 static struct clk_rcg2 esc1_clk_src = { 790 .cmd_rcgr = 0x2180, 791 .hid_width = 5, 792 .parent_map = mmss_xo_dsibyte_map, 793 .freq_tbl = ftbl_mdss_esc0_1_clk, 794 .clkr.hw.init = &(struct clk_init_data){ 795 .name = "esc1_clk_src", 796 .parent_names = mmss_xo_dsibyte, 797 .num_parents = 3, 798 .ops = &clk_rcg2_ops, 799 }, 800 }; 801 802 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 803 F(10000, P_XO, 16, 1, 120), 804 F(24000, P_XO, 16, 1, 50), 805 F(6000000, P_GPLL0_DIV, 10, 1, 5), 806 F(12000000, P_GPLL0_DIV, 1, 1, 25), 807 F(13000000, P_GPLL0_DIV, 2, 13, 150), 808 F(24000000, P_GPLL0_DIV, 1, 2, 25), 809 { } 810 }; 811 812 static struct clk_rcg2 camss_gp0_clk_src = { 813 .cmd_rcgr = 0x3420, 814 .mnd_width = 8, 815 .hid_width = 5, 816 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 817 .freq_tbl = ftbl_camss_gp0_clk_src, 818 .clkr.hw.init = &(struct clk_init_data){ 819 .name = "camss_gp0_clk_src", 820 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 821 .num_parents = 5, 822 .ops = &clk_rcg2_ops, 823 }, 824 }; 825 826 static struct clk_rcg2 camss_gp1_clk_src = { 827 .cmd_rcgr = 0x3450, 828 .mnd_width = 8, 829 .hid_width = 5, 830 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 831 .freq_tbl = ftbl_camss_gp0_clk_src, 832 .clkr.hw.init = &(struct clk_init_data){ 833 .name = "camss_gp1_clk_src", 834 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 835 .num_parents = 5, 836 .ops = &clk_rcg2_ops, 837 }, 838 }; 839 840 static const struct freq_tbl ftbl_mclk0_clk_src[] = { 841 F(4800000, P_XO, 4, 0, 0), 842 F(6000000, P_GPLL0_DIV, 10, 1, 5), 843 F(8000000, P_GPLL0_DIV, 1, 2, 75), 844 F(9600000, P_XO, 2, 0, 0), 845 F(16666667, P_GPLL0_DIV, 2, 1, 9), 846 F(19200000, P_XO, 1, 0, 0), 847 F(24000000, P_GPLL0_DIV, 1, 2, 25), 848 F(33333333, P_GPLL0_DIV, 1, 1, 9), 849 F(48000000, P_GPLL0, 1, 2, 25), 850 F(66666667, P_GPLL0, 1, 1, 9), 851 { } 852 }; 853 854 static struct clk_rcg2 mclk0_clk_src = { 855 .cmd_rcgr = 0x3360, 856 .mnd_width = 8, 857 .hid_width = 5, 858 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 859 .freq_tbl = ftbl_mclk0_clk_src, 860 .clkr.hw.init = &(struct clk_init_data){ 861 .name = "mclk0_clk_src", 862 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 863 .num_parents = 5, 864 .ops = &clk_rcg2_ops, 865 }, 866 }; 867 868 static struct clk_rcg2 mclk1_clk_src = { 869 .cmd_rcgr = 0x3390, 870 .mnd_width = 8, 871 .hid_width = 5, 872 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 873 .freq_tbl = ftbl_mclk0_clk_src, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "mclk1_clk_src", 876 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 877 .num_parents = 5, 878 .ops = &clk_rcg2_ops, 879 }, 880 }; 881 882 static struct clk_rcg2 mclk2_clk_src = { 883 .cmd_rcgr = 0x33c0, 884 .mnd_width = 8, 885 .hid_width = 5, 886 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 887 .freq_tbl = ftbl_mclk0_clk_src, 888 .clkr.hw.init = &(struct clk_init_data){ 889 .name = "mclk2_clk_src", 890 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 891 .num_parents = 5, 892 .ops = &clk_rcg2_ops, 893 }, 894 }; 895 896 static struct clk_rcg2 mclk3_clk_src = { 897 .cmd_rcgr = 0x33f0, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 901 .freq_tbl = ftbl_mclk0_clk_src, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "mclk3_clk_src", 904 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 905 .num_parents = 5, 906 .ops = &clk_rcg2_ops, 907 }, 908 }; 909 910 static const struct freq_tbl ftbl_cci_clk_src[] = { 911 F(19200000, P_XO, 1, 0, 0), 912 F(37500000, P_GPLL0, 16, 0, 0), 913 F(50000000, P_GPLL0, 12, 0, 0), 914 F(100000000, P_GPLL0, 6, 0, 0), 915 { } 916 }; 917 918 static struct clk_rcg2 cci_clk_src = { 919 .cmd_rcgr = 0x3300, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 923 .freq_tbl = ftbl_cci_clk_src, 924 .clkr.hw.init = &(struct clk_init_data){ 925 .name = "cci_clk_src", 926 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 927 .num_parents = 5, 928 .ops = &clk_rcg2_ops, 929 }, 930 }; 931 932 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 933 F(100000000, P_GPLL0_DIV, 3, 0, 0), 934 F(200000000, P_GPLL0, 3, 0, 0), 935 F(266666667, P_MMPLL0, 3, 0, 0), 936 { } 937 }; 938 939 static struct clk_rcg2 csi0phytimer_clk_src = { 940 .cmd_rcgr = 0x3000, 941 .hid_width = 5, 942 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 943 .freq_tbl = ftbl_csi0phytimer_clk_src, 944 .clkr.hw.init = &(struct clk_init_data){ 945 .name = "csi0phytimer_clk_src", 946 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 947 .num_parents = 7, 948 .ops = &clk_rcg2_ops, 949 }, 950 }; 951 952 static struct clk_rcg2 csi1phytimer_clk_src = { 953 .cmd_rcgr = 0x3030, 954 .hid_width = 5, 955 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 956 .freq_tbl = ftbl_csi0phytimer_clk_src, 957 .clkr.hw.init = &(struct clk_init_data){ 958 .name = "csi1phytimer_clk_src", 959 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 960 .num_parents = 7, 961 .ops = &clk_rcg2_ops, 962 }, 963 }; 964 965 static struct clk_rcg2 csi2phytimer_clk_src = { 966 .cmd_rcgr = 0x3060, 967 .hid_width = 5, 968 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 969 .freq_tbl = ftbl_csi0phytimer_clk_src, 970 .clkr.hw.init = &(struct clk_init_data){ 971 .name = "csi2phytimer_clk_src", 972 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 973 .num_parents = 7, 974 .ops = &clk_rcg2_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = { 979 F(100000000, P_GPLL0_DIV, 3, 0, 0), 980 F(200000000, P_GPLL0, 3, 0, 0), 981 F(320000000, P_MMPLL4, 3, 0, 0), 982 F(384000000, P_MMPLL4, 2.5, 0, 0), 983 { } 984 }; 985 986 static struct clk_rcg2 csiphy0_3p_clk_src = { 987 .cmd_rcgr = 0x3240, 988 .hid_width = 5, 989 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 990 .freq_tbl = ftbl_csiphy0_3p_clk_src, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "csiphy0_3p_clk_src", 993 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 994 .num_parents = 7, 995 .ops = &clk_rcg2_ops, 996 }, 997 }; 998 999 static struct clk_rcg2 csiphy1_3p_clk_src = { 1000 .cmd_rcgr = 0x3260, 1001 .hid_width = 5, 1002 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1003 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 .name = "csiphy1_3p_clk_src", 1006 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1007 .num_parents = 7, 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static struct clk_rcg2 csiphy2_3p_clk_src = { 1013 .cmd_rcgr = 0x3280, 1014 .hid_width = 5, 1015 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1016 .freq_tbl = ftbl_csiphy0_3p_clk_src, 1017 .clkr.hw.init = &(struct clk_init_data){ 1018 .name = "csiphy2_3p_clk_src", 1019 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1020 .num_parents = 7, 1021 .ops = &clk_rcg2_ops, 1022 }, 1023 }; 1024 1025 static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 1026 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1027 F(150000000, P_GPLL0, 4, 0, 0), 1028 F(228571429, P_MMPLL0, 3.5, 0, 0), 1029 F(266666667, P_MMPLL0, 3, 0, 0), 1030 F(320000000, P_MMPLL0, 2.5, 0, 0), 1031 F(480000000, P_MMPLL4, 2, 0, 0), 1032 { } 1033 }; 1034 1035 static struct clk_rcg2 jpeg0_clk_src = { 1036 .cmd_rcgr = 0x3500, 1037 .hid_width = 5, 1038 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1039 .freq_tbl = ftbl_jpeg0_clk_src, 1040 .clkr.hw.init = &(struct clk_init_data){ 1041 .name = "jpeg0_clk_src", 1042 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1043 .num_parents = 7, 1044 .ops = &clk_rcg2_ops, 1045 }, 1046 }; 1047 1048 static const struct freq_tbl ftbl_jpeg2_clk_src[] = { 1049 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1050 F(150000000, P_GPLL0, 4, 0, 0), 1051 F(228571429, P_MMPLL0, 3.5, 0, 0), 1052 F(266666667, P_MMPLL0, 3, 0, 0), 1053 F(320000000, P_MMPLL0, 2.5, 0, 0), 1054 { } 1055 }; 1056 1057 static struct clk_rcg2 jpeg2_clk_src = { 1058 .cmd_rcgr = 0x3540, 1059 .hid_width = 5, 1060 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1061 .freq_tbl = ftbl_jpeg2_clk_src, 1062 .clkr.hw.init = &(struct clk_init_data){ 1063 .name = "jpeg2_clk_src", 1064 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1065 .num_parents = 7, 1066 .ops = &clk_rcg2_ops, 1067 }, 1068 }; 1069 1070 static struct clk_rcg2 jpeg_dma_clk_src = { 1071 .cmd_rcgr = 0x3560, 1072 .hid_width = 5, 1073 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1074 .freq_tbl = ftbl_jpeg0_clk_src, 1075 .clkr.hw.init = &(struct clk_init_data){ 1076 .name = "jpeg_dma_clk_src", 1077 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1078 .num_parents = 7, 1079 .ops = &clk_rcg2_ops, 1080 }, 1081 }; 1082 1083 static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1084 F(75000000, P_GPLL0_DIV, 4, 0, 0), 1085 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1086 F(300000000, P_GPLL0, 2, 0, 0), 1087 F(320000000, P_MMPLL0, 2.5, 0, 0), 1088 F(480000000, P_MMPLL4, 2, 0, 0), 1089 F(600000000, P_GPLL0, 1, 0, 0), 1090 { } 1091 }; 1092 1093 static struct clk_rcg2 vfe0_clk_src = { 1094 .cmd_rcgr = 0x3600, 1095 .hid_width = 5, 1096 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1097 .freq_tbl = ftbl_vfe0_clk_src, 1098 .clkr.hw.init = &(struct clk_init_data){ 1099 .name = "vfe0_clk_src", 1100 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1101 .num_parents = 7, 1102 .ops = &clk_rcg2_ops, 1103 }, 1104 }; 1105 1106 static struct clk_rcg2 vfe1_clk_src = { 1107 .cmd_rcgr = 0x3620, 1108 .hid_width = 5, 1109 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1110 .freq_tbl = ftbl_vfe0_clk_src, 1111 .clkr.hw.init = &(struct clk_init_data){ 1112 .name = "vfe1_clk_src", 1113 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1114 .num_parents = 7, 1115 .ops = &clk_rcg2_ops, 1116 }, 1117 }; 1118 1119 static const struct freq_tbl ftbl_cpp_clk_src[] = { 1120 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1121 F(200000000, P_GPLL0, 3, 0, 0), 1122 F(320000000, P_MMPLL0, 2.5, 0, 0), 1123 F(480000000, P_MMPLL4, 2, 0, 0), 1124 F(640000000, P_MMPLL4, 1.5, 0, 0), 1125 { } 1126 }; 1127 1128 static struct clk_rcg2 cpp_clk_src = { 1129 .cmd_rcgr = 0x3640, 1130 .hid_width = 5, 1131 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1132 .freq_tbl = ftbl_cpp_clk_src, 1133 .clkr.hw.init = &(struct clk_init_data){ 1134 .name = "cpp_clk_src", 1135 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1136 .num_parents = 7, 1137 .ops = &clk_rcg2_ops, 1138 }, 1139 }; 1140 1141 static const struct freq_tbl ftbl_csi0_clk_src[] = { 1142 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1143 F(200000000, P_GPLL0, 3, 0, 0), 1144 F(266666667, P_MMPLL0, 3, 0, 0), 1145 F(480000000, P_MMPLL4, 2, 0, 0), 1146 F(600000000, P_GPLL0, 1, 0, 0), 1147 { } 1148 }; 1149 1150 static struct clk_rcg2 csi0_clk_src = { 1151 .cmd_rcgr = 0x3090, 1152 .hid_width = 5, 1153 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1154 .freq_tbl = ftbl_csi0_clk_src, 1155 .clkr.hw.init = &(struct clk_init_data){ 1156 .name = "csi0_clk_src", 1157 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1158 .num_parents = 7, 1159 .ops = &clk_rcg2_ops, 1160 }, 1161 }; 1162 1163 static struct clk_rcg2 csi1_clk_src = { 1164 .cmd_rcgr = 0x3100, 1165 .hid_width = 5, 1166 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1167 .freq_tbl = ftbl_csi0_clk_src, 1168 .clkr.hw.init = &(struct clk_init_data){ 1169 .name = "csi1_clk_src", 1170 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1171 .num_parents = 7, 1172 .ops = &clk_rcg2_ops, 1173 }, 1174 }; 1175 1176 static struct clk_rcg2 csi2_clk_src = { 1177 .cmd_rcgr = 0x3160, 1178 .hid_width = 5, 1179 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1180 .freq_tbl = ftbl_csi0_clk_src, 1181 .clkr.hw.init = &(struct clk_init_data){ 1182 .name = "csi2_clk_src", 1183 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1184 .num_parents = 7, 1185 .ops = &clk_rcg2_ops, 1186 }, 1187 }; 1188 1189 static struct clk_rcg2 csi3_clk_src = { 1190 .cmd_rcgr = 0x31c0, 1191 .hid_width = 5, 1192 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map, 1193 .freq_tbl = ftbl_csi0_clk_src, 1194 .clkr.hw.init = &(struct clk_init_data){ 1195 .name = "csi3_clk_src", 1196 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, 1197 .num_parents = 7, 1198 .ops = &clk_rcg2_ops, 1199 }, 1200 }; 1201 1202 static const struct freq_tbl ftbl_fd_core_clk_src[] = { 1203 F(100000000, P_GPLL0_DIV, 3, 0, 0), 1204 F(200000000, P_GPLL0, 3, 0, 0), 1205 F(400000000, P_MMPLL0, 2, 0, 0), 1206 { } 1207 }; 1208 1209 static struct clk_rcg2 fd_core_clk_src = { 1210 .cmd_rcgr = 0x3b00, 1211 .hid_width = 5, 1212 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map, 1213 .freq_tbl = ftbl_fd_core_clk_src, 1214 .clkr.hw.init = &(struct clk_init_data){ 1215 .name = "fd_core_clk_src", 1216 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, 1217 .num_parents = 5, 1218 .ops = &clk_rcg2_ops, 1219 }, 1220 }; 1221 1222 static struct clk_branch mmss_mmagic_ahb_clk = { 1223 .halt_reg = 0x5024, 1224 .clkr = { 1225 .enable_reg = 0x5024, 1226 .enable_mask = BIT(0), 1227 .hw.init = &(struct clk_init_data){ 1228 .name = "mmss_mmagic_ahb_clk", 1229 .parent_names = (const char *[]){ "ahb_clk_src" }, 1230 .num_parents = 1, 1231 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch mmss_mmagic_cfg_ahb_clk = { 1238 .halt_reg = 0x5054, 1239 .clkr = { 1240 .enable_reg = 0x5054, 1241 .enable_mask = BIT(0), 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "mmss_mmagic_cfg_ahb_clk", 1244 .parent_names = (const char *[]){ "ahb_clk_src" }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch mmss_misc_ahb_clk = { 1253 .halt_reg = 0x5018, 1254 .clkr = { 1255 .enable_reg = 0x5018, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "mmss_misc_ahb_clk", 1259 .parent_names = (const char *[]){ "ahb_clk_src" }, 1260 .num_parents = 1, 1261 .flags = CLK_SET_RATE_PARENT, 1262 .ops = &clk_branch2_ops, 1263 }, 1264 }, 1265 }; 1266 1267 static struct clk_branch mmss_misc_cxo_clk = { 1268 .halt_reg = 0x5014, 1269 .clkr = { 1270 .enable_reg = 0x5014, 1271 .enable_mask = BIT(0), 1272 .hw.init = &(struct clk_init_data){ 1273 .name = "mmss_misc_cxo_clk", 1274 .parent_names = (const char *[]){ "xo" }, 1275 .num_parents = 1, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch mmss_mmagic_axi_clk = { 1282 .halt_reg = 0x506c, 1283 .clkr = { 1284 .enable_reg = 0x506c, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "mmss_mmagic_axi_clk", 1288 .parent_names = (const char *[]){ "axi_clk_src" }, 1289 .num_parents = 1, 1290 .flags = CLK_SET_RATE_PARENT, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294 }; 1295 1296 static struct clk_branch mmss_mmagic_maxi_clk = { 1297 .halt_reg = 0x5074, 1298 .clkr = { 1299 .enable_reg = 0x5074, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "mmss_mmagic_maxi_clk", 1303 .parent_names = (const char *[]){ "maxi_clk_src" }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch mmagic_camss_axi_clk = { 1312 .halt_reg = 0x3c44, 1313 .clkr = { 1314 .enable_reg = 0x3c44, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "mmagic_camss_axi_clk", 1318 .parent_names = (const char *[]){ "axi_clk_src" }, 1319 .num_parents = 1, 1320 .flags = CLK_SET_RATE_PARENT, 1321 .ops = &clk_branch2_ops, 1322 }, 1323 }, 1324 }; 1325 1326 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { 1327 .halt_reg = 0x3c48, 1328 .clkr = { 1329 .enable_reg = 0x3c48, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "mmagic_camss_noc_cfg_ahb_clk", 1333 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch smmu_vfe_ahb_clk = { 1342 .halt_reg = 0x3c04, 1343 .clkr = { 1344 .enable_reg = 0x3c04, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "smmu_vfe_ahb_clk", 1348 .parent_names = (const char *[]){ "ahb_clk_src" }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch smmu_vfe_axi_clk = { 1357 .halt_reg = 0x3c08, 1358 .clkr = { 1359 .enable_reg = 0x3c08, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "smmu_vfe_axi_clk", 1363 .parent_names = (const char *[]){ "axi_clk_src" }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch smmu_cpp_ahb_clk = { 1372 .halt_reg = 0x3c14, 1373 .clkr = { 1374 .enable_reg = 0x3c14, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "smmu_cpp_ahb_clk", 1378 .parent_names = (const char *[]){ "ahb_clk_src" }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch smmu_cpp_axi_clk = { 1387 .halt_reg = 0x3c18, 1388 .clkr = { 1389 .enable_reg = 0x3c18, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "smmu_cpp_axi_clk", 1393 .parent_names = (const char *[]){ "axi_clk_src" }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch smmu_jpeg_ahb_clk = { 1402 .halt_reg = 0x3c24, 1403 .clkr = { 1404 .enable_reg = 0x3c24, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "smmu_jpeg_ahb_clk", 1408 .parent_names = (const char *[]){ "ahb_clk_src" }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 .ops = &clk_branch2_ops, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch smmu_jpeg_axi_clk = { 1417 .halt_reg = 0x3c28, 1418 .clkr = { 1419 .enable_reg = 0x3c28, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "smmu_jpeg_axi_clk", 1423 .parent_names = (const char *[]){ "axi_clk_src" }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch mmagic_mdss_axi_clk = { 1432 .halt_reg = 0x2474, 1433 .clkr = { 1434 .enable_reg = 0x2474, 1435 .enable_mask = BIT(0), 1436 .hw.init = &(struct clk_init_data){ 1437 .name = "mmagic_mdss_axi_clk", 1438 .parent_names = (const char *[]){ "axi_clk_src" }, 1439 .num_parents = 1, 1440 .flags = CLK_SET_RATE_PARENT, 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { 1447 .halt_reg = 0x2478, 1448 .clkr = { 1449 .enable_reg = 0x2478, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "mmagic_mdss_noc_cfg_ahb_clk", 1453 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch smmu_rot_ahb_clk = { 1462 .halt_reg = 0x2444, 1463 .clkr = { 1464 .enable_reg = 0x2444, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "smmu_rot_ahb_clk", 1468 .parent_names = (const char *[]){ "ahb_clk_src" }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch smmu_rot_axi_clk = { 1477 .halt_reg = 0x2448, 1478 .clkr = { 1479 .enable_reg = 0x2448, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "smmu_rot_axi_clk", 1483 .parent_names = (const char *[]){ "axi_clk_src" }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch smmu_mdp_ahb_clk = { 1492 .halt_reg = 0x2454, 1493 .clkr = { 1494 .enable_reg = 0x2454, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "smmu_mdp_ahb_clk", 1498 .parent_names = (const char *[]){ "ahb_clk_src" }, 1499 .num_parents = 1, 1500 .flags = CLK_SET_RATE_PARENT, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch smmu_mdp_axi_clk = { 1507 .halt_reg = 0x2458, 1508 .clkr = { 1509 .enable_reg = 0x2458, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "smmu_mdp_axi_clk", 1513 .parent_names = (const char *[]){ "axi_clk_src" }, 1514 .num_parents = 1, 1515 .flags = CLK_SET_RATE_PARENT, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch mmagic_video_axi_clk = { 1522 .halt_reg = 0x1194, 1523 .clkr = { 1524 .enable_reg = 0x1194, 1525 .enable_mask = BIT(0), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "mmagic_video_axi_clk", 1528 .parent_names = (const char *[]){ "axi_clk_src" }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { 1537 .halt_reg = 0x1198, 1538 .clkr = { 1539 .enable_reg = 0x1198, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "mmagic_video_noc_cfg_ahb_clk", 1543 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch smmu_video_ahb_clk = { 1552 .halt_reg = 0x1174, 1553 .clkr = { 1554 .enable_reg = 0x1174, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "smmu_video_ahb_clk", 1558 .parent_names = (const char *[]){ "ahb_clk_src" }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch smmu_video_axi_clk = { 1567 .halt_reg = 0x1178, 1568 .clkr = { 1569 .enable_reg = 0x1178, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "smmu_video_axi_clk", 1573 .parent_names = (const char *[]){ "axi_clk_src" }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch mmagic_bimc_axi_clk = { 1582 .halt_reg = 0x5294, 1583 .clkr = { 1584 .enable_reg = 0x5294, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "mmagic_bimc_axi_clk", 1588 .parent_names = (const char *[]){ "axi_clk_src" }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { 1597 .halt_reg = 0x5298, 1598 .clkr = { 1599 .enable_reg = 0x5298, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "mmagic_bimc_noc_cfg_ahb_clk", 1603 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gpu_gx_gfx3d_clk = { 1612 .halt_reg = 0x4028, 1613 .clkr = { 1614 .enable_reg = 0x4028, 1615 .enable_mask = BIT(0), 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "gpu_gx_gfx3d_clk", 1618 .parent_names = (const char *[]){ "gfx3d_clk_src" }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gpu_gx_rbbmtimer_clk = { 1627 .halt_reg = 0x40b0, 1628 .clkr = { 1629 .enable_reg = 0x40b0, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "gpu_gx_rbbmtimer_clk", 1633 .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gpu_ahb_clk = { 1642 .halt_reg = 0x403c, 1643 .clkr = { 1644 .enable_reg = 0x403c, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gpu_ahb_clk", 1648 .parent_names = (const char *[]){ "ahb_clk_src" }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gpu_aon_isense_clk = { 1657 .halt_reg = 0x4044, 1658 .clkr = { 1659 .enable_reg = 0x4044, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gpu_aon_isense_clk", 1663 .parent_names = (const char *[]){ "isense_clk_src" }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch vmem_maxi_clk = { 1672 .halt_reg = 0x1204, 1673 .clkr = { 1674 .enable_reg = 0x1204, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(struct clk_init_data){ 1677 .name = "vmem_maxi_clk", 1678 .parent_names = (const char *[]){ "maxi_clk_src" }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch vmem_ahb_clk = { 1687 .halt_reg = 0x1208, 1688 .clkr = { 1689 .enable_reg = 0x1208, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "vmem_ahb_clk", 1693 .parent_names = (const char *[]){ "ahb_clk_src" }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch mmss_rbcpr_clk = { 1702 .halt_reg = 0x4084, 1703 .clkr = { 1704 .enable_reg = 0x4084, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "mmss_rbcpr_clk", 1708 .parent_names = (const char *[]){ "rbcpr_clk_src" }, 1709 .num_parents = 1, 1710 .flags = CLK_SET_RATE_PARENT, 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch mmss_rbcpr_ahb_clk = { 1717 .halt_reg = 0x4088, 1718 .clkr = { 1719 .enable_reg = 0x4088, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "mmss_rbcpr_ahb_clk", 1723 .parent_names = (const char *[]){ "ahb_clk_src" }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch video_core_clk = { 1732 .halt_reg = 0x1028, 1733 .clkr = { 1734 .enable_reg = 0x1028, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "video_core_clk", 1738 .parent_names = (const char *[]){ "video_core_clk_src" }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch video_axi_clk = { 1747 .halt_reg = 0x1034, 1748 .clkr = { 1749 .enable_reg = 0x1034, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "video_axi_clk", 1753 .parent_names = (const char *[]){ "axi_clk_src" }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch video_maxi_clk = { 1762 .halt_reg = 0x1038, 1763 .clkr = { 1764 .enable_reg = 0x1038, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(struct clk_init_data){ 1767 .name = "video_maxi_clk", 1768 .parent_names = (const char *[]){ "maxi_clk_src" }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch video_ahb_clk = { 1777 .halt_reg = 0x1030, 1778 .clkr = { 1779 .enable_reg = 0x1030, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "video_ahb_clk", 1783 .parent_names = (const char *[]){ "ahb_clk_src" }, 1784 .num_parents = 1, 1785 .flags = CLK_SET_RATE_PARENT, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch video_subcore0_clk = { 1792 .halt_reg = 0x1048, 1793 .clkr = { 1794 .enable_reg = 0x1048, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "video_subcore0_clk", 1798 .parent_names = (const char *[]){ "video_subcore0_clk_src" }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch video_subcore1_clk = { 1807 .halt_reg = 0x104c, 1808 .clkr = { 1809 .enable_reg = 0x104c, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "video_subcore1_clk", 1813 .parent_names = (const char *[]){ "video_subcore1_clk_src" }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch mdss_ahb_clk = { 1822 .halt_reg = 0x2308, 1823 .clkr = { 1824 .enable_reg = 0x2308, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(struct clk_init_data){ 1827 .name = "mdss_ahb_clk", 1828 .parent_names = (const char *[]){ "ahb_clk_src" }, 1829 .num_parents = 1, 1830 .flags = CLK_SET_RATE_PARENT, 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch mdss_hdmi_ahb_clk = { 1837 .halt_reg = 0x230c, 1838 .clkr = { 1839 .enable_reg = 0x230c, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "mdss_hdmi_ahb_clk", 1843 .parent_names = (const char *[]){ "ahb_clk_src" }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch mdss_axi_clk = { 1852 .halt_reg = 0x2310, 1853 .clkr = { 1854 .enable_reg = 0x2310, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "mdss_axi_clk", 1858 .parent_names = (const char *[]){ "axi_clk_src" }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch mdss_pclk0_clk = { 1867 .halt_reg = 0x2314, 1868 .clkr = { 1869 .enable_reg = 0x2314, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "mdss_pclk0_clk", 1873 .parent_names = (const char *[]){ "pclk0_clk_src" }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch mdss_pclk1_clk = { 1882 .halt_reg = 0x2318, 1883 .clkr = { 1884 .enable_reg = 0x2318, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "mdss_pclk1_clk", 1888 .parent_names = (const char *[]){ "pclk1_clk_src" }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch mdss_mdp_clk = { 1897 .halt_reg = 0x231c, 1898 .clkr = { 1899 .enable_reg = 0x231c, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "mdss_mdp_clk", 1903 .parent_names = (const char *[]){ "mdp_clk_src" }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch mdss_extpclk_clk = { 1912 .halt_reg = 0x2324, 1913 .clkr = { 1914 .enable_reg = 0x2324, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "mdss_extpclk_clk", 1918 .parent_names = (const char *[]){ "extpclk_clk_src" }, 1919 .num_parents = 1, 1920 .flags = CLK_SET_RATE_PARENT, 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924 }; 1925 1926 static struct clk_branch mdss_vsync_clk = { 1927 .halt_reg = 0x2328, 1928 .clkr = { 1929 .enable_reg = 0x2328, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "mdss_vsync_clk", 1933 .parent_names = (const char *[]){ "vsync_clk_src" }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch mdss_hdmi_clk = { 1942 .halt_reg = 0x2338, 1943 .clkr = { 1944 .enable_reg = 0x2338, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "mdss_hdmi_clk", 1948 .parent_names = (const char *[]){ "hdmi_clk_src" }, 1949 .num_parents = 1, 1950 .flags = CLK_SET_RATE_PARENT, 1951 .ops = &clk_branch2_ops, 1952 }, 1953 }, 1954 }; 1955 1956 static struct clk_branch mdss_byte0_clk = { 1957 .halt_reg = 0x233c, 1958 .clkr = { 1959 .enable_reg = 0x233c, 1960 .enable_mask = BIT(0), 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "mdss_byte0_clk", 1963 .parent_names = (const char *[]){ "byte0_clk_src" }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch mdss_byte1_clk = { 1972 .halt_reg = 0x2340, 1973 .clkr = { 1974 .enable_reg = 0x2340, 1975 .enable_mask = BIT(0), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "mdss_byte1_clk", 1978 .parent_names = (const char *[]){ "byte1_clk_src" }, 1979 .num_parents = 1, 1980 .flags = CLK_SET_RATE_PARENT, 1981 .ops = &clk_branch2_ops, 1982 }, 1983 }, 1984 }; 1985 1986 static struct clk_branch mdss_esc0_clk = { 1987 .halt_reg = 0x2344, 1988 .clkr = { 1989 .enable_reg = 0x2344, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "mdss_esc0_clk", 1993 .parent_names = (const char *[]){ "esc0_clk_src" }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch mdss_esc1_clk = { 2002 .halt_reg = 0x2348, 2003 .clkr = { 2004 .enable_reg = 0x2348, 2005 .enable_mask = BIT(0), 2006 .hw.init = &(struct clk_init_data){ 2007 .name = "mdss_esc1_clk", 2008 .parent_names = (const char *[]){ "esc1_clk_src" }, 2009 .num_parents = 1, 2010 .flags = CLK_SET_RATE_PARENT, 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch camss_top_ahb_clk = { 2017 .halt_reg = 0x3484, 2018 .clkr = { 2019 .enable_reg = 0x3484, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(struct clk_init_data){ 2022 .name = "camss_top_ahb_clk", 2023 .parent_names = (const char *[]){ "ahb_clk_src" }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch camss_ahb_clk = { 2032 .halt_reg = 0x348c, 2033 .clkr = { 2034 .enable_reg = 0x348c, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(struct clk_init_data){ 2037 .name = "camss_ahb_clk", 2038 .parent_names = (const char *[]){ "ahb_clk_src" }, 2039 .num_parents = 1, 2040 .flags = CLK_SET_RATE_PARENT, 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch camss_micro_ahb_clk = { 2047 .halt_reg = 0x3494, 2048 .clkr = { 2049 .enable_reg = 0x3494, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "camss_micro_ahb_clk", 2053 .parent_names = (const char *[]){ "ahb_clk_src" }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch camss_gp0_clk = { 2062 .halt_reg = 0x3444, 2063 .clkr = { 2064 .enable_reg = 0x3444, 2065 .enable_mask = BIT(0), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "camss_gp0_clk", 2068 .parent_names = (const char *[]){ "camss_gp0_clk_src" }, 2069 .num_parents = 1, 2070 .flags = CLK_SET_RATE_PARENT, 2071 .ops = &clk_branch2_ops, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch camss_gp1_clk = { 2077 .halt_reg = 0x3474, 2078 .clkr = { 2079 .enable_reg = 0x3474, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "camss_gp1_clk", 2083 .parent_names = (const char *[]){ "camss_gp1_clk_src" }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch camss_mclk0_clk = { 2092 .halt_reg = 0x3384, 2093 .clkr = { 2094 .enable_reg = 0x3384, 2095 .enable_mask = BIT(0), 2096 .hw.init = &(struct clk_init_data){ 2097 .name = "camss_mclk0_clk", 2098 .parent_names = (const char *[]){ "mclk0_clk_src" }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch camss_mclk1_clk = { 2107 .halt_reg = 0x33b4, 2108 .clkr = { 2109 .enable_reg = 0x33b4, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "camss_mclk1_clk", 2113 .parent_names = (const char *[]){ "mclk1_clk_src" }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch camss_mclk2_clk = { 2122 .halt_reg = 0x33e4, 2123 .clkr = { 2124 .enable_reg = 0x33e4, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "camss_mclk2_clk", 2128 .parent_names = (const char *[]){ "mclk2_clk_src" }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch camss_mclk3_clk = { 2137 .halt_reg = 0x3414, 2138 .clkr = { 2139 .enable_reg = 0x3414, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "camss_mclk3_clk", 2143 .parent_names = (const char *[]){ "mclk3_clk_src" }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149 }; 2150 2151 static struct clk_branch camss_cci_clk = { 2152 .halt_reg = 0x3344, 2153 .clkr = { 2154 .enable_reg = 0x3344, 2155 .enable_mask = BIT(0), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "camss_cci_clk", 2158 .parent_names = (const char *[]){ "cci_clk_src" }, 2159 .num_parents = 1, 2160 .flags = CLK_SET_RATE_PARENT, 2161 .ops = &clk_branch2_ops, 2162 }, 2163 }, 2164 }; 2165 2166 static struct clk_branch camss_cci_ahb_clk = { 2167 .halt_reg = 0x3348, 2168 .clkr = { 2169 .enable_reg = 0x3348, 2170 .enable_mask = BIT(0), 2171 .hw.init = &(struct clk_init_data){ 2172 .name = "camss_cci_ahb_clk", 2173 .parent_names = (const char *[]){ "ahb_clk_src" }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch camss_csi0phytimer_clk = { 2182 .halt_reg = 0x3024, 2183 .clkr = { 2184 .enable_reg = 0x3024, 2185 .enable_mask = BIT(0), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "camss_csi0phytimer_clk", 2188 .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, 2189 .num_parents = 1, 2190 .flags = CLK_SET_RATE_PARENT, 2191 .ops = &clk_branch2_ops, 2192 }, 2193 }, 2194 }; 2195 2196 static struct clk_branch camss_csi1phytimer_clk = { 2197 .halt_reg = 0x3054, 2198 .clkr = { 2199 .enable_reg = 0x3054, 2200 .enable_mask = BIT(0), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "camss_csi1phytimer_clk", 2203 .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, 2204 .num_parents = 1, 2205 .flags = CLK_SET_RATE_PARENT, 2206 .ops = &clk_branch2_ops, 2207 }, 2208 }, 2209 }; 2210 2211 static struct clk_branch camss_csi2phytimer_clk = { 2212 .halt_reg = 0x3084, 2213 .clkr = { 2214 .enable_reg = 0x3084, 2215 .enable_mask = BIT(0), 2216 .hw.init = &(struct clk_init_data){ 2217 .name = "camss_csi2phytimer_clk", 2218 .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, 2219 .num_parents = 1, 2220 .flags = CLK_SET_RATE_PARENT, 2221 .ops = &clk_branch2_ops, 2222 }, 2223 }, 2224 }; 2225 2226 static struct clk_branch camss_csiphy0_3p_clk = { 2227 .halt_reg = 0x3234, 2228 .clkr = { 2229 .enable_reg = 0x3234, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(struct clk_init_data){ 2232 .name = "camss_csiphy0_3p_clk", 2233 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, 2234 .num_parents = 1, 2235 .flags = CLK_SET_RATE_PARENT, 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch camss_csiphy1_3p_clk = { 2242 .halt_reg = 0x3254, 2243 .clkr = { 2244 .enable_reg = 0x3254, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "camss_csiphy1_3p_clk", 2248 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, 2249 .num_parents = 1, 2250 .flags = CLK_SET_RATE_PARENT, 2251 .ops = &clk_branch2_ops, 2252 }, 2253 }, 2254 }; 2255 2256 static struct clk_branch camss_csiphy2_3p_clk = { 2257 .halt_reg = 0x3274, 2258 .clkr = { 2259 .enable_reg = 0x3274, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(struct clk_init_data){ 2262 .name = "camss_csiphy2_3p_clk", 2263 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, 2264 .num_parents = 1, 2265 .flags = CLK_SET_RATE_PARENT, 2266 .ops = &clk_branch2_ops, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch camss_jpeg0_clk = { 2272 .halt_reg = 0x35a8, 2273 .clkr = { 2274 .enable_reg = 0x35a8, 2275 .enable_mask = BIT(0), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "camss_jpeg0_clk", 2278 .parent_names = (const char *[]){ "jpeg0_clk_src" }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch camss_jpeg2_clk = { 2287 .halt_reg = 0x35b0, 2288 .clkr = { 2289 .enable_reg = 0x35b0, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "camss_jpeg2_clk", 2293 .parent_names = (const char *[]){ "jpeg2_clk_src" }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch camss_jpeg_dma_clk = { 2302 .halt_reg = 0x35c0, 2303 .clkr = { 2304 .enable_reg = 0x35c0, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "camss_jpeg_dma_clk", 2308 .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch camss_jpeg_ahb_clk = { 2317 .halt_reg = 0x35b4, 2318 .clkr = { 2319 .enable_reg = 0x35b4, 2320 .enable_mask = BIT(0), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "camss_jpeg_ahb_clk", 2323 .parent_names = (const char *[]){ "ahb_clk_src" }, 2324 .num_parents = 1, 2325 .flags = CLK_SET_RATE_PARENT, 2326 .ops = &clk_branch2_ops, 2327 }, 2328 }, 2329 }; 2330 2331 static struct clk_branch camss_jpeg_axi_clk = { 2332 .halt_reg = 0x35b8, 2333 .clkr = { 2334 .enable_reg = 0x35b8, 2335 .enable_mask = BIT(0), 2336 .hw.init = &(struct clk_init_data){ 2337 .name = "camss_jpeg_axi_clk", 2338 .parent_names = (const char *[]){ "axi_clk_src" }, 2339 .num_parents = 1, 2340 .flags = CLK_SET_RATE_PARENT, 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch camss_vfe_ahb_clk = { 2347 .halt_reg = 0x36b8, 2348 .clkr = { 2349 .enable_reg = 0x36b8, 2350 .enable_mask = BIT(0), 2351 .hw.init = &(struct clk_init_data){ 2352 .name = "camss_vfe_ahb_clk", 2353 .parent_names = (const char *[]){ "ahb_clk_src" }, 2354 .num_parents = 1, 2355 .flags = CLK_SET_RATE_PARENT, 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch camss_vfe_axi_clk = { 2362 .halt_reg = 0x36bc, 2363 .clkr = { 2364 .enable_reg = 0x36bc, 2365 .enable_mask = BIT(0), 2366 .hw.init = &(struct clk_init_data){ 2367 .name = "camss_vfe_axi_clk", 2368 .parent_names = (const char *[]){ "axi_clk_src" }, 2369 .num_parents = 1, 2370 .flags = CLK_SET_RATE_PARENT, 2371 .ops = &clk_branch2_ops, 2372 }, 2373 }, 2374 }; 2375 2376 static struct clk_branch camss_vfe0_clk = { 2377 .halt_reg = 0x36a8, 2378 .clkr = { 2379 .enable_reg = 0x36a8, 2380 .enable_mask = BIT(0), 2381 .hw.init = &(struct clk_init_data){ 2382 .name = "camss_vfe0_clk", 2383 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2384 .num_parents = 1, 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch camss_vfe0_stream_clk = { 2392 .halt_reg = 0x3720, 2393 .clkr = { 2394 .enable_reg = 0x3720, 2395 .enable_mask = BIT(0), 2396 .hw.init = &(struct clk_init_data){ 2397 .name = "camss_vfe0_stream_clk", 2398 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2399 .num_parents = 1, 2400 .flags = CLK_SET_RATE_PARENT, 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_branch camss_vfe0_ahb_clk = { 2407 .halt_reg = 0x3668, 2408 .clkr = { 2409 .enable_reg = 0x3668, 2410 .enable_mask = BIT(0), 2411 .hw.init = &(struct clk_init_data){ 2412 .name = "camss_vfe0_ahb_clk", 2413 .parent_names = (const char *[]){ "ahb_clk_src" }, 2414 .num_parents = 1, 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch camss_vfe1_clk = { 2422 .halt_reg = 0x36ac, 2423 .clkr = { 2424 .enable_reg = 0x36ac, 2425 .enable_mask = BIT(0), 2426 .hw.init = &(struct clk_init_data){ 2427 .name = "camss_vfe1_clk", 2428 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT, 2431 .ops = &clk_branch2_ops, 2432 }, 2433 }, 2434 }; 2435 2436 static struct clk_branch camss_vfe1_stream_clk = { 2437 .halt_reg = 0x3724, 2438 .clkr = { 2439 .enable_reg = 0x3724, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "camss_vfe1_stream_clk", 2443 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2444 .num_parents = 1, 2445 .flags = CLK_SET_RATE_PARENT, 2446 .ops = &clk_branch2_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch camss_vfe1_ahb_clk = { 2452 .halt_reg = 0x3678, 2453 .clkr = { 2454 .enable_reg = 0x3678, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "camss_vfe1_ahb_clk", 2458 .parent_names = (const char *[]){ "ahb_clk_src" }, 2459 .num_parents = 1, 2460 .flags = CLK_SET_RATE_PARENT, 2461 .ops = &clk_branch2_ops, 2462 }, 2463 }, 2464 }; 2465 2466 static struct clk_branch camss_csi_vfe0_clk = { 2467 .halt_reg = 0x3704, 2468 .clkr = { 2469 .enable_reg = 0x3704, 2470 .enable_mask = BIT(0), 2471 .hw.init = &(struct clk_init_data){ 2472 .name = "camss_csi_vfe0_clk", 2473 .parent_names = (const char *[]){ "vfe0_clk_src" }, 2474 .num_parents = 1, 2475 .flags = CLK_SET_RATE_PARENT, 2476 .ops = &clk_branch2_ops, 2477 }, 2478 }, 2479 }; 2480 2481 static struct clk_branch camss_csi_vfe1_clk = { 2482 .halt_reg = 0x3714, 2483 .clkr = { 2484 .enable_reg = 0x3714, 2485 .enable_mask = BIT(0), 2486 .hw.init = &(struct clk_init_data){ 2487 .name = "camss_csi_vfe1_clk", 2488 .parent_names = (const char *[]){ "vfe1_clk_src" }, 2489 .num_parents = 1, 2490 .flags = CLK_SET_RATE_PARENT, 2491 .ops = &clk_branch2_ops, 2492 }, 2493 }, 2494 }; 2495 2496 static struct clk_branch camss_cpp_vbif_ahb_clk = { 2497 .halt_reg = 0x36c8, 2498 .clkr = { 2499 .enable_reg = 0x36c8, 2500 .enable_mask = BIT(0), 2501 .hw.init = &(struct clk_init_data){ 2502 .name = "camss_cpp_vbif_ahb_clk", 2503 .parent_names = (const char *[]){ "ahb_clk_src" }, 2504 .num_parents = 1, 2505 .flags = CLK_SET_RATE_PARENT, 2506 .ops = &clk_branch2_ops, 2507 }, 2508 }, 2509 }; 2510 2511 static struct clk_branch camss_cpp_axi_clk = { 2512 .halt_reg = 0x36c4, 2513 .clkr = { 2514 .enable_reg = 0x36c4, 2515 .enable_mask = BIT(0), 2516 .hw.init = &(struct clk_init_data){ 2517 .name = "camss_cpp_axi_clk", 2518 .parent_names = (const char *[]){ "axi_clk_src" }, 2519 .num_parents = 1, 2520 .flags = CLK_SET_RATE_PARENT, 2521 .ops = &clk_branch2_ops, 2522 }, 2523 }, 2524 }; 2525 2526 static struct clk_branch camss_cpp_clk = { 2527 .halt_reg = 0x36b0, 2528 .clkr = { 2529 .enable_reg = 0x36b0, 2530 .enable_mask = BIT(0), 2531 .hw.init = &(struct clk_init_data){ 2532 .name = "camss_cpp_clk", 2533 .parent_names = (const char *[]){ "cpp_clk_src" }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch camss_cpp_ahb_clk = { 2542 .halt_reg = 0x36b4, 2543 .clkr = { 2544 .enable_reg = 0x36b4, 2545 .enable_mask = BIT(0), 2546 .hw.init = &(struct clk_init_data){ 2547 .name = "camss_cpp_ahb_clk", 2548 .parent_names = (const char *[]){ "ahb_clk_src" }, 2549 .num_parents = 1, 2550 .flags = CLK_SET_RATE_PARENT, 2551 .ops = &clk_branch2_ops, 2552 }, 2553 }, 2554 }; 2555 2556 static struct clk_branch camss_csi0_clk = { 2557 .halt_reg = 0x30b4, 2558 .clkr = { 2559 .enable_reg = 0x30b4, 2560 .enable_mask = BIT(0), 2561 .hw.init = &(struct clk_init_data){ 2562 .name = "camss_csi0_clk", 2563 .parent_names = (const char *[]){ "csi0_clk_src" }, 2564 .num_parents = 1, 2565 .flags = CLK_SET_RATE_PARENT, 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch camss_csi0_ahb_clk = { 2572 .halt_reg = 0x30bc, 2573 .clkr = { 2574 .enable_reg = 0x30bc, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "camss_csi0_ahb_clk", 2578 .parent_names = (const char *[]){ "ahb_clk_src" }, 2579 .num_parents = 1, 2580 .flags = CLK_SET_RATE_PARENT, 2581 .ops = &clk_branch2_ops, 2582 }, 2583 }, 2584 }; 2585 2586 static struct clk_branch camss_csi0phy_clk = { 2587 .halt_reg = 0x30c4, 2588 .clkr = { 2589 .enable_reg = 0x30c4, 2590 .enable_mask = BIT(0), 2591 .hw.init = &(struct clk_init_data){ 2592 .name = "camss_csi0phy_clk", 2593 .parent_names = (const char *[]){ "csi0_clk_src" }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch camss_csi0rdi_clk = { 2602 .halt_reg = 0x30d4, 2603 .clkr = { 2604 .enable_reg = 0x30d4, 2605 .enable_mask = BIT(0), 2606 .hw.init = &(struct clk_init_data){ 2607 .name = "camss_csi0rdi_clk", 2608 .parent_names = (const char *[]){ "csi0_clk_src" }, 2609 .num_parents = 1, 2610 .flags = CLK_SET_RATE_PARENT, 2611 .ops = &clk_branch2_ops, 2612 }, 2613 }, 2614 }; 2615 2616 static struct clk_branch camss_csi0pix_clk = { 2617 .halt_reg = 0x30e4, 2618 .clkr = { 2619 .enable_reg = 0x30e4, 2620 .enable_mask = BIT(0), 2621 .hw.init = &(struct clk_init_data){ 2622 .name = "camss_csi0pix_clk", 2623 .parent_names = (const char *[]){ "csi0_clk_src" }, 2624 .num_parents = 1, 2625 .flags = CLK_SET_RATE_PARENT, 2626 .ops = &clk_branch2_ops, 2627 }, 2628 }, 2629 }; 2630 2631 static struct clk_branch camss_csi1_clk = { 2632 .halt_reg = 0x3124, 2633 .clkr = { 2634 .enable_reg = 0x3124, 2635 .enable_mask = BIT(0), 2636 .hw.init = &(struct clk_init_data){ 2637 .name = "camss_csi1_clk", 2638 .parent_names = (const char *[]){ "csi1_clk_src" }, 2639 .num_parents = 1, 2640 .flags = CLK_SET_RATE_PARENT, 2641 .ops = &clk_branch2_ops, 2642 }, 2643 }, 2644 }; 2645 2646 static struct clk_branch camss_csi1_ahb_clk = { 2647 .halt_reg = 0x3128, 2648 .clkr = { 2649 .enable_reg = 0x3128, 2650 .enable_mask = BIT(0), 2651 .hw.init = &(struct clk_init_data){ 2652 .name = "camss_csi1_ahb_clk", 2653 .parent_names = (const char *[]){ "ahb_clk_src" }, 2654 .num_parents = 1, 2655 .flags = CLK_SET_RATE_PARENT, 2656 .ops = &clk_branch2_ops, 2657 }, 2658 }, 2659 }; 2660 2661 static struct clk_branch camss_csi1phy_clk = { 2662 .halt_reg = 0x3134, 2663 .clkr = { 2664 .enable_reg = 0x3134, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(struct clk_init_data){ 2667 .name = "camss_csi1phy_clk", 2668 .parent_names = (const char *[]){ "csi1_clk_src" }, 2669 .num_parents = 1, 2670 .flags = CLK_SET_RATE_PARENT, 2671 .ops = &clk_branch2_ops, 2672 }, 2673 }, 2674 }; 2675 2676 static struct clk_branch camss_csi1rdi_clk = { 2677 .halt_reg = 0x3144, 2678 .clkr = { 2679 .enable_reg = 0x3144, 2680 .enable_mask = BIT(0), 2681 .hw.init = &(struct clk_init_data){ 2682 .name = "camss_csi1rdi_clk", 2683 .parent_names = (const char *[]){ "csi1_clk_src" }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch camss_csi1pix_clk = { 2692 .halt_reg = 0x3154, 2693 .clkr = { 2694 .enable_reg = 0x3154, 2695 .enable_mask = BIT(0), 2696 .hw.init = &(struct clk_init_data){ 2697 .name = "camss_csi1pix_clk", 2698 .parent_names = (const char *[]){ "csi1_clk_src" }, 2699 .num_parents = 1, 2700 .flags = CLK_SET_RATE_PARENT, 2701 .ops = &clk_branch2_ops, 2702 }, 2703 }, 2704 }; 2705 2706 static struct clk_branch camss_csi2_clk = { 2707 .halt_reg = 0x3184, 2708 .clkr = { 2709 .enable_reg = 0x3184, 2710 .enable_mask = BIT(0), 2711 .hw.init = &(struct clk_init_data){ 2712 .name = "camss_csi2_clk", 2713 .parent_names = (const char *[]){ "csi2_clk_src" }, 2714 .num_parents = 1, 2715 .flags = CLK_SET_RATE_PARENT, 2716 .ops = &clk_branch2_ops, 2717 }, 2718 }, 2719 }; 2720 2721 static struct clk_branch camss_csi2_ahb_clk = { 2722 .halt_reg = 0x3188, 2723 .clkr = { 2724 .enable_reg = 0x3188, 2725 .enable_mask = BIT(0), 2726 .hw.init = &(struct clk_init_data){ 2727 .name = "camss_csi2_ahb_clk", 2728 .parent_names = (const char *[]){ "ahb_clk_src" }, 2729 .num_parents = 1, 2730 .flags = CLK_SET_RATE_PARENT, 2731 .ops = &clk_branch2_ops, 2732 }, 2733 }, 2734 }; 2735 2736 static struct clk_branch camss_csi2phy_clk = { 2737 .halt_reg = 0x3194, 2738 .clkr = { 2739 .enable_reg = 0x3194, 2740 .enable_mask = BIT(0), 2741 .hw.init = &(struct clk_init_data){ 2742 .name = "camss_csi2phy_clk", 2743 .parent_names = (const char *[]){ "csi2_clk_src" }, 2744 .num_parents = 1, 2745 .flags = CLK_SET_RATE_PARENT, 2746 .ops = &clk_branch2_ops, 2747 }, 2748 }, 2749 }; 2750 2751 static struct clk_branch camss_csi2rdi_clk = { 2752 .halt_reg = 0x31a4, 2753 .clkr = { 2754 .enable_reg = 0x31a4, 2755 .enable_mask = BIT(0), 2756 .hw.init = &(struct clk_init_data){ 2757 .name = "camss_csi2rdi_clk", 2758 .parent_names = (const char *[]){ "csi2_clk_src" }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch camss_csi2pix_clk = { 2767 .halt_reg = 0x31b4, 2768 .clkr = { 2769 .enable_reg = 0x31b4, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(struct clk_init_data){ 2772 .name = "camss_csi2pix_clk", 2773 .parent_names = (const char *[]){ "csi2_clk_src" }, 2774 .num_parents = 1, 2775 .flags = CLK_SET_RATE_PARENT, 2776 .ops = &clk_branch2_ops, 2777 }, 2778 }, 2779 }; 2780 2781 static struct clk_branch camss_csi3_clk = { 2782 .halt_reg = 0x31e4, 2783 .clkr = { 2784 .enable_reg = 0x31e4, 2785 .enable_mask = BIT(0), 2786 .hw.init = &(struct clk_init_data){ 2787 .name = "camss_csi3_clk", 2788 .parent_names = (const char *[]){ "csi3_clk_src" }, 2789 .num_parents = 1, 2790 .flags = CLK_SET_RATE_PARENT, 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch camss_csi3_ahb_clk = { 2797 .halt_reg = 0x31e8, 2798 .clkr = { 2799 .enable_reg = 0x31e8, 2800 .enable_mask = BIT(0), 2801 .hw.init = &(struct clk_init_data){ 2802 .name = "camss_csi3_ahb_clk", 2803 .parent_names = (const char *[]){ "ahb_clk_src" }, 2804 .num_parents = 1, 2805 .flags = CLK_SET_RATE_PARENT, 2806 .ops = &clk_branch2_ops, 2807 }, 2808 }, 2809 }; 2810 2811 static struct clk_branch camss_csi3phy_clk = { 2812 .halt_reg = 0x31f4, 2813 .clkr = { 2814 .enable_reg = 0x31f4, 2815 .enable_mask = BIT(0), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "camss_csi3phy_clk", 2818 .parent_names = (const char *[]){ "csi3_clk_src" }, 2819 .num_parents = 1, 2820 .flags = CLK_SET_RATE_PARENT, 2821 .ops = &clk_branch2_ops, 2822 }, 2823 }, 2824 }; 2825 2826 static struct clk_branch camss_csi3rdi_clk = { 2827 .halt_reg = 0x3204, 2828 .clkr = { 2829 .enable_reg = 0x3204, 2830 .enable_mask = BIT(0), 2831 .hw.init = &(struct clk_init_data){ 2832 .name = "camss_csi3rdi_clk", 2833 .parent_names = (const char *[]){ "csi3_clk_src" }, 2834 .num_parents = 1, 2835 .flags = CLK_SET_RATE_PARENT, 2836 .ops = &clk_branch2_ops, 2837 }, 2838 }, 2839 }; 2840 2841 static struct clk_branch camss_csi3pix_clk = { 2842 .halt_reg = 0x3214, 2843 .clkr = { 2844 .enable_reg = 0x3214, 2845 .enable_mask = BIT(0), 2846 .hw.init = &(struct clk_init_data){ 2847 .name = "camss_csi3pix_clk", 2848 .parent_names = (const char *[]){ "csi3_clk_src" }, 2849 .num_parents = 1, 2850 .flags = CLK_SET_RATE_PARENT, 2851 .ops = &clk_branch2_ops, 2852 }, 2853 }, 2854 }; 2855 2856 static struct clk_branch camss_ispif_ahb_clk = { 2857 .halt_reg = 0x3224, 2858 .clkr = { 2859 .enable_reg = 0x3224, 2860 .enable_mask = BIT(0), 2861 .hw.init = &(struct clk_init_data){ 2862 .name = "camss_ispif_ahb_clk", 2863 .parent_names = (const char *[]){ "ahb_clk_src" }, 2864 .num_parents = 1, 2865 .flags = CLK_SET_RATE_PARENT, 2866 .ops = &clk_branch2_ops, 2867 }, 2868 }, 2869 }; 2870 2871 static struct clk_branch fd_core_clk = { 2872 .halt_reg = 0x3b68, 2873 .clkr = { 2874 .enable_reg = 0x3b68, 2875 .enable_mask = BIT(0), 2876 .hw.init = &(struct clk_init_data){ 2877 .name = "fd_core_clk", 2878 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2879 .num_parents = 1, 2880 .flags = CLK_SET_RATE_PARENT, 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch fd_core_uar_clk = { 2887 .halt_reg = 0x3b6c, 2888 .clkr = { 2889 .enable_reg = 0x3b6c, 2890 .enable_mask = BIT(0), 2891 .hw.init = &(struct clk_init_data){ 2892 .name = "fd_core_uar_clk", 2893 .parent_names = (const char *[]){ "fd_core_clk_src" }, 2894 .num_parents = 1, 2895 .flags = CLK_SET_RATE_PARENT, 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_branch fd_ahb_clk = { 2902 .halt_reg = 0x3ba74, 2903 .clkr = { 2904 .enable_reg = 0x3ba74, 2905 .enable_mask = BIT(0), 2906 .hw.init = &(struct clk_init_data){ 2907 .name = "fd_ahb_clk", 2908 .parent_names = (const char *[]){ "ahb_clk_src" }, 2909 .num_parents = 1, 2910 .flags = CLK_SET_RATE_PARENT, 2911 .ops = &clk_branch2_ops, 2912 }, 2913 }, 2914 }; 2915 2916 static struct clk_hw *mmcc_msm8996_hws[] = { 2917 &gpll0_div.hw, 2918 }; 2919 2920 static struct clk_regmap *mmcc_msm8996_clocks[] = { 2921 [MMPLL0_EARLY] = &mmpll0_early.clkr, 2922 [MMPLL0_PLL] = &mmpll0.clkr, 2923 [MMPLL1_EARLY] = &mmpll1_early.clkr, 2924 [MMPLL1_PLL] = &mmpll1.clkr, 2925 [MMPLL2_EARLY] = &mmpll2_early.clkr, 2926 [MMPLL2_PLL] = &mmpll2.clkr, 2927 [MMPLL3_EARLY] = &mmpll3_early.clkr, 2928 [MMPLL3_PLL] = &mmpll3.clkr, 2929 [MMPLL4_EARLY] = &mmpll4_early.clkr, 2930 [MMPLL4_PLL] = &mmpll4.clkr, 2931 [MMPLL5_EARLY] = &mmpll5_early.clkr, 2932 [MMPLL5_PLL] = &mmpll5.clkr, 2933 [MMPLL8_EARLY] = &mmpll8_early.clkr, 2934 [MMPLL8_PLL] = &mmpll8.clkr, 2935 [MMPLL9_EARLY] = &mmpll9_early.clkr, 2936 [MMPLL9_PLL] = &mmpll9.clkr, 2937 [AHB_CLK_SRC] = &ahb_clk_src.clkr, 2938 [AXI_CLK_SRC] = &axi_clk_src.clkr, 2939 [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 2940 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2941 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 2942 [ISENSE_CLK_SRC] = &isense_clk_src.clkr, 2943 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 2944 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 2945 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 2946 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 2947 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2948 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2949 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2950 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2951 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2952 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2953 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2954 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2955 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2956 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2957 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2958 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2959 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2960 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2961 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2962 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2963 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2964 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2965 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2966 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2967 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr, 2968 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr, 2969 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr, 2970 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2971 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 2972 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr, 2973 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2974 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2975 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2976 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2977 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2978 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2979 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2980 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 2981 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr, 2982 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, 2983 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 2984 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, 2985 [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr, 2986 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, 2987 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, 2988 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, 2989 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr, 2990 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr, 2991 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr, 2992 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr, 2993 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr, 2994 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr, 2995 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr, 2996 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr, 2997 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr, 2998 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr, 2999 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr, 3000 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr, 3001 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr, 3002 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, 3003 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, 3004 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, 3005 [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr, 3006 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, 3007 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, 3008 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, 3009 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr, 3010 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr, 3011 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 3012 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 3013 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3014 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3015 [VIDEO_CORE_CLK] = &video_core_clk.clkr, 3016 [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 3017 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 3018 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 3019 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 3020 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 3021 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3022 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3023 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3024 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3025 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3026 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3027 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3028 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3029 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3030 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3031 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3032 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3033 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3034 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 3035 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 3036 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 3037 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 3038 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 3039 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 3040 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 3041 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 3042 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 3043 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 3044 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 3045 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 3046 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 3047 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 3048 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr, 3049 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr, 3050 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr, 3051 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 3052 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr, 3053 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr, 3054 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 3055 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 3056 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr, 3057 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr, 3058 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 3059 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 3060 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 3061 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 3062 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 3063 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 3064 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 3065 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 3066 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 3067 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 3068 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 3069 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 3070 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 3071 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 3072 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 3073 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 3074 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 3075 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 3076 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 3077 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 3078 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 3079 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 3080 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 3081 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 3082 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 3083 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 3084 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 3085 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 3086 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 3087 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 3088 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 3089 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 3090 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 3091 [FD_CORE_CLK] = &fd_core_clk.clkr, 3092 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 3093 [FD_AHB_CLK] = &fd_ahb_clk.clkr, 3094 }; 3095 3096 static const struct qcom_reset_map mmcc_msm8996_resets[] = { 3097 [MMAGICAHB_BCR] = { 0x5020 }, 3098 [MMAGIC_CFG_BCR] = { 0x5050 }, 3099 [MISC_BCR] = { 0x5010 }, 3100 [BTO_BCR] = { 0x5030 }, 3101 [MMAGICAXI_BCR] = { 0x5060 }, 3102 [MMAGICMAXI_BCR] = { 0x5070 }, 3103 [DSA_BCR] = { 0x50a0 }, 3104 [MMAGIC_CAMSS_BCR] = { 0x3c40 }, 3105 [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 3106 [SMMU_VFE_BCR] = { 0x3c00 }, 3107 [SMMU_CPP_BCR] = { 0x3c10 }, 3108 [SMMU_JPEG_BCR] = { 0x3c20 }, 3109 [MMAGIC_MDSS_BCR] = { 0x2470 }, 3110 [THROTTLE_MDSS_BCR] = { 0x2460 }, 3111 [SMMU_ROT_BCR] = { 0x2440 }, 3112 [SMMU_MDP_BCR] = { 0x2450 }, 3113 [MMAGIC_VIDEO_BCR] = { 0x1190 }, 3114 [THROTTLE_VIDEO_BCR] = { 0x1180 }, 3115 [SMMU_VIDEO_BCR] = { 0x1170 }, 3116 [MMAGIC_BIMC_BCR] = { 0x5290 }, 3117 [GPU_GX_BCR] = { 0x4020 }, 3118 [GPU_BCR] = { 0x4030 }, 3119 [GPU_AON_BCR] = { 0x4040 }, 3120 [VMEM_BCR] = { 0x1200 }, 3121 [MMSS_RBCPR_BCR] = { 0x4080 }, 3122 [VIDEO_BCR] = { 0x1020 }, 3123 [MDSS_BCR] = { 0x2300 }, 3124 [CAMSS_TOP_BCR] = { 0x3480 }, 3125 [CAMSS_AHB_BCR] = { 0x3488 }, 3126 [CAMSS_MICRO_BCR] = { 0x3490 }, 3127 [CAMSS_CCI_BCR] = { 0x3340 }, 3128 [CAMSS_PHY0_BCR] = { 0x3020 }, 3129 [CAMSS_PHY1_BCR] = { 0x3050 }, 3130 [CAMSS_PHY2_BCR] = { 0x3080 }, 3131 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 }, 3132 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 }, 3133 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 }, 3134 [CAMSS_JPEG_BCR] = { 0x35a0 }, 3135 [CAMSS_VFE_BCR] = { 0x36a0 }, 3136 [CAMSS_VFE0_BCR] = { 0x3660 }, 3137 [CAMSS_VFE1_BCR] = { 0x3670 }, 3138 [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 3139 [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 3140 [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 3141 [CAMSS_CPP_BCR] = { 0x36d0 }, 3142 [CAMSS_CSI0_BCR] = { 0x30b0 }, 3143 [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 3144 [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 3145 [CAMSS_CSI1_BCR] = { 0x3120 }, 3146 [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 3147 [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 3148 [CAMSS_CSI2_BCR] = { 0x3180 }, 3149 [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 3150 [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 3151 [CAMSS_CSI3_BCR] = { 0x31e0 }, 3152 [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 3153 [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 3154 [CAMSS_ISPIF_BCR] = { 0x3220 }, 3155 [FD_BCR] = { 0x3b60 }, 3156 [MMSS_SPDM_RM_BCR] = { 0x300 }, 3157 }; 3158 3159 static const struct regmap_config mmcc_msm8996_regmap_config = { 3160 .reg_bits = 32, 3161 .reg_stride = 4, 3162 .val_bits = 32, 3163 .max_register = 0xb008, 3164 .fast_io = true, 3165 }; 3166 3167 static const struct qcom_cc_desc mmcc_msm8996_desc = { 3168 .config = &mmcc_msm8996_regmap_config, 3169 .clks = mmcc_msm8996_clocks, 3170 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), 3171 .resets = mmcc_msm8996_resets, 3172 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), 3173 }; 3174 3175 static const struct of_device_id mmcc_msm8996_match_table[] = { 3176 { .compatible = "qcom,mmcc-msm8996" }, 3177 { } 3178 }; 3179 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); 3180 3181 static int mmcc_msm8996_probe(struct platform_device *pdev) 3182 { 3183 struct clk *clk; 3184 struct device *dev = &pdev->dev; 3185 int i; 3186 struct regmap *regmap; 3187 3188 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); 3189 if (IS_ERR(regmap)) 3190 return PTR_ERR(regmap); 3191 3192 /* Disable the AHB DCD */ 3193 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); 3194 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ 3195 regmap_update_bits(regmap, 0x5054, BIT(15), 0); 3196 3197 for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) { 3198 clk = devm_clk_register(dev, mmcc_msm8996_hws[i]); 3199 if (IS_ERR(clk)) 3200 return PTR_ERR(clk); 3201 } 3202 3203 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); 3204 } 3205 3206 static struct platform_driver mmcc_msm8996_driver = { 3207 .probe = mmcc_msm8996_probe, 3208 .driver = { 3209 .name = "mmcc-msm8996", 3210 .of_match_table = mmcc_msm8996_match_table, 3211 }, 3212 }; 3213 module_platform_driver(mmcc_msm8996_driver); 3214 3215 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); 3216 MODULE_LICENSE("GPL v2"); 3217 MODULE_ALIAS("platform:mmcc-msm8996"); 3218