xref: /linux/drivers/clk/qcom/mmcc-msm8960.c (revision d91517839e5d95adc0cf4b28caa7af62a71de526)
1 /*
2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/regmap.h>
24 #include <linux/reset-controller.h>
25 
26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28 
29 #include "clk-regmap.h"
30 #include "clk-pll.h"
31 #include "clk-rcg.h"
32 #include "clk-branch.h"
33 #include "reset.h"
34 
35 #define P_PXO	0
36 #define P_PLL8	1
37 #define P_PLL2	2
38 #define P_PLL3	3
39 
40 static u8 mmcc_pxo_pll8_pll2_map[] = {
41 	[P_PXO]		= 0,
42 	[P_PLL8]	= 2,
43 	[P_PLL2]	= 1,
44 };
45 
46 static const char *mmcc_pxo_pll8_pll2[] = {
47 	"pxo",
48 	"pll8_vote",
49 	"pll2",
50 };
51 
52 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
53 	[P_PXO]		= 0,
54 	[P_PLL8]	= 2,
55 	[P_PLL2]	= 1,
56 	[P_PLL3]	= 3,
57 };
58 
59 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
60 	"pxo",
61 	"pll2",
62 	"pll8_vote",
63 	"pll3",
64 };
65 
66 static struct clk_pll pll2 = {
67 	.l_reg = 0x320,
68 	.m_reg = 0x324,
69 	.n_reg = 0x328,
70 	.config_reg = 0x32c,
71 	.mode_reg = 0x31c,
72 	.status_reg = 0x334,
73 	.status_bit = 16,
74 	.clkr.hw.init = &(struct clk_init_data){
75 		.name = "pll2",
76 		.parent_names = (const char *[]){ "pxo" },
77 		.num_parents = 1,
78 		.ops = &clk_pll_ops,
79 	},
80 };
81 
82 static struct freq_tbl clk_tbl_cam[] = {
83 	{   6000000, P_PLL8, 4, 1, 16 },
84 	{   8000000, P_PLL8, 4, 1, 12 },
85 	{  12000000, P_PLL8, 4, 1,  8 },
86 	{  16000000, P_PLL8, 4, 1,  6 },
87 	{  19200000, P_PLL8, 4, 1,  5 },
88 	{  24000000, P_PLL8, 4, 1,  4 },
89 	{  32000000, P_PLL8, 4, 1,  3 },
90 	{  48000000, P_PLL8, 4, 1,  2 },
91 	{  64000000, P_PLL8, 3, 1,  2 },
92 	{  96000000, P_PLL8, 4, 0,  0 },
93 	{ 128000000, P_PLL8, 3, 0,  0 },
94 	{ }
95 };
96 
97 static struct clk_rcg camclk0_src = {
98 	.ns_reg = 0x0148,
99 	.md_reg = 0x0144,
100 	.mn = {
101 		.mnctr_en_bit = 5,
102 		.mnctr_reset_bit = 8,
103 		.reset_in_cc = true,
104 		.mnctr_mode_shift = 6,
105 		.n_val_shift = 24,
106 		.m_val_shift = 8,
107 		.width = 8,
108 	},
109 	.p = {
110 		.pre_div_shift = 14,
111 		.pre_div_width = 2,
112 	},
113 	.s = {
114 		.src_sel_shift = 0,
115 		.parent_map = mmcc_pxo_pll8_pll2_map,
116 	},
117 	.freq_tbl = clk_tbl_cam,
118 	.clkr = {
119 		.enable_reg = 0x0140,
120 		.enable_mask = BIT(2),
121 		.hw.init = &(struct clk_init_data){
122 			.name = "camclk0_src",
123 			.parent_names = mmcc_pxo_pll8_pll2,
124 			.num_parents = 3,
125 			.ops = &clk_rcg_ops,
126 		},
127 	},
128 };
129 
130 static struct clk_branch camclk0_clk = {
131 	.halt_reg = 0x01e8,
132 	.halt_bit = 15,
133 	.clkr = {
134 		.enable_reg = 0x0140,
135 		.enable_mask = BIT(0),
136 		.hw.init = &(struct clk_init_data){
137 			.name = "camclk0_clk",
138 			.parent_names = (const char *[]){ "camclk0_src" },
139 			.num_parents = 1,
140 			.ops = &clk_branch_ops,
141 		},
142 	},
143 
144 };
145 
146 static struct clk_rcg camclk1_src = {
147 	.ns_reg = 0x015c,
148 	.md_reg = 0x0158,
149 	.mn = {
150 		.mnctr_en_bit = 5,
151 		.mnctr_reset_bit = 8,
152 		.reset_in_cc = true,
153 		.mnctr_mode_shift = 6,
154 		.n_val_shift = 24,
155 		.m_val_shift = 8,
156 		.width = 8,
157 	},
158 	.p = {
159 		.pre_div_shift = 14,
160 		.pre_div_width = 2,
161 	},
162 	.s = {
163 		.src_sel_shift = 0,
164 		.parent_map = mmcc_pxo_pll8_pll2_map,
165 	},
166 	.freq_tbl = clk_tbl_cam,
167 	.clkr = {
168 		.enable_reg = 0x0154,
169 		.enable_mask = BIT(2),
170 		.hw.init = &(struct clk_init_data){
171 			.name = "camclk1_src",
172 			.parent_names = mmcc_pxo_pll8_pll2,
173 			.num_parents = 3,
174 			.ops = &clk_rcg_ops,
175 		},
176 	},
177 };
178 
179 static struct clk_branch camclk1_clk = {
180 	.halt_reg = 0x01e8,
181 	.halt_bit = 16,
182 	.clkr = {
183 		.enable_reg = 0x0154,
184 		.enable_mask = BIT(0),
185 		.hw.init = &(struct clk_init_data){
186 			.name = "camclk1_clk",
187 			.parent_names = (const char *[]){ "camclk1_src" },
188 			.num_parents = 1,
189 			.ops = &clk_branch_ops,
190 		},
191 	},
192 
193 };
194 
195 static struct clk_rcg camclk2_src = {
196 	.ns_reg = 0x0228,
197 	.md_reg = 0x0224,
198 	.mn = {
199 		.mnctr_en_bit = 5,
200 		.mnctr_reset_bit = 8,
201 		.reset_in_cc = true,
202 		.mnctr_mode_shift = 6,
203 		.n_val_shift = 24,
204 		.m_val_shift = 8,
205 		.width = 8,
206 	},
207 	.p = {
208 		.pre_div_shift = 14,
209 		.pre_div_width = 2,
210 	},
211 	.s = {
212 		.src_sel_shift = 0,
213 		.parent_map = mmcc_pxo_pll8_pll2_map,
214 	},
215 	.freq_tbl = clk_tbl_cam,
216 	.clkr = {
217 		.enable_reg = 0x0220,
218 		.enable_mask = BIT(2),
219 		.hw.init = &(struct clk_init_data){
220 			.name = "camclk2_src",
221 			.parent_names = mmcc_pxo_pll8_pll2,
222 			.num_parents = 3,
223 			.ops = &clk_rcg_ops,
224 		},
225 	},
226 };
227 
228 static struct clk_branch camclk2_clk = {
229 	.halt_reg = 0x01e8,
230 	.halt_bit = 16,
231 	.clkr = {
232 		.enable_reg = 0x0220,
233 		.enable_mask = BIT(0),
234 		.hw.init = &(struct clk_init_data){
235 			.name = "camclk2_clk",
236 			.parent_names = (const char *[]){ "camclk2_src" },
237 			.num_parents = 1,
238 			.ops = &clk_branch_ops,
239 		},
240 	},
241 
242 };
243 
244 static struct freq_tbl clk_tbl_csi[] = {
245 	{  27000000, P_PXO,  1, 0, 0 },
246 	{  85330000, P_PLL8, 1, 2, 9 },
247 	{ 177780000, P_PLL2, 1, 2, 9 },
248 	{ }
249 };
250 
251 static struct clk_rcg csi0_src = {
252 	.ns_reg = 0x0048,
253 	.md_reg	= 0x0044,
254 	.mn = {
255 		.mnctr_en_bit = 5,
256 		.mnctr_reset_bit = 7,
257 		.mnctr_mode_shift = 6,
258 		.n_val_shift = 24,
259 		.m_val_shift = 8,
260 		.width = 8,
261 	},
262 	.p = {
263 		.pre_div_shift = 14,
264 		.pre_div_width = 2,
265 	},
266 	.s = {
267 		.src_sel_shift = 0,
268 		.parent_map = mmcc_pxo_pll8_pll2_map,
269 	},
270 	.freq_tbl = clk_tbl_csi,
271 	.clkr = {
272 		.enable_reg = 0x0040,
273 		.enable_mask = BIT(2),
274 		.hw.init = &(struct clk_init_data){
275 			.name = "csi0_src",
276 			.parent_names = mmcc_pxo_pll8_pll2,
277 			.num_parents = 3,
278 			.ops = &clk_rcg_ops,
279 		},
280 	},
281 };
282 
283 static struct clk_branch csi0_clk = {
284 	.halt_reg = 0x01cc,
285 	.halt_bit = 13,
286 	.clkr = {
287 		.enable_reg = 0x0040,
288 		.enable_mask = BIT(0),
289 		.hw.init = &(struct clk_init_data){
290 			.parent_names = (const char *[]){ "csi0_src" },
291 			.num_parents = 1,
292 			.name = "csi0_clk",
293 			.ops = &clk_branch_ops,
294 			.flags = CLK_SET_RATE_PARENT,
295 		},
296 	},
297 };
298 
299 static struct clk_branch csi0_phy_clk = {
300 	.halt_reg = 0x01e8,
301 	.halt_bit = 9,
302 	.clkr = {
303 		.enable_reg = 0x0040,
304 		.enable_mask = BIT(8),
305 		.hw.init = &(struct clk_init_data){
306 			.parent_names = (const char *[]){ "csi0_src" },
307 			.num_parents = 1,
308 			.name = "csi0_phy_clk",
309 			.ops = &clk_branch_ops,
310 			.flags = CLK_SET_RATE_PARENT,
311 		},
312 	},
313 };
314 
315 static struct clk_rcg csi1_src = {
316 	.ns_reg = 0x0010,
317 	.md_reg	= 0x0028,
318 	.mn = {
319 		.mnctr_en_bit = 5,
320 		.mnctr_reset_bit = 7,
321 		.mnctr_mode_shift = 6,
322 		.n_val_shift = 24,
323 		.m_val_shift = 8,
324 		.width = 8,
325 	},
326 	.p = {
327 		.pre_div_shift = 14,
328 		.pre_div_width = 2,
329 	},
330 	.s = {
331 		.src_sel_shift = 0,
332 		.parent_map = mmcc_pxo_pll8_pll2_map,
333 	},
334 	.freq_tbl = clk_tbl_csi,
335 	.clkr = {
336 		.enable_reg = 0x0024,
337 		.enable_mask = BIT(2),
338 		.hw.init = &(struct clk_init_data){
339 			.name = "csi1_src",
340 			.parent_names = mmcc_pxo_pll8_pll2,
341 			.num_parents = 3,
342 			.ops = &clk_rcg_ops,
343 		},
344 	},
345 };
346 
347 static struct clk_branch csi1_clk = {
348 	.halt_reg = 0x01cc,
349 	.halt_bit = 14,
350 	.clkr = {
351 		.enable_reg = 0x0024,
352 		.enable_mask = BIT(0),
353 		.hw.init = &(struct clk_init_data){
354 			.parent_names = (const char *[]){ "csi1_src" },
355 			.num_parents = 1,
356 			.name = "csi1_clk",
357 			.ops = &clk_branch_ops,
358 			.flags = CLK_SET_RATE_PARENT,
359 		},
360 	},
361 };
362 
363 static struct clk_branch csi1_phy_clk = {
364 	.halt_reg = 0x01e8,
365 	.halt_bit = 10,
366 	.clkr = {
367 		.enable_reg = 0x0024,
368 		.enable_mask = BIT(8),
369 		.hw.init = &(struct clk_init_data){
370 			.parent_names = (const char *[]){ "csi1_src" },
371 			.num_parents = 1,
372 			.name = "csi1_phy_clk",
373 			.ops = &clk_branch_ops,
374 			.flags = CLK_SET_RATE_PARENT,
375 		},
376 	},
377 };
378 
379 static struct clk_rcg csi2_src = {
380 	.ns_reg = 0x0234,
381 	.md_reg = 0x022c,
382 	.mn = {
383 		.mnctr_en_bit = 5,
384 		.mnctr_reset_bit = 7,
385 		.mnctr_mode_shift = 6,
386 		.n_val_shift = 24,
387 		.m_val_shift = 8,
388 		.width = 8,
389 	},
390 	.p = {
391 		.pre_div_shift = 14,
392 		.pre_div_width = 2,
393 	},
394 	.s = {
395 		.src_sel_shift = 0,
396 		.parent_map = mmcc_pxo_pll8_pll2_map,
397 	},
398 	.freq_tbl = clk_tbl_csi,
399 	.clkr = {
400 		.enable_reg = 0x022c,
401 		.enable_mask = BIT(2),
402 		.hw.init = &(struct clk_init_data){
403 			.name = "csi2_src",
404 			.parent_names = mmcc_pxo_pll8_pll2,
405 			.num_parents = 3,
406 			.ops = &clk_rcg_ops,
407 		},
408 	},
409 };
410 
411 static struct clk_branch csi2_clk = {
412 	.halt_reg = 0x01cc,
413 	.halt_bit = 29,
414 	.clkr = {
415 		.enable_reg = 0x022c,
416 		.enable_mask = BIT(0),
417 		.hw.init = &(struct clk_init_data){
418 			.parent_names = (const char *[]){ "csi2_src" },
419 			.num_parents = 1,
420 			.name = "csi2_clk",
421 			.ops = &clk_branch_ops,
422 			.flags = CLK_SET_RATE_PARENT,
423 		},
424 	},
425 };
426 
427 static struct clk_branch csi2_phy_clk = {
428 	.halt_reg = 0x01e8,
429 	.halt_bit = 29,
430 	.clkr = {
431 		.enable_reg = 0x022c,
432 		.enable_mask = BIT(8),
433 		.hw.init = &(struct clk_init_data){
434 			.parent_names = (const char *[]){ "csi2_src" },
435 			.num_parents = 1,
436 			.name = "csi2_phy_clk",
437 			.ops = &clk_branch_ops,
438 			.flags = CLK_SET_RATE_PARENT,
439 		},
440 	},
441 };
442 
443 struct clk_pix_rdi {
444 	u32 s_reg;
445 	u32 s_mask;
446 	u32 s2_reg;
447 	u32 s2_mask;
448 	struct clk_regmap clkr;
449 };
450 
451 #define to_clk_pix_rdi(_hw) \
452 	container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
453 
454 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
455 {
456 	int i;
457 	int ret = 0;
458 	u32 val;
459 	struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
460 	struct clk *clk = hw->clk;
461 	int num_parents = __clk_get_num_parents(hw->clk);
462 
463 	/*
464 	 * These clocks select three inputs via two muxes. One mux selects
465 	 * between csi0 and csi1 and the second mux selects between that mux's
466 	 * output and csi2. The source and destination selections for each
467 	 * mux must be clocking for the switch to succeed so just turn on
468 	 * all three sources because it's easier than figuring out what source
469 	 * needs to be on at what time.
470 	 */
471 	for (i = 0; i < num_parents; i++) {
472 		ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
473 		if (ret)
474 			goto err;
475 	}
476 
477 	if (index == 2)
478 		val = rdi->s2_mask;
479 	else
480 		val = 0;
481 	regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
482 	/*
483 	 * Wait at least 6 cycles of slowest clock
484 	 * for the glitch-free MUX to fully switch sources.
485 	 */
486 	udelay(1);
487 
488 	if (index == 1)
489 		val = rdi->s_mask;
490 	else
491 		val = 0;
492 	regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
493 	/*
494 	 * Wait at least 6 cycles of slowest clock
495 	 * for the glitch-free MUX to fully switch sources.
496 	 */
497 	udelay(1);
498 
499 err:
500 	for (i--; i >= 0; i--)
501 		clk_disable_unprepare(clk_get_parent_by_index(clk, i));
502 
503 	return ret;
504 }
505 
506 static u8 pix_rdi_get_parent(struct clk_hw *hw)
507 {
508 	u32 val;
509 	struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
510 
511 
512 	regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
513 	if (val & rdi->s2_mask)
514 		return 2;
515 
516 	regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
517 	if (val & rdi->s_mask)
518 		return 1;
519 
520 	return 0;
521 }
522 
523 static const struct clk_ops clk_ops_pix_rdi = {
524 	.enable = clk_enable_regmap,
525 	.disable = clk_disable_regmap,
526 	.set_parent = pix_rdi_set_parent,
527 	.get_parent = pix_rdi_get_parent,
528 	.determine_rate = __clk_mux_determine_rate,
529 };
530 
531 static const char *pix_rdi_parents[] = {
532 	"csi0_clk",
533 	"csi1_clk",
534 	"csi2_clk",
535 };
536 
537 static struct clk_pix_rdi csi_pix_clk = {
538 	.s_reg = 0x0058,
539 	.s_mask = BIT(25),
540 	.s2_reg = 0x0238,
541 	.s2_mask = BIT(13),
542 	.clkr = {
543 		.enable_reg = 0x0058,
544 		.enable_mask = BIT(26),
545 		.hw.init = &(struct clk_init_data){
546 			.name = "csi_pix_clk",
547 			.parent_names = pix_rdi_parents,
548 			.num_parents = 3,
549 			.ops = &clk_ops_pix_rdi,
550 		},
551 	},
552 };
553 
554 static struct clk_pix_rdi csi_pix1_clk = {
555 	.s_reg = 0x0238,
556 	.s_mask = BIT(8),
557 	.s2_reg = 0x0238,
558 	.s2_mask = BIT(9),
559 	.clkr = {
560 		.enable_reg = 0x0238,
561 		.enable_mask = BIT(10),
562 		.hw.init = &(struct clk_init_data){
563 			.name = "csi_pix1_clk",
564 			.parent_names = pix_rdi_parents,
565 			.num_parents = 3,
566 			.ops = &clk_ops_pix_rdi,
567 		},
568 	},
569 };
570 
571 static struct clk_pix_rdi csi_rdi_clk = {
572 	.s_reg = 0x0058,
573 	.s_mask = BIT(12),
574 	.s2_reg = 0x0238,
575 	.s2_mask = BIT(12),
576 	.clkr = {
577 		.enable_reg = 0x0058,
578 		.enable_mask = BIT(13),
579 		.hw.init = &(struct clk_init_data){
580 			.name = "csi_rdi_clk",
581 			.parent_names = pix_rdi_parents,
582 			.num_parents = 3,
583 			.ops = &clk_ops_pix_rdi,
584 		},
585 	},
586 };
587 
588 static struct clk_pix_rdi csi_rdi1_clk = {
589 	.s_reg = 0x0238,
590 	.s_mask = BIT(0),
591 	.s2_reg = 0x0238,
592 	.s2_mask = BIT(1),
593 	.clkr = {
594 		.enable_reg = 0x0238,
595 		.enable_mask = BIT(2),
596 		.hw.init = &(struct clk_init_data){
597 			.name = "csi_rdi1_clk",
598 			.parent_names = pix_rdi_parents,
599 			.num_parents = 3,
600 			.ops = &clk_ops_pix_rdi,
601 		},
602 	},
603 };
604 
605 static struct clk_pix_rdi csi_rdi2_clk = {
606 	.s_reg = 0x0238,
607 	.s_mask = BIT(4),
608 	.s2_reg = 0x0238,
609 	.s2_mask = BIT(5),
610 	.clkr = {
611 		.enable_reg = 0x0238,
612 		.enable_mask = BIT(6),
613 		.hw.init = &(struct clk_init_data){
614 			.name = "csi_rdi2_clk",
615 			.parent_names = pix_rdi_parents,
616 			.num_parents = 3,
617 			.ops = &clk_ops_pix_rdi,
618 		},
619 	},
620 };
621 
622 static struct freq_tbl clk_tbl_csiphytimer[] = {
623 	{  85330000, P_PLL8, 1, 2, 9 },
624 	{ 177780000, P_PLL2, 1, 2, 9 },
625 	{ }
626 };
627 
628 static struct clk_rcg csiphytimer_src = {
629 	.ns_reg = 0x0168,
630 	.md_reg = 0x0164,
631 	.mn = {
632 		.mnctr_en_bit = 5,
633 		.mnctr_reset_bit = 8,
634 		.reset_in_cc = true,
635 		.mnctr_mode_shift = 6,
636 		.n_val_shift = 24,
637 		.m_val_shift = 8,
638 		.width = 8,
639 	},
640 	.p = {
641 		.pre_div_shift = 14,
642 		.pre_div_width = 2,
643 	},
644 	.s = {
645 		.src_sel_shift = 0,
646 		.parent_map = mmcc_pxo_pll8_pll2_map,
647 	},
648 	.freq_tbl = clk_tbl_csiphytimer,
649 	.clkr = {
650 		.enable_reg = 0x0160,
651 		.enable_mask = BIT(2),
652 		.hw.init = &(struct clk_init_data){
653 			.name = "csiphytimer_src",
654 			.parent_names = mmcc_pxo_pll8_pll2,
655 			.num_parents = 3,
656 			.ops = &clk_rcg_ops,
657 		},
658 	},
659 };
660 
661 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
662 
663 static struct clk_branch csiphy0_timer_clk = {
664 	.halt_reg = 0x01e8,
665 	.halt_bit = 17,
666 	.clkr = {
667 		.enable_reg = 0x0160,
668 		.enable_mask = BIT(0),
669 		.hw.init = &(struct clk_init_data){
670 			.parent_names = csixphy_timer_src,
671 			.num_parents = 1,
672 			.name = "csiphy0_timer_clk",
673 			.ops = &clk_branch_ops,
674 			.flags = CLK_SET_RATE_PARENT,
675 		},
676 	},
677 };
678 
679 static struct clk_branch csiphy1_timer_clk = {
680 	.halt_reg = 0x01e8,
681 	.halt_bit = 18,
682 	.clkr = {
683 		.enable_reg = 0x0160,
684 		.enable_mask = BIT(9),
685 		.hw.init = &(struct clk_init_data){
686 			.parent_names = csixphy_timer_src,
687 			.num_parents = 1,
688 			.name = "csiphy1_timer_clk",
689 			.ops = &clk_branch_ops,
690 			.flags = CLK_SET_RATE_PARENT,
691 		},
692 	},
693 };
694 
695 static struct clk_branch csiphy2_timer_clk = {
696 	.halt_reg = 0x01e8,
697 	.halt_bit = 30,
698 	.clkr = {
699 		.enable_reg = 0x0160,
700 		.enable_mask = BIT(11),
701 		.hw.init = &(struct clk_init_data){
702 			.parent_names = csixphy_timer_src,
703 			.num_parents = 1,
704 			.name = "csiphy2_timer_clk",
705 			.ops = &clk_branch_ops,
706 			.flags = CLK_SET_RATE_PARENT,
707 		},
708 	},
709 };
710 
711 static struct freq_tbl clk_tbl_gfx2d[] = {
712 	{  27000000, P_PXO,  1,  0 },
713 	{  48000000, P_PLL8, 1,  8 },
714 	{  54857000, P_PLL8, 1,  7 },
715 	{  64000000, P_PLL8, 1,  6 },
716 	{  76800000, P_PLL8, 1,  5 },
717 	{  96000000, P_PLL8, 1,  4 },
718 	{ 128000000, P_PLL8, 1,  3 },
719 	{ 145455000, P_PLL2, 2, 11 },
720 	{ 160000000, P_PLL2, 1,  5 },
721 	{ 177778000, P_PLL2, 2,  9 },
722 	{ 200000000, P_PLL2, 1,  4 },
723 	{ 228571000, P_PLL2, 2,  7 },
724 	{ }
725 };
726 
727 static struct clk_dyn_rcg gfx2d0_src = {
728 	.ns_reg = 0x0070,
729 	.md_reg[0] = 0x0064,
730 	.md_reg[1] = 0x0068,
731 	.mn[0] = {
732 		.mnctr_en_bit = 8,
733 		.mnctr_reset_bit = 25,
734 		.mnctr_mode_shift = 9,
735 		.n_val_shift = 20,
736 		.m_val_shift = 4,
737 		.width = 4,
738 	},
739 	.mn[1] = {
740 		.mnctr_en_bit = 5,
741 		.mnctr_reset_bit = 24,
742 		.mnctr_mode_shift = 6,
743 		.n_val_shift = 16,
744 		.m_val_shift = 4,
745 		.width = 4,
746 	},
747 	.s[0] = {
748 		.src_sel_shift = 3,
749 		.parent_map = mmcc_pxo_pll8_pll2_map,
750 	},
751 	.s[1] = {
752 		.src_sel_shift = 0,
753 		.parent_map = mmcc_pxo_pll8_pll2_map,
754 	},
755 	.mux_sel_bit = 11,
756 	.freq_tbl = clk_tbl_gfx2d,
757 	.clkr = {
758 		.enable_reg = 0x0060,
759 		.enable_mask = BIT(2),
760 		.hw.init = &(struct clk_init_data){
761 			.name = "gfx2d0_src",
762 			.parent_names = mmcc_pxo_pll8_pll2,
763 			.num_parents = 3,
764 			.ops = &clk_dyn_rcg_ops,
765 		},
766 	},
767 };
768 
769 static struct clk_branch gfx2d0_clk = {
770 	.halt_reg = 0x01c8,
771 	.halt_bit = 9,
772 	.clkr = {
773 		.enable_reg = 0x0060,
774 		.enable_mask = BIT(0),
775 		.hw.init = &(struct clk_init_data){
776 			.name = "gfx2d0_clk",
777 			.parent_names = (const char *[]){ "gfx2d0_src" },
778 			.num_parents = 1,
779 			.ops = &clk_branch_ops,
780 			.flags = CLK_SET_RATE_PARENT,
781 		},
782 	},
783 };
784 
785 static struct clk_dyn_rcg gfx2d1_src = {
786 	.ns_reg = 0x007c,
787 	.md_reg[0] = 0x0078,
788 	.md_reg[1] = 0x006c,
789 	.mn[0] = {
790 		.mnctr_en_bit = 8,
791 		.mnctr_reset_bit = 25,
792 		.mnctr_mode_shift = 9,
793 		.n_val_shift = 20,
794 		.m_val_shift = 4,
795 		.width = 4,
796 	},
797 	.mn[1] = {
798 		.mnctr_en_bit = 5,
799 		.mnctr_reset_bit = 24,
800 		.mnctr_mode_shift = 6,
801 		.n_val_shift = 16,
802 		.m_val_shift = 4,
803 		.width = 4,
804 	},
805 	.s[0] = {
806 		.src_sel_shift = 3,
807 		.parent_map = mmcc_pxo_pll8_pll2_map,
808 	},
809 	.s[1] = {
810 		.src_sel_shift = 0,
811 		.parent_map = mmcc_pxo_pll8_pll2_map,
812 	},
813 	.mux_sel_bit = 11,
814 	.freq_tbl = clk_tbl_gfx2d,
815 	.clkr = {
816 		.enable_reg = 0x0074,
817 		.enable_mask = BIT(2),
818 		.hw.init = &(struct clk_init_data){
819 			.name = "gfx2d1_src",
820 			.parent_names = mmcc_pxo_pll8_pll2,
821 			.num_parents = 3,
822 			.ops = &clk_dyn_rcg_ops,
823 		},
824 	},
825 };
826 
827 static struct clk_branch gfx2d1_clk = {
828 	.halt_reg = 0x01c8,
829 	.halt_bit = 14,
830 	.clkr = {
831 		.enable_reg = 0x0074,
832 		.enable_mask = BIT(0),
833 		.hw.init = &(struct clk_init_data){
834 			.name = "gfx2d1_clk",
835 			.parent_names = (const char *[]){ "gfx2d1_src" },
836 			.num_parents = 1,
837 			.ops = &clk_branch_ops,
838 			.flags = CLK_SET_RATE_PARENT,
839 		},
840 	},
841 };
842 
843 static struct freq_tbl clk_tbl_gfx3d[] = {
844 	{  27000000, P_PXO,  1,  0 },
845 	{  48000000, P_PLL8, 1,  8 },
846 	{  54857000, P_PLL8, 1,  7 },
847 	{  64000000, P_PLL8, 1,  6 },
848 	{  76800000, P_PLL8, 1,  5 },
849 	{  96000000, P_PLL8, 1,  4 },
850 	{ 128000000, P_PLL8, 1,  3 },
851 	{ 145455000, P_PLL2, 2, 11 },
852 	{ 160000000, P_PLL2, 1,  5 },
853 	{ 177778000, P_PLL2, 2,  9 },
854 	{ 200000000, P_PLL2, 1,  4 },
855 	{ 228571000, P_PLL2, 2,  7 },
856 	{ 266667000, P_PLL2, 1,  3 },
857 	{ 300000000, P_PLL3, 1,  4 },
858 	{ 320000000, P_PLL2, 2,  5 },
859 	{ 400000000, P_PLL2, 1,  2 },
860 	{ }
861 };
862 
863 static struct clk_dyn_rcg gfx3d_src = {
864 	.ns_reg = 0x008c,
865 	.md_reg[0] = 0x0084,
866 	.md_reg[1] = 0x0088,
867 	.mn[0] = {
868 		.mnctr_en_bit = 8,
869 		.mnctr_reset_bit = 25,
870 		.mnctr_mode_shift = 9,
871 		.n_val_shift = 18,
872 		.m_val_shift = 4,
873 		.width = 4,
874 	},
875 	.mn[1] = {
876 		.mnctr_en_bit = 5,
877 		.mnctr_reset_bit = 24,
878 		.mnctr_mode_shift = 6,
879 		.n_val_shift = 14,
880 		.m_val_shift = 4,
881 		.width = 4,
882 	},
883 	.s[0] = {
884 		.src_sel_shift = 3,
885 		.parent_map = mmcc_pxo_pll8_pll2_pll3_map,
886 	},
887 	.s[1] = {
888 		.src_sel_shift = 0,
889 		.parent_map = mmcc_pxo_pll8_pll2_pll3_map,
890 	},
891 	.mux_sel_bit = 11,
892 	.freq_tbl = clk_tbl_gfx3d,
893 	.clkr = {
894 		.enable_reg = 0x0080,
895 		.enable_mask = BIT(2),
896 		.hw.init = &(struct clk_init_data){
897 			.name = "gfx3d_src",
898 			.parent_names = mmcc_pxo_pll8_pll2_pll3,
899 			.num_parents = 3,
900 			.ops = &clk_dyn_rcg_ops,
901 		},
902 	},
903 };
904 
905 static struct clk_branch gfx3d_clk = {
906 	.halt_reg = 0x01c8,
907 	.halt_bit = 4,
908 	.clkr = {
909 		.enable_reg = 0x0080,
910 		.enable_mask = BIT(0),
911 		.hw.init = &(struct clk_init_data){
912 			.name = "gfx3d_clk",
913 			.parent_names = (const char *[]){ "gfx3d_src" },
914 			.num_parents = 1,
915 			.ops = &clk_branch_ops,
916 			.flags = CLK_SET_RATE_PARENT,
917 		},
918 	},
919 };
920 
921 static struct freq_tbl clk_tbl_ijpeg[] = {
922 	{  27000000, P_PXO,  1, 0,  0 },
923 	{  36570000, P_PLL8, 1, 2, 21 },
924 	{  54860000, P_PLL8, 7, 0,  0 },
925 	{  96000000, P_PLL8, 4, 0,  0 },
926 	{ 109710000, P_PLL8, 1, 2,  7 },
927 	{ 128000000, P_PLL8, 3, 0,  0 },
928 	{ 153600000, P_PLL8, 1, 2,  5 },
929 	{ 200000000, P_PLL2, 4, 0,  0 },
930 	{ 228571000, P_PLL2, 1, 2,  7 },
931 	{ 266667000, P_PLL2, 1, 1,  3 },
932 	{ 320000000, P_PLL2, 1, 2,  5 },
933 	{ }
934 };
935 
936 static struct clk_rcg ijpeg_src = {
937 	.ns_reg = 0x00a0,
938 	.md_reg = 0x009c,
939 	.mn = {
940 		.mnctr_en_bit = 5,
941 		.mnctr_reset_bit = 7,
942 		.mnctr_mode_shift = 6,
943 		.n_val_shift = 16,
944 		.m_val_shift = 8,
945 		.width = 8,
946 	},
947 	.p = {
948 		.pre_div_shift = 12,
949 		.pre_div_width = 2,
950 	},
951 	.s = {
952 		.src_sel_shift = 0,
953 		.parent_map = mmcc_pxo_pll8_pll2_map,
954 	},
955 	.freq_tbl = clk_tbl_ijpeg,
956 	.clkr = {
957 		.enable_reg = 0x0098,
958 		.enable_mask = BIT(2),
959 		.hw.init = &(struct clk_init_data){
960 			.name = "ijpeg_src",
961 			.parent_names = mmcc_pxo_pll8_pll2,
962 			.num_parents = 3,
963 			.ops = &clk_rcg_ops,
964 		},
965 	},
966 };
967 
968 static struct clk_branch ijpeg_clk = {
969 	.halt_reg = 0x01c8,
970 	.halt_bit = 24,
971 	.clkr = {
972 		.enable_reg = 0x0098,
973 		.enable_mask = BIT(0),
974 		.hw.init = &(struct clk_init_data){
975 			.name = "ijpeg_clk",
976 			.parent_names = (const char *[]){ "ijpeg_src" },
977 			.num_parents = 1,
978 			.ops = &clk_branch_ops,
979 			.flags = CLK_SET_RATE_PARENT,
980 		},
981 	},
982 };
983 
984 static struct freq_tbl clk_tbl_jpegd[] = {
985 	{  64000000, P_PLL8, 6 },
986 	{  76800000, P_PLL8, 5 },
987 	{  96000000, P_PLL8, 4 },
988 	{ 160000000, P_PLL2, 5 },
989 	{ 200000000, P_PLL2, 4 },
990 	{ }
991 };
992 
993 static struct clk_rcg jpegd_src = {
994 	.ns_reg = 0x00ac,
995 	.p = {
996 		.pre_div_shift = 12,
997 		.pre_div_width = 2,
998 	},
999 	.s = {
1000 		.src_sel_shift = 0,
1001 		.parent_map = mmcc_pxo_pll8_pll2_map,
1002 	},
1003 	.freq_tbl = clk_tbl_jpegd,
1004 	.clkr = {
1005 		.enable_reg = 0x00a4,
1006 		.enable_mask = BIT(2),
1007 		.hw.init = &(struct clk_init_data){
1008 			.name = "jpegd_src",
1009 			.parent_names = mmcc_pxo_pll8_pll2,
1010 			.num_parents = 3,
1011 			.ops = &clk_rcg_ops,
1012 		},
1013 	},
1014 };
1015 
1016 static struct clk_branch jpegd_clk = {
1017 	.halt_reg = 0x01c8,
1018 	.halt_bit = 19,
1019 	.clkr = {
1020 		.enable_reg = 0x00a4,
1021 		.enable_mask = BIT(0),
1022 		.hw.init = &(struct clk_init_data){
1023 			.name = "jpegd_clk",
1024 			.parent_names = (const char *[]){ "jpegd_src" },
1025 			.num_parents = 1,
1026 			.ops = &clk_branch_ops,
1027 			.flags = CLK_SET_RATE_PARENT,
1028 		},
1029 	},
1030 };
1031 
1032 static struct freq_tbl clk_tbl_mdp[] = {
1033 	{   9600000, P_PLL8, 1, 1, 40 },
1034 	{  13710000, P_PLL8, 1, 1, 28 },
1035 	{  27000000, P_PXO,  1, 0,  0 },
1036 	{  29540000, P_PLL8, 1, 1, 13 },
1037 	{  34910000, P_PLL8, 1, 1, 11 },
1038 	{  38400000, P_PLL8, 1, 1, 10 },
1039 	{  59080000, P_PLL8, 1, 2, 13 },
1040 	{  76800000, P_PLL8, 1, 1,  5 },
1041 	{  85330000, P_PLL8, 1, 2,  9 },
1042 	{  96000000, P_PLL8, 1, 1,  4 },
1043 	{ 128000000, P_PLL8, 1, 1,  3 },
1044 	{ 160000000, P_PLL2, 1, 1,  5 },
1045 	{ 177780000, P_PLL2, 1, 2,  9 },
1046 	{ 200000000, P_PLL2, 1, 1,  4 },
1047 	{ 228571000, P_PLL2, 1, 2,  7 },
1048 	{ 266667000, P_PLL2, 1, 1,  3 },
1049 	{ }
1050 };
1051 
1052 static struct clk_dyn_rcg mdp_src = {
1053 	.ns_reg = 0x00d0,
1054 	.md_reg[0] = 0x00c4,
1055 	.md_reg[1] = 0x00c8,
1056 	.mn[0] = {
1057 		.mnctr_en_bit = 8,
1058 		.mnctr_reset_bit = 31,
1059 		.mnctr_mode_shift = 9,
1060 		.n_val_shift = 22,
1061 		.m_val_shift = 8,
1062 		.width = 8,
1063 	},
1064 	.mn[1] = {
1065 		.mnctr_en_bit = 5,
1066 		.mnctr_reset_bit = 30,
1067 		.mnctr_mode_shift = 6,
1068 		.n_val_shift = 14,
1069 		.m_val_shift = 8,
1070 		.width = 8,
1071 	},
1072 	.s[0] = {
1073 		.src_sel_shift = 3,
1074 		.parent_map = mmcc_pxo_pll8_pll2_map,
1075 	},
1076 	.s[1] = {
1077 		.src_sel_shift = 0,
1078 		.parent_map = mmcc_pxo_pll8_pll2_map,
1079 	},
1080 	.mux_sel_bit = 11,
1081 	.freq_tbl = clk_tbl_mdp,
1082 	.clkr = {
1083 		.enable_reg = 0x00c0,
1084 		.enable_mask = BIT(2),
1085 		.hw.init = &(struct clk_init_data){
1086 			.name = "mdp_src",
1087 			.parent_names = mmcc_pxo_pll8_pll2,
1088 			.num_parents = 3,
1089 			.ops = &clk_dyn_rcg_ops,
1090 		},
1091 	},
1092 };
1093 
1094 static struct clk_branch mdp_clk = {
1095 	.halt_reg = 0x01d0,
1096 	.halt_bit = 10,
1097 	.clkr = {
1098 		.enable_reg = 0x00c0,
1099 		.enable_mask = BIT(0),
1100 		.hw.init = &(struct clk_init_data){
1101 			.name = "mdp_clk",
1102 			.parent_names = (const char *[]){ "mdp_src" },
1103 			.num_parents = 1,
1104 			.ops = &clk_branch_ops,
1105 			.flags = CLK_SET_RATE_PARENT,
1106 		},
1107 	},
1108 };
1109 
1110 static struct clk_branch mdp_lut_clk = {
1111 	.halt_reg = 0x01e8,
1112 	.halt_bit = 13,
1113 	.clkr = {
1114 		.enable_reg = 0x016c,
1115 		.enable_mask = BIT(0),
1116 		.hw.init = &(struct clk_init_data){
1117 			.parent_names = (const char *[]){ "mdp_clk" },
1118 			.num_parents = 1,
1119 			.name = "mdp_lut_clk",
1120 			.ops = &clk_branch_ops,
1121 			.flags = CLK_SET_RATE_PARENT,
1122 		},
1123 	},
1124 };
1125 
1126 static struct clk_branch mdp_vsync_clk = {
1127 	.halt_reg = 0x01cc,
1128 	.halt_bit = 22,
1129 	.clkr = {
1130 		.enable_reg = 0x0058,
1131 		.enable_mask = BIT(6),
1132 		.hw.init = &(struct clk_init_data){
1133 			.name = "mdp_vsync_clk",
1134 			.parent_names = (const char *[]){ "pxo" },
1135 			.num_parents = 1,
1136 			.ops = &clk_branch_ops
1137 		},
1138 	},
1139 };
1140 
1141 static struct freq_tbl clk_tbl_rot[] = {
1142 	{  27000000, P_PXO,   1 },
1143 	{  29540000, P_PLL8, 13 },
1144 	{  32000000, P_PLL8, 12 },
1145 	{  38400000, P_PLL8, 10 },
1146 	{  48000000, P_PLL8,  8 },
1147 	{  54860000, P_PLL8,  7 },
1148 	{  64000000, P_PLL8,  6 },
1149 	{  76800000, P_PLL8,  5 },
1150 	{  96000000, P_PLL8,  4 },
1151 	{ 100000000, P_PLL2,  8 },
1152 	{ 114290000, P_PLL2,  7 },
1153 	{ 133330000, P_PLL2,  6 },
1154 	{ 160000000, P_PLL2,  5 },
1155 	{ 200000000, P_PLL2,  4 },
1156 	{ }
1157 };
1158 
1159 static struct clk_dyn_rcg rot_src = {
1160 	.ns_reg = 0x00e8,
1161 	.p[0] = {
1162 		.pre_div_shift = 22,
1163 		.pre_div_width = 4,
1164 	},
1165 	.p[1] = {
1166 		.pre_div_shift = 26,
1167 		.pre_div_width = 4,
1168 	},
1169 	.s[0] = {
1170 		.src_sel_shift = 16,
1171 		.parent_map = mmcc_pxo_pll8_pll2_map,
1172 	},
1173 	.s[1] = {
1174 		.src_sel_shift = 19,
1175 		.parent_map = mmcc_pxo_pll8_pll2_map,
1176 	},
1177 	.mux_sel_bit = 30,
1178 	.freq_tbl = clk_tbl_rot,
1179 	.clkr = {
1180 		.enable_reg = 0x00e0,
1181 		.enable_mask = BIT(2),
1182 		.hw.init = &(struct clk_init_data){
1183 			.name = "rot_src",
1184 			.parent_names = mmcc_pxo_pll8_pll2,
1185 			.num_parents = 3,
1186 			.ops = &clk_dyn_rcg_ops,
1187 		},
1188 	},
1189 };
1190 
1191 static struct clk_branch rot_clk = {
1192 	.halt_reg = 0x01d0,
1193 	.halt_bit = 15,
1194 	.clkr = {
1195 		.enable_reg = 0x00e0,
1196 		.enable_mask = BIT(0),
1197 		.hw.init = &(struct clk_init_data){
1198 			.name = "rot_clk",
1199 			.parent_names = (const char *[]){ "rot_src" },
1200 			.num_parents = 1,
1201 			.ops = &clk_branch_ops,
1202 			.flags = CLK_SET_RATE_PARENT,
1203 		},
1204 	},
1205 };
1206 
1207 #define P_HDMI_PLL 1
1208 
1209 static u8 mmcc_pxo_hdmi_map[] = {
1210 	[P_PXO]		= 0,
1211 	[P_HDMI_PLL]	= 2,
1212 };
1213 
1214 static const char *mmcc_pxo_hdmi[] = {
1215 	"pxo",
1216 	"hdmi_pll",
1217 };
1218 
1219 static struct freq_tbl clk_tbl_tv[] = {
1220 	{  25200000, P_HDMI_PLL, 1, 0, 0 },
1221 	{  27000000, P_HDMI_PLL, 1, 0, 0 },
1222 	{  27030000, P_HDMI_PLL, 1, 0, 0 },
1223 	{  74250000, P_HDMI_PLL, 1, 0, 0 },
1224 	{ 108000000, P_HDMI_PLL, 1, 0, 0 },
1225 	{ 148500000, P_HDMI_PLL, 1, 0, 0 },
1226 	{ }
1227 };
1228 
1229 static struct clk_rcg tv_src = {
1230 	.ns_reg = 0x00f4,
1231 	.md_reg = 0x00f0,
1232 	.mn = {
1233 		.mnctr_en_bit = 5,
1234 		.mnctr_reset_bit = 7,
1235 		.mnctr_mode_shift = 6,
1236 		.n_val_shift = 16,
1237 		.m_val_shift = 8,
1238 		.width = 8,
1239 	},
1240 	.p = {
1241 		.pre_div_shift = 14,
1242 		.pre_div_width = 2,
1243 	},
1244 	.s = {
1245 		.src_sel_shift = 0,
1246 		.parent_map = mmcc_pxo_hdmi_map,
1247 	},
1248 	.freq_tbl = clk_tbl_tv,
1249 	.clkr = {
1250 		.enable_reg = 0x00ec,
1251 		.enable_mask = BIT(2),
1252 		.hw.init = &(struct clk_init_data){
1253 			.name = "tv_src",
1254 			.parent_names = mmcc_pxo_hdmi,
1255 			.num_parents = 2,
1256 			.ops = &clk_rcg_ops,
1257 			.flags = CLK_SET_RATE_PARENT,
1258 		},
1259 	},
1260 };
1261 
1262 static const char *tv_src_name[] = { "tv_src" };
1263 
1264 static struct clk_branch tv_enc_clk = {
1265 	.halt_reg = 0x01d4,
1266 	.halt_bit = 9,
1267 	.clkr = {
1268 		.enable_reg = 0x00ec,
1269 		.enable_mask = BIT(8),
1270 		.hw.init = &(struct clk_init_data){
1271 			.parent_names = tv_src_name,
1272 			.num_parents = 1,
1273 			.name = "tv_enc_clk",
1274 			.ops = &clk_branch_ops,
1275 			.flags = CLK_SET_RATE_PARENT,
1276 		},
1277 	},
1278 };
1279 
1280 static struct clk_branch tv_dac_clk = {
1281 	.halt_reg = 0x01d4,
1282 	.halt_bit = 10,
1283 	.clkr = {
1284 		.enable_reg = 0x00ec,
1285 		.enable_mask = BIT(10),
1286 		.hw.init = &(struct clk_init_data){
1287 			.parent_names = tv_src_name,
1288 			.num_parents = 1,
1289 			.name = "tv_dac_clk",
1290 			.ops = &clk_branch_ops,
1291 			.flags = CLK_SET_RATE_PARENT,
1292 		},
1293 	},
1294 };
1295 
1296 static struct clk_branch mdp_tv_clk = {
1297 	.halt_reg = 0x01d4,
1298 	.halt_bit = 12,
1299 	.clkr = {
1300 		.enable_reg = 0x00ec,
1301 		.enable_mask = BIT(0),
1302 		.hw.init = &(struct clk_init_data){
1303 			.parent_names = tv_src_name,
1304 			.num_parents = 1,
1305 			.name = "mdp_tv_clk",
1306 			.ops = &clk_branch_ops,
1307 			.flags = CLK_SET_RATE_PARENT,
1308 		},
1309 	},
1310 };
1311 
1312 static struct clk_branch hdmi_tv_clk = {
1313 	.halt_reg = 0x01d4,
1314 	.halt_bit = 11,
1315 	.clkr = {
1316 		.enable_reg = 0x00ec,
1317 		.enable_mask = BIT(12),
1318 		.hw.init = &(struct clk_init_data){
1319 			.parent_names = tv_src_name,
1320 			.num_parents = 1,
1321 			.name = "hdmi_tv_clk",
1322 			.ops = &clk_branch_ops,
1323 			.flags = CLK_SET_RATE_PARENT,
1324 		},
1325 	},
1326 };
1327 
1328 static struct clk_branch hdmi_app_clk = {
1329 	.halt_reg = 0x01cc,
1330 	.halt_bit = 25,
1331 	.clkr = {
1332 		.enable_reg = 0x005c,
1333 		.enable_mask = BIT(11),
1334 		.hw.init = &(struct clk_init_data){
1335 			.parent_names = (const char *[]){ "pxo" },
1336 			.num_parents = 1,
1337 			.name = "hdmi_app_clk",
1338 			.ops = &clk_branch_ops,
1339 		},
1340 	},
1341 };
1342 
1343 static struct freq_tbl clk_tbl_vcodec[] = {
1344 	{  27000000, P_PXO,  1,  0 },
1345 	{  32000000, P_PLL8, 1, 12 },
1346 	{  48000000, P_PLL8, 1,  8 },
1347 	{  54860000, P_PLL8, 1,  7 },
1348 	{  96000000, P_PLL8, 1,  4 },
1349 	{ 133330000, P_PLL2, 1,  6 },
1350 	{ 200000000, P_PLL2, 1,  4 },
1351 	{ 228570000, P_PLL2, 2,  7 },
1352 	{ 266670000, P_PLL2, 1,  3 },
1353 	{ }
1354 };
1355 
1356 static struct clk_dyn_rcg vcodec_src = {
1357 	.ns_reg = 0x0100,
1358 	.md_reg[0] = 0x00fc,
1359 	.md_reg[1] = 0x0128,
1360 	.mn[0] = {
1361 		.mnctr_en_bit = 5,
1362 		.mnctr_reset_bit = 31,
1363 		.mnctr_mode_shift = 6,
1364 		.n_val_shift = 11,
1365 		.m_val_shift = 8,
1366 		.width = 8,
1367 	},
1368 	.mn[1] = {
1369 		.mnctr_en_bit = 10,
1370 		.mnctr_reset_bit = 30,
1371 		.mnctr_mode_shift = 11,
1372 		.n_val_shift = 19,
1373 		.m_val_shift = 8,
1374 		.width = 8,
1375 	},
1376 	.s[0] = {
1377 		.src_sel_shift = 27,
1378 		.parent_map = mmcc_pxo_pll8_pll2_map,
1379 	},
1380 	.s[1] = {
1381 		.src_sel_shift = 0,
1382 		.parent_map = mmcc_pxo_pll8_pll2_map,
1383 	},
1384 	.mux_sel_bit = 13,
1385 	.freq_tbl = clk_tbl_vcodec,
1386 	.clkr = {
1387 		.enable_reg = 0x00f8,
1388 		.enable_mask = BIT(2),
1389 		.hw.init = &(struct clk_init_data){
1390 			.name = "vcodec_src",
1391 			.parent_names = mmcc_pxo_pll8_pll2,
1392 			.num_parents = 3,
1393 			.ops = &clk_dyn_rcg_ops,
1394 		},
1395 	},
1396 };
1397 
1398 static struct clk_branch vcodec_clk = {
1399 	.halt_reg = 0x01d0,
1400 	.halt_bit = 29,
1401 	.clkr = {
1402 		.enable_reg = 0x00f8,
1403 		.enable_mask = BIT(0),
1404 		.hw.init = &(struct clk_init_data){
1405 			.name = "vcodec_clk",
1406 			.parent_names = (const char *[]){ "vcodec_src" },
1407 			.num_parents = 1,
1408 			.ops = &clk_branch_ops,
1409 			.flags = CLK_SET_RATE_PARENT,
1410 		},
1411 	},
1412 };
1413 
1414 static struct freq_tbl clk_tbl_vpe[] = {
1415 	{  27000000, P_PXO,   1 },
1416 	{  34909000, P_PLL8, 11 },
1417 	{  38400000, P_PLL8, 10 },
1418 	{  64000000, P_PLL8,  6 },
1419 	{  76800000, P_PLL8,  5 },
1420 	{  96000000, P_PLL8,  4 },
1421 	{ 100000000, P_PLL2,  8 },
1422 	{ 160000000, P_PLL2,  5 },
1423 	{ }
1424 };
1425 
1426 static struct clk_rcg vpe_src = {
1427 	.ns_reg = 0x0118,
1428 	.p = {
1429 		.pre_div_shift = 12,
1430 		.pre_div_width = 4,
1431 	},
1432 	.s = {
1433 		.src_sel_shift = 0,
1434 		.parent_map = mmcc_pxo_pll8_pll2_map,
1435 	},
1436 	.freq_tbl = clk_tbl_vpe,
1437 	.clkr = {
1438 		.enable_reg = 0x0110,
1439 		.enable_mask = BIT(2),
1440 		.hw.init = &(struct clk_init_data){
1441 			.name = "vpe_src",
1442 			.parent_names = mmcc_pxo_pll8_pll2,
1443 			.num_parents = 3,
1444 			.ops = &clk_rcg_ops,
1445 		},
1446 	},
1447 };
1448 
1449 static struct clk_branch vpe_clk = {
1450 	.halt_reg = 0x01c8,
1451 	.halt_bit = 28,
1452 	.clkr = {
1453 		.enable_reg = 0x0110,
1454 		.enable_mask = BIT(0),
1455 		.hw.init = &(struct clk_init_data){
1456 			.name = "vpe_clk",
1457 			.parent_names = (const char *[]){ "vpe_src" },
1458 			.num_parents = 1,
1459 			.ops = &clk_branch_ops,
1460 			.flags = CLK_SET_RATE_PARENT,
1461 		},
1462 	},
1463 };
1464 
1465 static struct freq_tbl clk_tbl_vfe[] = {
1466 	{  13960000, P_PLL8,  1, 2, 55 },
1467 	{  27000000, P_PXO,   1, 0,  0 },
1468 	{  36570000, P_PLL8,  1, 2, 21 },
1469 	{  38400000, P_PLL8,  2, 1,  5 },
1470 	{  45180000, P_PLL8,  1, 2, 17 },
1471 	{  48000000, P_PLL8,  2, 1,  4 },
1472 	{  54860000, P_PLL8,  1, 1,  7 },
1473 	{  64000000, P_PLL8,  2, 1,  3 },
1474 	{  76800000, P_PLL8,  1, 1,  5 },
1475 	{  96000000, P_PLL8,  2, 1,  2 },
1476 	{ 109710000, P_PLL8,  1, 2,  7 },
1477 	{ 128000000, P_PLL8,  1, 1,  3 },
1478 	{ 153600000, P_PLL8,  1, 2,  5 },
1479 	{ 200000000, P_PLL2,  2, 1,  2 },
1480 	{ 228570000, P_PLL2,  1, 2,  7 },
1481 	{ 266667000, P_PLL2,  1, 1,  3 },
1482 	{ 320000000, P_PLL2,  1, 2,  5 },
1483 	{ }
1484 };
1485 
1486 static struct clk_rcg vfe_src = {
1487 	.ns_reg = 0x0108,
1488 	.mn = {
1489 		.mnctr_en_bit = 5,
1490 		.mnctr_reset_bit = 7,
1491 		.mnctr_mode_shift = 6,
1492 		.n_val_shift = 16,
1493 		.m_val_shift = 8,
1494 		.width = 8,
1495 	},
1496 	.p = {
1497 		.pre_div_shift = 10,
1498 		.pre_div_width = 1,
1499 	},
1500 	.s = {
1501 		.src_sel_shift = 0,
1502 		.parent_map = mmcc_pxo_pll8_pll2_map,
1503 	},
1504 	.freq_tbl = clk_tbl_vfe,
1505 	.clkr = {
1506 		.enable_reg = 0x0104,
1507 		.enable_mask = BIT(2),
1508 		.hw.init = &(struct clk_init_data){
1509 			.name = "vfe_src",
1510 			.parent_names = mmcc_pxo_pll8_pll2,
1511 			.num_parents = 3,
1512 			.ops = &clk_rcg_ops,
1513 		},
1514 	},
1515 };
1516 
1517 static struct clk_branch vfe_clk = {
1518 	.halt_reg = 0x01cc,
1519 	.halt_bit = 6,
1520 	.clkr = {
1521 		.enable_reg = 0x0104,
1522 		.enable_mask = BIT(0),
1523 		.hw.init = &(struct clk_init_data){
1524 			.name = "vfe_clk",
1525 			.parent_names = (const char *[]){ "vfe_src" },
1526 			.num_parents = 1,
1527 			.ops = &clk_branch_ops,
1528 			.flags = CLK_SET_RATE_PARENT,
1529 		},
1530 	},
1531 };
1532 
1533 static struct clk_branch vfe_csi_clk = {
1534 	.halt_reg = 0x01cc,
1535 	.halt_bit = 8,
1536 	.clkr = {
1537 		.enable_reg = 0x0104,
1538 		.enable_mask = BIT(12),
1539 		.hw.init = &(struct clk_init_data){
1540 			.parent_names = (const char *[]){ "vfe_src" },
1541 			.num_parents = 1,
1542 			.name = "vfe_csi_clk",
1543 			.ops = &clk_branch_ops,
1544 			.flags = CLK_SET_RATE_PARENT,
1545 		},
1546 	},
1547 };
1548 
1549 static struct clk_branch gmem_axi_clk = {
1550 	.halt_reg = 0x01d8,
1551 	.halt_bit = 6,
1552 	.clkr = {
1553 		.enable_reg = 0x0018,
1554 		.enable_mask = BIT(24),
1555 		.hw.init = &(struct clk_init_data){
1556 			.name = "gmem_axi_clk",
1557 			.ops = &clk_branch_ops,
1558 			.flags = CLK_IS_ROOT,
1559 		},
1560 	},
1561 };
1562 
1563 static struct clk_branch ijpeg_axi_clk = {
1564 	.hwcg_reg = 0x0018,
1565 	.hwcg_bit = 11,
1566 	.halt_reg = 0x01d8,
1567 	.halt_bit = 4,
1568 	.clkr = {
1569 		.enable_reg = 0x0018,
1570 		.enable_mask = BIT(21),
1571 		.hw.init = &(struct clk_init_data){
1572 			.name = "ijpeg_axi_clk",
1573 			.ops = &clk_branch_ops,
1574 			.flags = CLK_IS_ROOT,
1575 		},
1576 	},
1577 };
1578 
1579 static struct clk_branch mmss_imem_axi_clk = {
1580 	.hwcg_reg = 0x0018,
1581 	.hwcg_bit = 15,
1582 	.halt_reg = 0x01d8,
1583 	.halt_bit = 7,
1584 	.clkr = {
1585 		.enable_reg = 0x0018,
1586 		.enable_mask = BIT(22),
1587 		.hw.init = &(struct clk_init_data){
1588 			.name = "mmss_imem_axi_clk",
1589 			.ops = &clk_branch_ops,
1590 			.flags = CLK_IS_ROOT,
1591 		},
1592 	},
1593 };
1594 
1595 static struct clk_branch jpegd_axi_clk = {
1596 	.halt_reg = 0x01d8,
1597 	.halt_bit = 5,
1598 	.clkr = {
1599 		.enable_reg = 0x0018,
1600 		.enable_mask = BIT(25),
1601 		.hw.init = &(struct clk_init_data){
1602 			.name = "jpegd_axi_clk",
1603 			.ops = &clk_branch_ops,
1604 			.flags = CLK_IS_ROOT,
1605 		},
1606 	},
1607 };
1608 
1609 static struct clk_branch vcodec_axi_b_clk = {
1610 	.hwcg_reg = 0x0114,
1611 	.hwcg_bit = 22,
1612 	.halt_reg = 0x01e8,
1613 	.halt_bit = 25,
1614 	.clkr = {
1615 		.enable_reg = 0x0114,
1616 		.enable_mask = BIT(23),
1617 		.hw.init = &(struct clk_init_data){
1618 			.name = "vcodec_axi_b_clk",
1619 			.ops = &clk_branch_ops,
1620 			.flags = CLK_IS_ROOT,
1621 		},
1622 	},
1623 };
1624 
1625 static struct clk_branch vcodec_axi_a_clk = {
1626 	.hwcg_reg = 0x0114,
1627 	.hwcg_bit = 24,
1628 	.halt_reg = 0x01e8,
1629 	.halt_bit = 26,
1630 	.clkr = {
1631 		.enable_reg = 0x0114,
1632 		.enable_mask = BIT(25),
1633 		.hw.init = &(struct clk_init_data){
1634 			.name = "vcodec_axi_a_clk",
1635 			.ops = &clk_branch_ops,
1636 			.flags = CLK_IS_ROOT,
1637 		},
1638 	},
1639 };
1640 
1641 static struct clk_branch vcodec_axi_clk = {
1642 	.hwcg_reg = 0x0018,
1643 	.hwcg_bit = 13,
1644 	.halt_reg = 0x01d8,
1645 	.halt_bit = 3,
1646 	.clkr = {
1647 		.enable_reg = 0x0018,
1648 		.enable_mask = BIT(19),
1649 		.hw.init = &(struct clk_init_data){
1650 			.name = "vcodec_axi_clk",
1651 			.ops = &clk_branch_ops,
1652 			.flags = CLK_IS_ROOT,
1653 		},
1654 	},
1655 };
1656 
1657 static struct clk_branch vfe_axi_clk = {
1658 	.halt_reg = 0x01d8,
1659 	.halt_bit = 0,
1660 	.clkr = {
1661 		.enable_reg = 0x0018,
1662 		.enable_mask = BIT(18),
1663 		.hw.init = &(struct clk_init_data){
1664 			.name = "vfe_axi_clk",
1665 			.ops = &clk_branch_ops,
1666 			.flags = CLK_IS_ROOT,
1667 		},
1668 	},
1669 };
1670 
1671 static struct clk_branch mdp_axi_clk = {
1672 	.hwcg_reg = 0x0018,
1673 	.hwcg_bit = 16,
1674 	.halt_reg = 0x01d8,
1675 	.halt_bit = 8,
1676 	.clkr = {
1677 		.enable_reg = 0x0018,
1678 		.enable_mask = BIT(23),
1679 		.hw.init = &(struct clk_init_data){
1680 			.name = "mdp_axi_clk",
1681 			.ops = &clk_branch_ops,
1682 			.flags = CLK_IS_ROOT,
1683 		},
1684 	},
1685 };
1686 
1687 static struct clk_branch rot_axi_clk = {
1688 	.hwcg_reg = 0x0020,
1689 	.hwcg_bit = 25,
1690 	.halt_reg = 0x01d8,
1691 	.halt_bit = 2,
1692 	.clkr = {
1693 		.enable_reg = 0x0020,
1694 		.enable_mask = BIT(24),
1695 		.hw.init = &(struct clk_init_data){
1696 			.name = "rot_axi_clk",
1697 			.ops = &clk_branch_ops,
1698 			.flags = CLK_IS_ROOT,
1699 		},
1700 	},
1701 };
1702 
1703 static struct clk_branch vpe_axi_clk = {
1704 	.hwcg_reg = 0x0020,
1705 	.hwcg_bit = 27,
1706 	.halt_reg = 0x01d8,
1707 	.halt_bit = 1,
1708 	.clkr = {
1709 		.enable_reg = 0x0020,
1710 		.enable_mask = BIT(26),
1711 		.hw.init = &(struct clk_init_data){
1712 			.name = "vpe_axi_clk",
1713 			.ops = &clk_branch_ops,
1714 			.flags = CLK_IS_ROOT,
1715 		},
1716 	},
1717 };
1718 
1719 static struct clk_branch gfx3d_axi_clk = {
1720 	.hwcg_reg = 0x0244,
1721 	.hwcg_bit = 24,
1722 	.halt_reg = 0x0240,
1723 	.halt_bit = 30,
1724 	.clkr = {
1725 		.enable_reg = 0x0244,
1726 		.enable_mask = BIT(25),
1727 		.hw.init = &(struct clk_init_data){
1728 			.name = "gfx3d_axi_clk",
1729 			.ops = &clk_branch_ops,
1730 			.flags = CLK_IS_ROOT,
1731 		},
1732 	},
1733 };
1734 
1735 static struct clk_branch amp_ahb_clk = {
1736 	.halt_reg = 0x01dc,
1737 	.halt_bit = 18,
1738 	.clkr = {
1739 		.enable_reg = 0x0008,
1740 		.enable_mask = BIT(24),
1741 		.hw.init = &(struct clk_init_data){
1742 			.name = "amp_ahb_clk",
1743 			.ops = &clk_branch_ops,
1744 			.flags = CLK_IS_ROOT,
1745 		},
1746 	},
1747 };
1748 
1749 static struct clk_branch csi_ahb_clk = {
1750 	.halt_reg = 0x01dc,
1751 	.halt_bit = 16,
1752 	.clkr = {
1753 		.enable_reg = 0x0008,
1754 		.enable_mask = BIT(7),
1755 		.hw.init = &(struct clk_init_data){
1756 			.name = "csi_ahb_clk",
1757 			.ops = &clk_branch_ops,
1758 			.flags = CLK_IS_ROOT
1759 		},
1760 	},
1761 };
1762 
1763 static struct clk_branch dsi_m_ahb_clk = {
1764 	.halt_reg = 0x01dc,
1765 	.halt_bit = 19,
1766 	.clkr = {
1767 		.enable_reg = 0x0008,
1768 		.enable_mask = BIT(9),
1769 		.hw.init = &(struct clk_init_data){
1770 			.name = "dsi_m_ahb_clk",
1771 			.ops = &clk_branch_ops,
1772 			.flags = CLK_IS_ROOT,
1773 		},
1774 	},
1775 };
1776 
1777 static struct clk_branch dsi_s_ahb_clk = {
1778 	.hwcg_reg = 0x0038,
1779 	.hwcg_bit = 20,
1780 	.halt_reg = 0x01dc,
1781 	.halt_bit = 21,
1782 	.clkr = {
1783 		.enable_reg = 0x0008,
1784 		.enable_mask = BIT(18),
1785 		.hw.init = &(struct clk_init_data){
1786 			.name = "dsi_s_ahb_clk",
1787 			.ops = &clk_branch_ops,
1788 			.flags = CLK_IS_ROOT,
1789 		},
1790 	},
1791 };
1792 
1793 static struct clk_branch dsi2_m_ahb_clk = {
1794 	.halt_reg = 0x01d8,
1795 	.halt_bit = 18,
1796 	.clkr = {
1797 		.enable_reg = 0x0008,
1798 		.enable_mask = BIT(17),
1799 		.hw.init = &(struct clk_init_data){
1800 			.name = "dsi2_m_ahb_clk",
1801 			.ops = &clk_branch_ops,
1802 			.flags = CLK_IS_ROOT
1803 		},
1804 	},
1805 };
1806 
1807 static struct clk_branch dsi2_s_ahb_clk = {
1808 	.hwcg_reg = 0x0038,
1809 	.hwcg_bit = 15,
1810 	.halt_reg = 0x01dc,
1811 	.halt_bit = 20,
1812 	.clkr = {
1813 		.enable_reg = 0x0008,
1814 		.enable_mask = BIT(22),
1815 		.hw.init = &(struct clk_init_data){
1816 			.name = "dsi2_s_ahb_clk",
1817 			.ops = &clk_branch_ops,
1818 			.flags = CLK_IS_ROOT,
1819 		},
1820 	},
1821 };
1822 
1823 static struct clk_branch gfx2d0_ahb_clk = {
1824 	.hwcg_reg = 0x0038,
1825 	.hwcg_bit = 28,
1826 	.halt_reg = 0x01dc,
1827 	.halt_bit = 2,
1828 	.clkr = {
1829 		.enable_reg = 0x0008,
1830 		.enable_mask = BIT(19),
1831 		.hw.init = &(struct clk_init_data){
1832 			.name = "gfx2d0_ahb_clk",
1833 			.ops = &clk_branch_ops,
1834 			.flags = CLK_IS_ROOT,
1835 		},
1836 	},
1837 };
1838 
1839 static struct clk_branch gfx2d1_ahb_clk = {
1840 	.hwcg_reg = 0x0038,
1841 	.hwcg_bit = 29,
1842 	.halt_reg = 0x01dc,
1843 	.halt_bit = 3,
1844 	.clkr = {
1845 		.enable_reg = 0x0008,
1846 		.enable_mask = BIT(2),
1847 		.hw.init = &(struct clk_init_data){
1848 			.name = "gfx2d1_ahb_clk",
1849 			.ops = &clk_branch_ops,
1850 			.flags = CLK_IS_ROOT,
1851 		},
1852 	},
1853 };
1854 
1855 static struct clk_branch gfx3d_ahb_clk = {
1856 	.hwcg_reg = 0x0038,
1857 	.hwcg_bit = 27,
1858 	.halt_reg = 0x01dc,
1859 	.halt_bit = 4,
1860 	.clkr = {
1861 		.enable_reg = 0x0008,
1862 		.enable_mask = BIT(3),
1863 		.hw.init = &(struct clk_init_data){
1864 			.name = "gfx3d_ahb_clk",
1865 			.ops = &clk_branch_ops,
1866 			.flags = CLK_IS_ROOT,
1867 		},
1868 	},
1869 };
1870 
1871 static struct clk_branch hdmi_m_ahb_clk = {
1872 	.hwcg_reg = 0x0038,
1873 	.hwcg_bit = 21,
1874 	.halt_reg = 0x01dc,
1875 	.halt_bit = 5,
1876 	.clkr = {
1877 		.enable_reg = 0x0008,
1878 		.enable_mask = BIT(14),
1879 		.hw.init = &(struct clk_init_data){
1880 			.name = "hdmi_m_ahb_clk",
1881 			.ops = &clk_branch_ops,
1882 			.flags = CLK_IS_ROOT,
1883 		},
1884 	},
1885 };
1886 
1887 static struct clk_branch hdmi_s_ahb_clk = {
1888 	.hwcg_reg = 0x0038,
1889 	.hwcg_bit = 22,
1890 	.halt_reg = 0x01dc,
1891 	.halt_bit = 6,
1892 	.clkr = {
1893 		.enable_reg = 0x0008,
1894 		.enable_mask = BIT(4),
1895 		.hw.init = &(struct clk_init_data){
1896 			.name = "hdmi_s_ahb_clk",
1897 			.ops = &clk_branch_ops,
1898 			.flags = CLK_IS_ROOT,
1899 		},
1900 	},
1901 };
1902 
1903 static struct clk_branch ijpeg_ahb_clk = {
1904 	.halt_reg = 0x01dc,
1905 	.halt_bit = 9,
1906 	.clkr = {
1907 		.enable_reg = 0x0008,
1908 		.enable_mask = BIT(5),
1909 		.hw.init = &(struct clk_init_data){
1910 			.name = "ijpeg_ahb_clk",
1911 			.ops = &clk_branch_ops,
1912 			.flags = CLK_IS_ROOT
1913 		},
1914 	},
1915 };
1916 
1917 static struct clk_branch mmss_imem_ahb_clk = {
1918 	.hwcg_reg = 0x0038,
1919 	.hwcg_bit = 12,
1920 	.halt_reg = 0x01dc,
1921 	.halt_bit = 10,
1922 	.clkr = {
1923 		.enable_reg = 0x0008,
1924 		.enable_mask = BIT(6),
1925 		.hw.init = &(struct clk_init_data){
1926 			.name = "mmss_imem_ahb_clk",
1927 			.ops = &clk_branch_ops,
1928 			.flags = CLK_IS_ROOT
1929 		},
1930 	},
1931 };
1932 
1933 static struct clk_branch jpegd_ahb_clk = {
1934 	.halt_reg = 0x01dc,
1935 	.halt_bit = 7,
1936 	.clkr = {
1937 		.enable_reg = 0x0008,
1938 		.enable_mask = BIT(21),
1939 		.hw.init = &(struct clk_init_data){
1940 			.name = "jpegd_ahb_clk",
1941 			.ops = &clk_branch_ops,
1942 			.flags = CLK_IS_ROOT,
1943 		},
1944 	},
1945 };
1946 
1947 static struct clk_branch mdp_ahb_clk = {
1948 	.halt_reg = 0x01dc,
1949 	.halt_bit = 11,
1950 	.clkr = {
1951 		.enable_reg = 0x0008,
1952 		.enable_mask = BIT(10),
1953 		.hw.init = &(struct clk_init_data){
1954 			.name = "mdp_ahb_clk",
1955 			.ops = &clk_branch_ops,
1956 			.flags = CLK_IS_ROOT,
1957 		},
1958 	},
1959 };
1960 
1961 static struct clk_branch rot_ahb_clk = {
1962 	.halt_reg = 0x01dc,
1963 	.halt_bit = 13,
1964 	.clkr = {
1965 		.enable_reg = 0x0008,
1966 		.enable_mask = BIT(12),
1967 		.hw.init = &(struct clk_init_data){
1968 			.name = "rot_ahb_clk",
1969 			.ops = &clk_branch_ops,
1970 			.flags = CLK_IS_ROOT
1971 		},
1972 	},
1973 };
1974 
1975 static struct clk_branch smmu_ahb_clk = {
1976 	.hwcg_reg = 0x0008,
1977 	.hwcg_bit = 26,
1978 	.halt_reg = 0x01dc,
1979 	.halt_bit = 22,
1980 	.clkr = {
1981 		.enable_reg = 0x0008,
1982 		.enable_mask = BIT(15),
1983 		.hw.init = &(struct clk_init_data){
1984 			.name = "smmu_ahb_clk",
1985 			.ops = &clk_branch_ops,
1986 			.flags = CLK_IS_ROOT,
1987 		},
1988 	},
1989 };
1990 
1991 static struct clk_branch tv_enc_ahb_clk = {
1992 	.halt_reg = 0x01dc,
1993 	.halt_bit = 23,
1994 	.clkr = {
1995 		.enable_reg = 0x0008,
1996 		.enable_mask = BIT(25),
1997 		.hw.init = &(struct clk_init_data){
1998 			.name = "tv_enc_ahb_clk",
1999 			.ops = &clk_branch_ops,
2000 			.flags = CLK_IS_ROOT,
2001 		},
2002 	},
2003 };
2004 
2005 static struct clk_branch vcodec_ahb_clk = {
2006 	.hwcg_reg = 0x0038,
2007 	.hwcg_bit = 26,
2008 	.halt_reg = 0x01dc,
2009 	.halt_bit = 12,
2010 	.clkr = {
2011 		.enable_reg = 0x0008,
2012 		.enable_mask = BIT(11),
2013 		.hw.init = &(struct clk_init_data){
2014 			.name = "vcodec_ahb_clk",
2015 			.ops = &clk_branch_ops,
2016 			.flags = CLK_IS_ROOT,
2017 		},
2018 	},
2019 };
2020 
2021 static struct clk_branch vfe_ahb_clk = {
2022 	.halt_reg = 0x01dc,
2023 	.halt_bit = 14,
2024 	.clkr = {
2025 		.enable_reg = 0x0008,
2026 		.enable_mask = BIT(13),
2027 		.hw.init = &(struct clk_init_data){
2028 			.name = "vfe_ahb_clk",
2029 			.ops = &clk_branch_ops,
2030 			.flags = CLK_IS_ROOT,
2031 		},
2032 	},
2033 };
2034 
2035 static struct clk_branch vpe_ahb_clk = {
2036 	.halt_reg = 0x01dc,
2037 	.halt_bit = 15,
2038 	.clkr = {
2039 		.enable_reg = 0x0008,
2040 		.enable_mask = BIT(16),
2041 		.hw.init = &(struct clk_init_data){
2042 			.name = "vpe_ahb_clk",
2043 			.ops = &clk_branch_ops,
2044 			.flags = CLK_IS_ROOT,
2045 		},
2046 	},
2047 };
2048 
2049 static struct clk_regmap *mmcc_msm8960_clks[] = {
2050 	[TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2051 	[AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2052 	[DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2053 	[JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2054 	[GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2055 	[DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2056 	[DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2057 	[VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2058 	[SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2059 	[HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2060 	[VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2061 	[ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2062 	[VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2063 	[MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2064 	[DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2065 	[CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2066 	[MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2067 	[IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2068 	[HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2069 	[GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2070 	[GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2071 	[JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2072 	[GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2073 	[MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2074 	[MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2075 	[IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2076 	[GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2077 	[VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2078 	[VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2079 	[VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2080 	[ROT_AXI_CLK] = &rot_axi_clk.clkr,
2081 	[VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2082 	[VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2083 	[CSI0_SRC] = &csi0_src.clkr,
2084 	[CSI0_CLK] = &csi0_clk.clkr,
2085 	[CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2086 	[CSI1_SRC] = &csi1_src.clkr,
2087 	[CSI1_CLK] = &csi1_clk.clkr,
2088 	[CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2089 	[CSI2_SRC] = &csi2_src.clkr,
2090 	[CSI2_CLK] = &csi2_clk.clkr,
2091 	[CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2092 	[CSI_PIX_CLK] = &csi_pix_clk.clkr,
2093 	[CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2094 	[MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2095 	[HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2096 	[CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2097 	[CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2098 	[CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2099 	[GFX2D0_SRC] = &gfx2d0_src.clkr,
2100 	[GFX2D0_CLK] = &gfx2d0_clk.clkr,
2101 	[GFX2D1_SRC] = &gfx2d1_src.clkr,
2102 	[GFX2D1_CLK] = &gfx2d1_clk.clkr,
2103 	[GFX3D_SRC] = &gfx3d_src.clkr,
2104 	[GFX3D_CLK] = &gfx3d_clk.clkr,
2105 	[IJPEG_SRC] = &ijpeg_src.clkr,
2106 	[IJPEG_CLK] = &ijpeg_clk.clkr,
2107 	[JPEGD_SRC] = &jpegd_src.clkr,
2108 	[JPEGD_CLK] = &jpegd_clk.clkr,
2109 	[MDP_SRC] = &mdp_src.clkr,
2110 	[MDP_CLK] = &mdp_clk.clkr,
2111 	[MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2112 	[ROT_SRC] = &rot_src.clkr,
2113 	[ROT_CLK] = &rot_clk.clkr,
2114 	[TV_ENC_CLK] = &tv_enc_clk.clkr,
2115 	[TV_DAC_CLK] = &tv_dac_clk.clkr,
2116 	[HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2117 	[MDP_TV_CLK] = &mdp_tv_clk.clkr,
2118 	[TV_SRC] = &tv_src.clkr,
2119 	[VCODEC_SRC] = &vcodec_src.clkr,
2120 	[VCODEC_CLK] = &vcodec_clk.clkr,
2121 	[VFE_SRC] = &vfe_src.clkr,
2122 	[VFE_CLK] = &vfe_clk.clkr,
2123 	[VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2124 	[VPE_SRC] = &vpe_src.clkr,
2125 	[VPE_CLK] = &vpe_clk.clkr,
2126 	[CAMCLK0_SRC] = &camclk0_src.clkr,
2127 	[CAMCLK0_CLK] = &camclk0_clk.clkr,
2128 	[CAMCLK1_SRC] = &camclk1_src.clkr,
2129 	[CAMCLK1_CLK] = &camclk1_clk.clkr,
2130 	[CAMCLK2_SRC] = &camclk2_src.clkr,
2131 	[CAMCLK2_CLK] = &camclk2_clk.clkr,
2132 	[CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2133 	[CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2134 	[CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2135 	[CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2136 	[PLL2] = &pll2.clkr,
2137 };
2138 
2139 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2140 	[VPE_AXI_RESET] = { 0x0208, 15 },
2141 	[IJPEG_AXI_RESET] = { 0x0208, 14 },
2142 	[MPD_AXI_RESET] = { 0x0208, 13 },
2143 	[VFE_AXI_RESET] = { 0x0208, 9 },
2144 	[SP_AXI_RESET] = { 0x0208, 8 },
2145 	[VCODEC_AXI_RESET] = { 0x0208, 7 },
2146 	[ROT_AXI_RESET] = { 0x0208, 6 },
2147 	[VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2148 	[VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2149 	[FAB_S3_AXI_RESET] = { 0x0208, 3 },
2150 	[FAB_S2_AXI_RESET] = { 0x0208, 2 },
2151 	[FAB_S1_AXI_RESET] = { 0x0208, 1 },
2152 	[FAB_S0_AXI_RESET] = { 0x0208 },
2153 	[SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2154 	[SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2155 	[SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2156 	[SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2157 	[SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2158 	[SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2159 	[SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2160 	[SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2161 	[SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2162 	[SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2163 	[SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2164 	[SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2165 	[APU_AHB_RESET] = { 0x020c, 18 },
2166 	[CSI_AHB_RESET] = { 0x020c, 17 },
2167 	[TV_ENC_AHB_RESET] = { 0x020c, 15 },
2168 	[VPE_AHB_RESET] = { 0x020c, 14 },
2169 	[FABRIC_AHB_RESET] = { 0x020c, 13 },
2170 	[GFX2D0_AHB_RESET] = { 0x020c, 12 },
2171 	[GFX2D1_AHB_RESET] = { 0x020c, 11 },
2172 	[GFX3D_AHB_RESET] = { 0x020c, 10 },
2173 	[HDMI_AHB_RESET] = { 0x020c, 9 },
2174 	[MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2175 	[IJPEG_AHB_RESET] = { 0x020c, 7 },
2176 	[DSI_M_AHB_RESET] = { 0x020c, 6 },
2177 	[DSI_S_AHB_RESET] = { 0x020c, 5 },
2178 	[JPEGD_AHB_RESET] = { 0x020c, 4 },
2179 	[MDP_AHB_RESET] = { 0x020c, 3 },
2180 	[ROT_AHB_RESET] = { 0x020c, 2 },
2181 	[VCODEC_AHB_RESET] = { 0x020c, 1 },
2182 	[VFE_AHB_RESET] = { 0x020c, 0 },
2183 	[DSI2_M_AHB_RESET] = { 0x0210, 31 },
2184 	[DSI2_S_AHB_RESET] = { 0x0210, 30 },
2185 	[CSIPHY2_RESET] = { 0x0210, 29 },
2186 	[CSI_PIX1_RESET] = { 0x0210, 28 },
2187 	[CSIPHY0_RESET] = { 0x0210, 27 },
2188 	[CSIPHY1_RESET] = { 0x0210, 26 },
2189 	[DSI2_RESET] = { 0x0210, 25 },
2190 	[VFE_CSI_RESET] = { 0x0210, 24 },
2191 	[MDP_RESET] = { 0x0210, 21 },
2192 	[AMP_RESET] = { 0x0210, 20 },
2193 	[JPEGD_RESET] = { 0x0210, 19 },
2194 	[CSI1_RESET] = { 0x0210, 18 },
2195 	[VPE_RESET] = { 0x0210, 17 },
2196 	[MMSS_FABRIC_RESET] = { 0x0210, 16 },
2197 	[VFE_RESET] = { 0x0210, 15 },
2198 	[GFX2D0_RESET] = { 0x0210, 14 },
2199 	[GFX2D1_RESET] = { 0x0210, 13 },
2200 	[GFX3D_RESET] = { 0x0210, 12 },
2201 	[HDMI_RESET] = { 0x0210, 11 },
2202 	[MMSS_IMEM_RESET] = { 0x0210, 10 },
2203 	[IJPEG_RESET] = { 0x0210, 9 },
2204 	[CSI0_RESET] = { 0x0210, 8 },
2205 	[DSI_RESET] = { 0x0210, 7 },
2206 	[VCODEC_RESET] = { 0x0210, 6 },
2207 	[MDP_TV_RESET] = { 0x0210, 4 },
2208 	[MDP_VSYNC_RESET] = { 0x0210, 3 },
2209 	[ROT_RESET] = { 0x0210, 2 },
2210 	[TV_HDMI_RESET] = { 0x0210, 1 },
2211 	[TV_ENC_RESET] = { 0x0210 },
2212 	[CSI2_RESET] = { 0x0214, 2 },
2213 	[CSI_RDI1_RESET] = { 0x0214, 1 },
2214 	[CSI_RDI2_RESET] = { 0x0214 },
2215 };
2216 
2217 static const struct regmap_config mmcc_msm8960_regmap_config = {
2218 	.reg_bits	= 32,
2219 	.reg_stride	= 4,
2220 	.val_bits	= 32,
2221 	.max_register	= 0x334,
2222 	.fast_io	= true,
2223 };
2224 
2225 static const struct of_device_id mmcc_msm8960_match_table[] = {
2226 	{ .compatible = "qcom,mmcc-msm8960" },
2227 	{ }
2228 };
2229 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2230 
2231 struct qcom_cc {
2232 	struct qcom_reset_controller reset;
2233 	struct clk_onecell_data data;
2234 	struct clk *clks[];
2235 };
2236 
2237 static int mmcc_msm8960_probe(struct platform_device *pdev)
2238 {
2239 	void __iomem *base;
2240 	struct resource *res;
2241 	int i, ret;
2242 	struct device *dev = &pdev->dev;
2243 	struct clk *clk;
2244 	struct clk_onecell_data *data;
2245 	struct clk **clks;
2246 	struct regmap *regmap;
2247 	size_t num_clks;
2248 	struct qcom_reset_controller *reset;
2249 	struct qcom_cc *cc;
2250 
2251 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 	base = devm_ioremap_resource(dev, res);
2253 	if (IS_ERR(base))
2254 		return PTR_ERR(base);
2255 
2256 	regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2257 	if (IS_ERR(regmap))
2258 		return PTR_ERR(regmap);
2259 
2260 	num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2261 	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2262 			  GFP_KERNEL);
2263 	if (!cc)
2264 		return -ENOMEM;
2265 
2266 	clks = cc->clks;
2267 	data = &cc->data;
2268 	data->clks = clks;
2269 	data->clk_num = num_clks;
2270 
2271 	for (i = 0; i < num_clks; i++) {
2272 		if (!mmcc_msm8960_clks[i])
2273 			continue;
2274 		clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2275 		if (IS_ERR(clk))
2276 			return PTR_ERR(clk);
2277 		clks[i] = clk;
2278 	}
2279 
2280 	ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2281 	if (ret)
2282 		return ret;
2283 
2284 	reset = &cc->reset;
2285 	reset->rcdev.of_node = dev->of_node;
2286 	reset->rcdev.ops = &qcom_reset_ops,
2287 	reset->rcdev.owner = THIS_MODULE,
2288 	reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2289 	reset->regmap = regmap;
2290 	reset->reset_map = mmcc_msm8960_resets,
2291 	platform_set_drvdata(pdev, &reset->rcdev);
2292 
2293 	ret = reset_controller_register(&reset->rcdev);
2294 	if (ret)
2295 		of_clk_del_provider(dev->of_node);
2296 
2297 	return ret;
2298 }
2299 
2300 static int mmcc_msm8960_remove(struct platform_device *pdev)
2301 {
2302 	of_clk_del_provider(pdev->dev.of_node);
2303 	reset_controller_unregister(platform_get_drvdata(pdev));
2304 	return 0;
2305 }
2306 
2307 static struct platform_driver mmcc_msm8960_driver = {
2308 	.probe		= mmcc_msm8960_probe,
2309 	.remove		= mmcc_msm8960_remove,
2310 	.driver		= {
2311 		.name	= "mmcc-msm8960",
2312 		.owner	= THIS_MODULE,
2313 		.of_match_table = mmcc_msm8960_match_table,
2314 	},
2315 };
2316 
2317 module_platform_driver(mmcc_msm8960_driver);
2318 
2319 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2320 MODULE_LICENSE("GPL v2");
2321 MODULE_ALIAS("platform:mmcc-msm8960");
2322