1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 #include <linux/reset-controller.h> 12 13 #include <dt-bindings/clock/qcom,mmcc-apq8084.h> 14 #include <dt-bindings/reset/qcom,mmcc-apq8084.h> 15 16 #include "common.h" 17 #include "clk-regmap.h" 18 #include "clk-pll.h" 19 #include "clk-rcg.h" 20 #include "clk-branch.h" 21 #include "reset.h" 22 #include "gdsc.h" 23 24 enum { 25 P_XO, 26 P_MMPLL0, 27 P_EDPLINK, 28 P_MMPLL1, 29 P_HDMIPLL, 30 P_GPLL0, 31 P_EDPVCO, 32 P_MMPLL4, 33 P_DSI0PLL, 34 P_DSI0PLL_BYTE, 35 P_MMPLL2, 36 P_MMPLL3, 37 P_GPLL1, 38 P_DSI1PLL, 39 P_DSI1PLL_BYTE, 40 P_MMSLEEP, 41 }; 42 43 static struct clk_pll mmpll0 = { 44 .l_reg = 0x0004, 45 .m_reg = 0x0008, 46 .n_reg = 0x000c, 47 .config_reg = 0x0014, 48 .mode_reg = 0x0000, 49 .status_reg = 0x001c, 50 .status_bit = 17, 51 .clkr.hw.init = &(struct clk_init_data){ 52 .name = "mmpll0", 53 .parent_data = (const struct clk_parent_data[]){ 54 { .fw_name = "xo", .name = "xo_board" }, 55 }, 56 .num_parents = 1, 57 .ops = &clk_pll_ops, 58 }, 59 }; 60 61 static struct clk_regmap mmpll0_vote = { 62 .enable_reg = 0x0100, 63 .enable_mask = BIT(0), 64 .hw.init = &(struct clk_init_data){ 65 .name = "mmpll0_vote", 66 .parent_hws = (const struct clk_hw*[]){ 67 &mmpll0.clkr.hw 68 }, 69 .num_parents = 1, 70 .ops = &clk_pll_vote_ops, 71 }, 72 }; 73 74 static struct clk_pll mmpll1 = { 75 .l_reg = 0x0044, 76 .m_reg = 0x0048, 77 .n_reg = 0x004c, 78 .config_reg = 0x0050, 79 .mode_reg = 0x0040, 80 .status_reg = 0x005c, 81 .status_bit = 17, 82 .clkr.hw.init = &(struct clk_init_data){ 83 .name = "mmpll1", 84 .parent_data = (const struct clk_parent_data[]){ 85 { .fw_name = "xo", .name = "xo_board" }, 86 }, 87 .num_parents = 1, 88 .ops = &clk_pll_ops, 89 }, 90 }; 91 92 static struct clk_regmap mmpll1_vote = { 93 .enable_reg = 0x0100, 94 .enable_mask = BIT(1), 95 .hw.init = &(struct clk_init_data){ 96 .name = "mmpll1_vote", 97 .parent_hws = (const struct clk_hw*[]){ 98 &mmpll1.clkr.hw 99 }, 100 .num_parents = 1, 101 .ops = &clk_pll_vote_ops, 102 }, 103 }; 104 105 static struct clk_pll mmpll2 = { 106 .l_reg = 0x4104, 107 .m_reg = 0x4108, 108 .n_reg = 0x410c, 109 .config_reg = 0x4110, 110 .mode_reg = 0x4100, 111 .status_reg = 0x411c, 112 .clkr.hw.init = &(struct clk_init_data){ 113 .name = "mmpll2", 114 .parent_data = (const struct clk_parent_data[]){ 115 { .fw_name = "xo", .name = "xo_board" }, 116 }, 117 .num_parents = 1, 118 .ops = &clk_pll_ops, 119 }, 120 }; 121 122 static struct clk_pll mmpll3 = { 123 .l_reg = 0x0084, 124 .m_reg = 0x0088, 125 .n_reg = 0x008c, 126 .config_reg = 0x0090, 127 .mode_reg = 0x0080, 128 .status_reg = 0x009c, 129 .status_bit = 17, 130 .clkr.hw.init = &(struct clk_init_data){ 131 .name = "mmpll3", 132 .parent_data = (const struct clk_parent_data[]){ 133 { .fw_name = "xo", .name = "xo_board" }, 134 }, 135 .num_parents = 1, 136 .ops = &clk_pll_ops, 137 }, 138 }; 139 140 static struct clk_pll mmpll4 = { 141 .l_reg = 0x00a4, 142 .m_reg = 0x00a8, 143 .n_reg = 0x00ac, 144 .config_reg = 0x00b0, 145 .mode_reg = 0x0080, 146 .status_reg = 0x00bc, 147 .clkr.hw.init = &(struct clk_init_data){ 148 .name = "mmpll4", 149 .parent_data = (const struct clk_parent_data[]){ 150 { .fw_name = "xo", .name = "xo_board" }, 151 }, 152 .num_parents = 1, 153 .ops = &clk_pll_ops, 154 }, 155 }; 156 157 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 158 { P_XO, 0 }, 159 { P_MMPLL0, 1 }, 160 { P_MMPLL1, 2 }, 161 { P_GPLL0, 5 } 162 }; 163 164 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = { 165 { .fw_name = "xo", .name = "xo_board" }, 166 { .hw = &mmpll0_vote.hw }, 167 { .hw = &mmpll1_vote.hw }, 168 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 169 }; 170 171 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 172 { P_XO, 0 }, 173 { P_MMPLL0, 1 }, 174 { P_HDMIPLL, 4 }, 175 { P_GPLL0, 5 }, 176 { P_DSI0PLL, 2 }, 177 { P_DSI1PLL, 3 } 178 }; 179 180 static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 181 { .fw_name = "xo", .name = "xo_board" }, 182 { .hw = &mmpll0_vote.hw }, 183 { .fw_name = "hdmipll", .name = "hdmipll" }, 184 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 185 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 186 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 187 }; 188 189 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { 190 { P_XO, 0 }, 191 { P_MMPLL0, 1 }, 192 { P_MMPLL1, 2 }, 193 { P_GPLL0, 5 }, 194 { P_MMPLL2, 3 } 195 }; 196 197 static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = { 198 { .fw_name = "xo", .name = "xo_board" }, 199 { .hw = &mmpll0_vote.hw }, 200 { .hw = &mmpll1_vote.hw }, 201 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 202 { .hw = &mmpll2.clkr.hw }, 203 }; 204 205 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { 206 { P_XO, 0 }, 207 { P_MMPLL0, 1 }, 208 { P_MMPLL1, 2 }, 209 { P_GPLL0, 5 }, 210 { P_MMPLL3, 3 } 211 }; 212 213 static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = { 214 { .fw_name = "xo", .name = "xo_board" }, 215 { .hw = &mmpll0_vote.hw }, 216 { .hw = &mmpll1_vote.hw }, 217 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 218 { .hw = &mmpll3.clkr.hw }, 219 }; 220 221 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { 222 { P_XO, 0 }, 223 { P_EDPLINK, 4 }, 224 { P_HDMIPLL, 3 }, 225 { P_EDPVCO, 5 }, 226 { P_DSI0PLL, 1 }, 227 { P_DSI1PLL, 2 } 228 }; 229 230 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = { 231 { .fw_name = "xo", .name = "xo_board" }, 232 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 233 { .fw_name = "hdmipll", .name = "hdmipll" }, 234 { .fw_name = "edp_vco_div", .name = "edp_vco_div" }, 235 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 236 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 237 }; 238 239 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 240 { P_XO, 0 }, 241 { P_EDPLINK, 4 }, 242 { P_HDMIPLL, 3 }, 243 { P_GPLL0, 5 }, 244 { P_DSI0PLL, 1 }, 245 { P_DSI1PLL, 2 } 246 }; 247 248 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = { 249 { .fw_name = "xo", .name = "xo_board" }, 250 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 251 { .fw_name = "hdmipll", .name = "hdmipll" }, 252 { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, 253 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 254 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 255 }; 256 257 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 258 { P_XO, 0 }, 259 { P_EDPLINK, 4 }, 260 { P_HDMIPLL, 3 }, 261 { P_GPLL0, 5 }, 262 { P_DSI0PLL_BYTE, 1 }, 263 { P_DSI1PLL_BYTE, 2 } 264 }; 265 266 static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 267 { .fw_name = "xo", .name = "xo_board" }, 268 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 269 { .fw_name = "hdmipll", .name = "hdmipll" }, 270 { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, 271 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 272 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }, 273 }; 274 275 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { 276 { P_XO, 0 }, 277 { P_MMPLL0, 1 }, 278 { P_MMPLL1, 2 }, 279 { P_GPLL0, 5 }, 280 { P_MMPLL4, 3 } 281 }; 282 283 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = { 284 { .fw_name = "xo", .name = "xo_board" }, 285 { .hw = &mmpll0.clkr.hw }, 286 { .hw = &mmpll1.clkr.hw }, 287 { .hw = &mmpll4.clkr.hw }, 288 { .fw_name = "gpll0", .name = "gpll0" }, 289 }; 290 291 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { 292 { P_XO, 0 }, 293 { P_MMPLL0, 1 }, 294 { P_MMPLL1, 2 }, 295 { P_MMPLL4, 3 }, 296 { P_GPLL0, 5 }, 297 { P_GPLL1, 4 } 298 }; 299 300 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = { 301 { .fw_name = "xo", .name = "xo_board" }, 302 { .hw = &mmpll0.clkr.hw }, 303 { .hw = &mmpll1.clkr.hw }, 304 { .hw = &mmpll4.clkr.hw }, 305 { .fw_name = "gpll1", .name = "gpll1" }, 306 { .fw_name = "gpll0", .name = "gpll0" }, 307 }; 308 309 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { 310 { P_XO, 0 }, 311 { P_MMPLL0, 1 }, 312 { P_MMPLL1, 2 }, 313 { P_MMPLL4, 3 }, 314 { P_GPLL0, 5 }, 315 { P_GPLL1, 4 }, 316 { P_MMSLEEP, 6 } 317 }; 318 319 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 320 { .fw_name = "xo", .name = "xo_board" }, 321 { .hw = &mmpll0.clkr.hw }, 322 { .hw = &mmpll1.clkr.hw }, 323 { .hw = &mmpll4.clkr.hw }, 324 { .fw_name = "gpll1", .name = "gpll1" }, 325 { .fw_name = "gpll0", .name = "gpll0" }, 326 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 327 }; 328 329 static struct clk_rcg2 mmss_ahb_clk_src = { 330 .cmd_rcgr = 0x5000, 331 .hid_width = 5, 332 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 333 .clkr.hw.init = &(struct clk_init_data){ 334 .name = "mmss_ahb_clk_src", 335 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 336 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 337 .ops = &clk_rcg2_ops, 338 }, 339 }; 340 341 static const struct freq_tbl ftbl_mmss_axi_clk[] = { 342 F(19200000, P_XO, 1, 0, 0), 343 F(37500000, P_GPLL0, 16, 0, 0), 344 F(50000000, P_GPLL0, 12, 0, 0), 345 F(75000000, P_GPLL0, 8, 0, 0), 346 F(100000000, P_GPLL0, 6, 0, 0), 347 F(150000000, P_GPLL0, 4, 0, 0), 348 F(333430000, P_MMPLL1, 3.5, 0, 0), 349 F(400000000, P_MMPLL0, 2, 0, 0), 350 F(466800000, P_MMPLL1, 2.5, 0, 0), 351 { } 352 }; 353 354 static struct clk_rcg2 mmss_axi_clk_src = { 355 .cmd_rcgr = 0x5040, 356 .hid_width = 5, 357 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 358 .freq_tbl = ftbl_mmss_axi_clk, 359 .clkr.hw.init = &(struct clk_init_data){ 360 .name = "mmss_axi_clk_src", 361 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 362 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 363 .ops = &clk_rcg2_ops, 364 }, 365 }; 366 367 static const struct freq_tbl ftbl_ocmemnoc_clk[] = { 368 F(19200000, P_XO, 1, 0, 0), 369 F(37500000, P_GPLL0, 16, 0, 0), 370 F(50000000, P_GPLL0, 12, 0, 0), 371 F(75000000, P_GPLL0, 8, 0, 0), 372 F(109090000, P_GPLL0, 5.5, 0, 0), 373 F(150000000, P_GPLL0, 4, 0, 0), 374 F(228570000, P_MMPLL0, 3.5, 0, 0), 375 F(320000000, P_MMPLL0, 2.5, 0, 0), 376 { } 377 }; 378 379 static struct clk_rcg2 ocmemnoc_clk_src = { 380 .cmd_rcgr = 0x5090, 381 .hid_width = 5, 382 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 383 .freq_tbl = ftbl_ocmemnoc_clk, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "ocmemnoc_clk_src", 386 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 387 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 388 .ops = &clk_rcg2_ops, 389 }, 390 }; 391 392 static const struct freq_tbl ftbl_camss_csi0_3_clk[] = { 393 F(100000000, P_GPLL0, 6, 0, 0), 394 F(200000000, P_MMPLL0, 4, 0, 0), 395 { } 396 }; 397 398 static struct clk_rcg2 csi0_clk_src = { 399 .cmd_rcgr = 0x3090, 400 .hid_width = 5, 401 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 402 .freq_tbl = ftbl_camss_csi0_3_clk, 403 .clkr.hw.init = &(struct clk_init_data){ 404 .name = "csi0_clk_src", 405 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 406 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 407 .ops = &clk_rcg2_ops, 408 }, 409 }; 410 411 static struct clk_rcg2 csi1_clk_src = { 412 .cmd_rcgr = 0x3100, 413 .hid_width = 5, 414 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 415 .freq_tbl = ftbl_camss_csi0_3_clk, 416 .clkr.hw.init = &(struct clk_init_data){ 417 .name = "csi1_clk_src", 418 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 419 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 420 .ops = &clk_rcg2_ops, 421 }, 422 }; 423 424 static struct clk_rcg2 csi2_clk_src = { 425 .cmd_rcgr = 0x3160, 426 .hid_width = 5, 427 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 428 .freq_tbl = ftbl_camss_csi0_3_clk, 429 .clkr.hw.init = &(struct clk_init_data){ 430 .name = "csi2_clk_src", 431 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 432 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 433 .ops = &clk_rcg2_ops, 434 }, 435 }; 436 437 static struct clk_rcg2 csi3_clk_src = { 438 .cmd_rcgr = 0x31c0, 439 .hid_width = 5, 440 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 441 .freq_tbl = ftbl_camss_csi0_3_clk, 442 .clkr.hw.init = &(struct clk_init_data){ 443 .name = "csi3_clk_src", 444 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 445 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 446 .ops = &clk_rcg2_ops, 447 }, 448 }; 449 450 static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { 451 F(37500000, P_GPLL0, 16, 0, 0), 452 F(50000000, P_GPLL0, 12, 0, 0), 453 F(60000000, P_GPLL0, 10, 0, 0), 454 F(80000000, P_GPLL0, 7.5, 0, 0), 455 F(100000000, P_GPLL0, 6, 0, 0), 456 F(109090000, P_GPLL0, 5.5, 0, 0), 457 F(133330000, P_GPLL0, 4.5, 0, 0), 458 F(200000000, P_GPLL0, 3, 0, 0), 459 F(228570000, P_MMPLL0, 3.5, 0, 0), 460 F(266670000, P_MMPLL0, 3, 0, 0), 461 F(320000000, P_MMPLL0, 2.5, 0, 0), 462 F(465000000, P_MMPLL4, 2, 0, 0), 463 F(600000000, P_GPLL0, 1, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 vfe0_clk_src = { 468 .cmd_rcgr = 0x3600, 469 .hid_width = 5, 470 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 471 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 472 .clkr.hw.init = &(struct clk_init_data){ 473 .name = "vfe0_clk_src", 474 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 475 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 476 .ops = &clk_rcg2_ops, 477 }, 478 }; 479 480 static struct clk_rcg2 vfe1_clk_src = { 481 .cmd_rcgr = 0x3620, 482 .hid_width = 5, 483 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 484 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 485 .clkr.hw.init = &(struct clk_init_data){ 486 .name = "vfe1_clk_src", 487 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 488 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 489 .ops = &clk_rcg2_ops, 490 }, 491 }; 492 493 static const struct freq_tbl ftbl_mdss_mdp_clk[] = { 494 F(37500000, P_GPLL0, 16, 0, 0), 495 F(60000000, P_GPLL0, 10, 0, 0), 496 F(75000000, P_GPLL0, 8, 0, 0), 497 F(85710000, P_GPLL0, 7, 0, 0), 498 F(100000000, P_GPLL0, 6, 0, 0), 499 F(150000000, P_GPLL0, 4, 0, 0), 500 F(160000000, P_MMPLL0, 5, 0, 0), 501 F(200000000, P_MMPLL0, 4, 0, 0), 502 F(228570000, P_MMPLL0, 3.5, 0, 0), 503 F(300000000, P_GPLL0, 2, 0, 0), 504 F(320000000, P_MMPLL0, 2.5, 0, 0), 505 { } 506 }; 507 508 static struct clk_rcg2 mdp_clk_src = { 509 .cmd_rcgr = 0x2040, 510 .hid_width = 5, 511 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, 512 .freq_tbl = ftbl_mdss_mdp_clk, 513 .clkr.hw.init = &(struct clk_init_data){ 514 .name = "mdp_clk_src", 515 .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0, 516 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), 517 .ops = &clk_rcg2_ops, 518 }, 519 }; 520 521 static struct clk_rcg2 gfx3d_clk_src = { 522 .cmd_rcgr = 0x4000, 523 .hid_width = 5, 524 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, 525 .clkr.hw.init = &(struct clk_init_data){ 526 .name = "gfx3d_clk_src", 527 .parent_data = mmcc_xo_mmpll0_1_2_gpll0, 528 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0), 529 .ops = &clk_rcg2_ops, 530 }, 531 }; 532 533 static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { 534 F(75000000, P_GPLL0, 8, 0, 0), 535 F(133330000, P_GPLL0, 4.5, 0, 0), 536 F(200000000, P_GPLL0, 3, 0, 0), 537 F(228570000, P_MMPLL0, 3.5, 0, 0), 538 F(266670000, P_MMPLL0, 3, 0, 0), 539 F(320000000, P_MMPLL0, 2.5, 0, 0), 540 { } 541 }; 542 543 static struct clk_rcg2 jpeg0_clk_src = { 544 .cmd_rcgr = 0x3500, 545 .hid_width = 5, 546 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 547 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "jpeg0_clk_src", 550 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 551 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 552 .ops = &clk_rcg2_ops, 553 }, 554 }; 555 556 static struct clk_rcg2 jpeg1_clk_src = { 557 .cmd_rcgr = 0x3520, 558 .hid_width = 5, 559 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 560 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 561 .clkr.hw.init = &(struct clk_init_data){ 562 .name = "jpeg1_clk_src", 563 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 564 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 565 .ops = &clk_rcg2_ops, 566 }, 567 }; 568 569 static struct clk_rcg2 jpeg2_clk_src = { 570 .cmd_rcgr = 0x3540, 571 .hid_width = 5, 572 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 573 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "jpeg2_clk_src", 576 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 577 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static struct clk_rcg2 pclk0_clk_src = { 583 .cmd_rcgr = 0x2000, 584 .mnd_width = 8, 585 .hid_width = 5, 586 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 587 .clkr.hw.init = &(struct clk_init_data){ 588 .name = "pclk0_clk_src", 589 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 590 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 591 .ops = &clk_pixel_ops, 592 .flags = CLK_SET_RATE_PARENT, 593 }, 594 }; 595 596 static struct clk_rcg2 pclk1_clk_src = { 597 .cmd_rcgr = 0x2020, 598 .mnd_width = 8, 599 .hid_width = 5, 600 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "pclk1_clk_src", 603 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 604 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 605 .ops = &clk_pixel_ops, 606 .flags = CLK_SET_RATE_PARENT, 607 }, 608 }; 609 610 static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = { 611 F(50000000, P_GPLL0, 12, 0, 0), 612 F(100000000, P_GPLL0, 6, 0, 0), 613 F(133330000, P_GPLL0, 4.5, 0, 0), 614 F(200000000, P_MMPLL0, 4, 0, 0), 615 F(266670000, P_MMPLL0, 3, 0, 0), 616 F(465000000, P_MMPLL3, 2, 0, 0), 617 { } 618 }; 619 620 static struct clk_rcg2 vcodec0_clk_src = { 621 .cmd_rcgr = 0x1000, 622 .mnd_width = 8, 623 .hid_width = 5, 624 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, 625 .freq_tbl = ftbl_venus0_vcodec0_clk, 626 .clkr.hw.init = &(struct clk_init_data){ 627 .name = "vcodec0_clk_src", 628 .parent_data = mmcc_xo_mmpll0_1_3_gpll0, 629 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), 630 .ops = &clk_rcg2_ops, 631 }, 632 }; 633 634 static const struct freq_tbl ftbl_avsync_vp_clk[] = { 635 F(150000000, P_GPLL0, 4, 0, 0), 636 F(320000000, P_MMPLL0, 2.5, 0, 0), 637 { } 638 }; 639 640 static struct clk_rcg2 vp_clk_src = { 641 .cmd_rcgr = 0x2430, 642 .hid_width = 5, 643 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 644 .freq_tbl = ftbl_avsync_vp_clk, 645 .clkr.hw.init = &(struct clk_init_data){ 646 .name = "vp_clk_src", 647 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 648 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 649 .ops = &clk_rcg2_ops, 650 }, 651 }; 652 653 static const struct freq_tbl ftbl_camss_cci_cci_clk[] = { 654 F(19200000, P_XO, 1, 0, 0), 655 { } 656 }; 657 658 static struct clk_rcg2 cci_clk_src = { 659 .cmd_rcgr = 0x3300, 660 .mnd_width = 8, 661 .hid_width = 5, 662 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 663 .freq_tbl = ftbl_camss_cci_cci_clk, 664 .clkr.hw.init = &(struct clk_init_data){ 665 .name = "cci_clk_src", 666 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 667 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 668 .ops = &clk_rcg2_ops, 669 }, 670 }; 671 672 static const struct freq_tbl ftbl_camss_gp0_1_clk[] = { 673 F(10000, P_XO, 16, 1, 120), 674 F(24000, P_XO, 16, 1, 50), 675 F(6000000, P_GPLL0, 10, 1, 10), 676 F(12000000, P_GPLL0, 10, 1, 5), 677 F(13000000, P_GPLL0, 4, 13, 150), 678 F(24000000, P_GPLL0, 5, 1, 5), 679 { } 680 }; 681 682 static struct clk_rcg2 camss_gp0_clk_src = { 683 .cmd_rcgr = 0x3420, 684 .mnd_width = 8, 685 .hid_width = 5, 686 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 687 .freq_tbl = ftbl_camss_gp0_1_clk, 688 .clkr.hw.init = &(struct clk_init_data){ 689 .name = "camss_gp0_clk_src", 690 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 691 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep), 692 .ops = &clk_rcg2_ops, 693 }, 694 }; 695 696 static struct clk_rcg2 camss_gp1_clk_src = { 697 .cmd_rcgr = 0x3450, 698 .mnd_width = 8, 699 .hid_width = 5, 700 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 701 .freq_tbl = ftbl_camss_gp0_1_clk, 702 .clkr.hw.init = &(struct clk_init_data){ 703 .name = "camss_gp1_clk_src", 704 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 705 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep), 706 .ops = &clk_rcg2_ops, 707 }, 708 }; 709 710 static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = { 711 F(4800000, P_XO, 4, 0, 0), 712 F(6000000, P_GPLL0, 10, 1, 10), 713 F(8000000, P_GPLL0, 15, 1, 5), 714 F(9600000, P_XO, 2, 0, 0), 715 F(16000000, P_MMPLL0, 10, 1, 5), 716 F(19200000, P_XO, 1, 0, 0), 717 F(24000000, P_GPLL0, 5, 1, 5), 718 F(32000000, P_MMPLL0, 5, 1, 5), 719 F(48000000, P_GPLL0, 12.5, 0, 0), 720 F(64000000, P_MMPLL0, 12.5, 0, 0), 721 { } 722 }; 723 724 static struct clk_rcg2 mclk0_clk_src = { 725 .cmd_rcgr = 0x3360, 726 .mnd_width = 8, 727 .hid_width = 5, 728 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 729 .freq_tbl = ftbl_camss_mclk0_3_clk, 730 .clkr.hw.init = &(struct clk_init_data){ 731 .name = "mclk0_clk_src", 732 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 733 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 734 .ops = &clk_rcg2_ops, 735 }, 736 }; 737 738 static struct clk_rcg2 mclk1_clk_src = { 739 .cmd_rcgr = 0x3390, 740 .mnd_width = 8, 741 .hid_width = 5, 742 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 743 .freq_tbl = ftbl_camss_mclk0_3_clk, 744 .clkr.hw.init = &(struct clk_init_data){ 745 .name = "mclk1_clk_src", 746 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 747 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 748 .ops = &clk_rcg2_ops, 749 }, 750 }; 751 752 static struct clk_rcg2 mclk2_clk_src = { 753 .cmd_rcgr = 0x33c0, 754 .mnd_width = 8, 755 .hid_width = 5, 756 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 757 .freq_tbl = ftbl_camss_mclk0_3_clk, 758 .clkr.hw.init = &(struct clk_init_data){ 759 .name = "mclk2_clk_src", 760 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 761 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 762 .ops = &clk_rcg2_ops, 763 }, 764 }; 765 766 static struct clk_rcg2 mclk3_clk_src = { 767 .cmd_rcgr = 0x33f0, 768 .mnd_width = 8, 769 .hid_width = 5, 770 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 771 .freq_tbl = ftbl_camss_mclk0_3_clk, 772 .clkr.hw.init = &(struct clk_init_data){ 773 .name = "mclk3_clk_src", 774 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 775 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 776 .ops = &clk_rcg2_ops, 777 }, 778 }; 779 780 static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { 781 F(100000000, P_GPLL0, 6, 0, 0), 782 F(200000000, P_MMPLL0, 4, 0, 0), 783 { } 784 }; 785 786 static struct clk_rcg2 csi0phytimer_clk_src = { 787 .cmd_rcgr = 0x3000, 788 .hid_width = 5, 789 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 790 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 791 .clkr.hw.init = &(struct clk_init_data){ 792 .name = "csi0phytimer_clk_src", 793 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 794 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 795 .ops = &clk_rcg2_ops, 796 }, 797 }; 798 799 static struct clk_rcg2 csi1phytimer_clk_src = { 800 .cmd_rcgr = 0x3030, 801 .hid_width = 5, 802 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 803 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 804 .clkr.hw.init = &(struct clk_init_data){ 805 .name = "csi1phytimer_clk_src", 806 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 807 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 808 .ops = &clk_rcg2_ops, 809 }, 810 }; 811 812 static struct clk_rcg2 csi2phytimer_clk_src = { 813 .cmd_rcgr = 0x3060, 814 .hid_width = 5, 815 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 816 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 817 .clkr.hw.init = &(struct clk_init_data){ 818 .name = "csi2phytimer_clk_src", 819 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 820 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { 826 F(133330000, P_GPLL0, 4.5, 0, 0), 827 F(266670000, P_MMPLL0, 3, 0, 0), 828 F(320000000, P_MMPLL0, 2.5, 0, 0), 829 F(372000000, P_MMPLL4, 2.5, 0, 0), 830 F(465000000, P_MMPLL4, 2, 0, 0), 831 F(600000000, P_GPLL0, 1, 0, 0), 832 { } 833 }; 834 835 static struct clk_rcg2 cpp_clk_src = { 836 .cmd_rcgr = 0x3640, 837 .hid_width = 5, 838 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 839 .freq_tbl = ftbl_camss_vfe_cpp_clk, 840 .clkr.hw.init = &(struct clk_init_data){ 841 .name = "cpp_clk_src", 842 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 843 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 844 .ops = &clk_rcg2_ops, 845 }, 846 }; 847 848 static struct clk_rcg2 byte0_clk_src = { 849 .cmd_rcgr = 0x2120, 850 .hid_width = 5, 851 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 852 .clkr.hw.init = &(struct clk_init_data){ 853 .name = "byte0_clk_src", 854 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 855 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 856 .ops = &clk_byte2_ops, 857 .flags = CLK_SET_RATE_PARENT, 858 }, 859 }; 860 861 static struct clk_rcg2 byte1_clk_src = { 862 .cmd_rcgr = 0x2140, 863 .hid_width = 5, 864 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 865 .clkr.hw.init = &(struct clk_init_data){ 866 .name = "byte1_clk_src", 867 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 868 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 869 .ops = &clk_byte2_ops, 870 .flags = CLK_SET_RATE_PARENT, 871 }, 872 }; 873 874 static const struct freq_tbl ftbl_mdss_edpaux_clk[] = { 875 F(19200000, P_XO, 1, 0, 0), 876 { } 877 }; 878 879 static struct clk_rcg2 edpaux_clk_src = { 880 .cmd_rcgr = 0x20e0, 881 .hid_width = 5, 882 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 883 .freq_tbl = ftbl_mdss_edpaux_clk, 884 .clkr.hw.init = &(struct clk_init_data){ 885 .name = "edpaux_clk_src", 886 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 887 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 888 .ops = &clk_rcg2_ops, 889 }, 890 }; 891 892 static const struct freq_tbl ftbl_mdss_edplink_clk[] = { 893 F(135000000, P_EDPLINK, 2, 0, 0), 894 F(270000000, P_EDPLINK, 11, 0, 0), 895 { } 896 }; 897 898 static struct clk_rcg2 edplink_clk_src = { 899 .cmd_rcgr = 0x20c0, 900 .hid_width = 5, 901 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 902 .freq_tbl = ftbl_mdss_edplink_clk, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "edplink_clk_src", 905 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 906 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 907 .ops = &clk_rcg2_ops, 908 .flags = CLK_SET_RATE_PARENT, 909 }, 910 }; 911 912 static const struct freq_tbl edp_pixel_freq_tbl[] = { 913 { .src = P_EDPVCO }, 914 { } 915 }; 916 917 static struct clk_rcg2 edppixel_clk_src = { 918 .cmd_rcgr = 0x20a0, 919 .mnd_width = 8, 920 .hid_width = 5, 921 .parent_map = mmcc_xo_dsi_hdmi_edp_map, 922 .freq_tbl = edp_pixel_freq_tbl, 923 .clkr.hw.init = &(struct clk_init_data){ 924 .name = "edppixel_clk_src", 925 .parent_data = mmcc_xo_dsi_hdmi_edp, 926 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), 927 .ops = &clk_edp_pixel_ops, 928 }, 929 }; 930 931 static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 932 F(19200000, P_XO, 1, 0, 0), 933 { } 934 }; 935 936 static struct clk_rcg2 esc0_clk_src = { 937 .cmd_rcgr = 0x2160, 938 .hid_width = 5, 939 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 940 .freq_tbl = ftbl_mdss_esc0_1_clk, 941 .clkr.hw.init = &(struct clk_init_data){ 942 .name = "esc0_clk_src", 943 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 944 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 945 .ops = &clk_rcg2_ops, 946 }, 947 }; 948 949 static struct clk_rcg2 esc1_clk_src = { 950 .cmd_rcgr = 0x2180, 951 .hid_width = 5, 952 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 953 .freq_tbl = ftbl_mdss_esc0_1_clk, 954 .clkr.hw.init = &(struct clk_init_data){ 955 .name = "esc1_clk_src", 956 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 957 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 958 .ops = &clk_rcg2_ops, 959 }, 960 }; 961 962 static const struct freq_tbl extpclk_freq_tbl[] = { 963 { .src = P_HDMIPLL }, 964 { } 965 }; 966 967 static struct clk_rcg2 extpclk_clk_src = { 968 .cmd_rcgr = 0x2060, 969 .hid_width = 5, 970 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 971 .freq_tbl = extpclk_freq_tbl, 972 .clkr.hw.init = &(struct clk_init_data){ 973 .name = "extpclk_clk_src", 974 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 975 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 976 .ops = &clk_byte_ops, 977 .flags = CLK_SET_RATE_PARENT, 978 }, 979 }; 980 981 static const struct freq_tbl ftbl_mdss_hdmi_clk[] = { 982 F(19200000, P_XO, 1, 0, 0), 983 { } 984 }; 985 986 static struct clk_rcg2 hdmi_clk_src = { 987 .cmd_rcgr = 0x2100, 988 .hid_width = 5, 989 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 990 .freq_tbl = ftbl_mdss_hdmi_clk, 991 .clkr.hw.init = &(struct clk_init_data){ 992 .name = "hdmi_clk_src", 993 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 994 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 995 .ops = &clk_rcg2_ops, 996 }, 997 }; 998 999 static const struct freq_tbl ftbl_mdss_vsync_clk[] = { 1000 F(19200000, P_XO, 1, 0, 0), 1001 { } 1002 }; 1003 1004 static struct clk_rcg2 vsync_clk_src = { 1005 .cmd_rcgr = 0x2080, 1006 .hid_width = 5, 1007 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1008 .freq_tbl = ftbl_mdss_vsync_clk, 1009 .clkr.hw.init = &(struct clk_init_data){ 1010 .name = "vsync_clk_src", 1011 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1012 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1013 .ops = &clk_rcg2_ops, 1014 }, 1015 }; 1016 1017 static const struct freq_tbl ftbl_mmss_rbcpr_clk[] = { 1018 F(50000000, P_GPLL0, 12, 0, 0), 1019 { } 1020 }; 1021 1022 static struct clk_rcg2 rbcpr_clk_src = { 1023 .cmd_rcgr = 0x4060, 1024 .hid_width = 5, 1025 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1026 .freq_tbl = ftbl_mmss_rbcpr_clk, 1027 .clkr.hw.init = &(struct clk_init_data){ 1028 .name = "rbcpr_clk_src", 1029 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1030 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1031 .ops = &clk_rcg2_ops, 1032 }, 1033 }; 1034 1035 static const struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = { 1036 F(19200000, P_XO, 1, 0, 0), 1037 { } 1038 }; 1039 1040 static struct clk_rcg2 rbbmtimer_clk_src = { 1041 .cmd_rcgr = 0x4090, 1042 .hid_width = 5, 1043 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1044 .freq_tbl = ftbl_oxili_rbbmtimer_clk, 1045 .clkr.hw.init = &(struct clk_init_data){ 1046 .name = "rbbmtimer_clk_src", 1047 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1048 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1049 .ops = &clk_rcg2_ops, 1050 }, 1051 }; 1052 1053 static const struct freq_tbl ftbl_vpu_maple_clk[] = { 1054 F(50000000, P_GPLL0, 12, 0, 0), 1055 F(100000000, P_GPLL0, 6, 0, 0), 1056 F(133330000, P_GPLL0, 4.5, 0, 0), 1057 F(200000000, P_MMPLL0, 4, 0, 0), 1058 F(266670000, P_MMPLL0, 3, 0, 0), 1059 F(465000000, P_MMPLL3, 2, 0, 0), 1060 { } 1061 }; 1062 1063 static struct clk_rcg2 maple_clk_src = { 1064 .cmd_rcgr = 0x1320, 1065 .hid_width = 5, 1066 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1067 .freq_tbl = ftbl_vpu_maple_clk, 1068 .clkr.hw.init = &(struct clk_init_data){ 1069 .name = "maple_clk_src", 1070 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1071 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1072 .ops = &clk_rcg2_ops, 1073 }, 1074 }; 1075 1076 static const struct freq_tbl ftbl_vpu_vdp_clk[] = { 1077 F(50000000, P_GPLL0, 12, 0, 0), 1078 F(100000000, P_GPLL0, 6, 0, 0), 1079 F(200000000, P_MMPLL0, 4, 0, 0), 1080 F(320000000, P_MMPLL0, 2.5, 0, 0), 1081 F(400000000, P_MMPLL0, 2, 0, 0), 1082 { } 1083 }; 1084 1085 static struct clk_rcg2 vdp_clk_src = { 1086 .cmd_rcgr = 0x1300, 1087 .hid_width = 5, 1088 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1089 .freq_tbl = ftbl_vpu_vdp_clk, 1090 .clkr.hw.init = &(struct clk_init_data){ 1091 .name = "vdp_clk_src", 1092 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1093 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1094 .ops = &clk_rcg2_ops, 1095 }, 1096 }; 1097 1098 static const struct freq_tbl ftbl_vpu_bus_clk[] = { 1099 F(40000000, P_GPLL0, 15, 0, 0), 1100 F(80000000, P_MMPLL0, 10, 0, 0), 1101 { } 1102 }; 1103 1104 static struct clk_rcg2 vpu_bus_clk_src = { 1105 .cmd_rcgr = 0x1340, 1106 .hid_width = 5, 1107 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1108 .freq_tbl = ftbl_vpu_bus_clk, 1109 .clkr.hw.init = &(struct clk_init_data){ 1110 .name = "vpu_bus_clk_src", 1111 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1112 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1113 .ops = &clk_rcg2_ops, 1114 }, 1115 }; 1116 1117 static struct clk_branch mmss_cxo_clk = { 1118 .halt_reg = 0x5104, 1119 .clkr = { 1120 .enable_reg = 0x5104, 1121 .enable_mask = BIT(0), 1122 .hw.init = &(struct clk_init_data){ 1123 .name = "mmss_cxo_clk", 1124 .parent_data = (const struct clk_parent_data[]){ 1125 { .fw_name = "xo", .name = "xo_board" }, 1126 }, 1127 .num_parents = 1, 1128 .flags = CLK_SET_RATE_PARENT, 1129 .ops = &clk_branch2_ops, 1130 }, 1131 }, 1132 }; 1133 1134 static struct clk_branch mmss_sleepclk_clk = { 1135 .halt_reg = 0x5100, 1136 .clkr = { 1137 .enable_reg = 0x5100, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(struct clk_init_data){ 1140 .name = "mmss_sleepclk_clk", 1141 .parent_data = (const struct clk_parent_data[]){ 1142 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch avsync_ahb_clk = { 1152 .halt_reg = 0x2414, 1153 .clkr = { 1154 .enable_reg = 0x2414, 1155 .enable_mask = BIT(0), 1156 .hw.init = &(struct clk_init_data){ 1157 .name = "avsync_ahb_clk", 1158 .parent_hws = (const struct clk_hw*[]){ 1159 &mmss_ahb_clk_src.clkr.hw 1160 }, 1161 .num_parents = 1, 1162 .flags = CLK_SET_RATE_PARENT, 1163 .ops = &clk_branch2_ops, 1164 }, 1165 }, 1166 }; 1167 1168 static struct clk_branch avsync_edppixel_clk = { 1169 .halt_reg = 0x2418, 1170 .clkr = { 1171 .enable_reg = 0x2418, 1172 .enable_mask = BIT(0), 1173 .hw.init = &(struct clk_init_data){ 1174 .name = "avsync_edppixel_clk", 1175 .parent_hws = (const struct clk_hw*[]){ 1176 &edppixel_clk_src.clkr.hw 1177 }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 .ops = &clk_branch2_ops, 1181 }, 1182 }, 1183 }; 1184 1185 static struct clk_branch avsync_extpclk_clk = { 1186 .halt_reg = 0x2410, 1187 .clkr = { 1188 .enable_reg = 0x2410, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(struct clk_init_data){ 1191 .name = "avsync_extpclk_clk", 1192 .parent_hws = (const struct clk_hw*[]){ 1193 &extpclk_clk_src.clkr.hw 1194 }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch avsync_pclk0_clk = { 1203 .halt_reg = 0x241c, 1204 .clkr = { 1205 .enable_reg = 0x241c, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(struct clk_init_data){ 1208 .name = "avsync_pclk0_clk", 1209 .parent_hws = (const struct clk_hw*[]){ 1210 &pclk0_clk_src.clkr.hw 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch avsync_pclk1_clk = { 1220 .halt_reg = 0x2420, 1221 .clkr = { 1222 .enable_reg = 0x2420, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "avsync_pclk1_clk", 1226 .parent_hws = (const struct clk_hw*[]){ 1227 &pclk1_clk_src.clkr.hw 1228 }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_branch2_ops, 1232 }, 1233 }, 1234 }; 1235 1236 static struct clk_branch avsync_vp_clk = { 1237 .halt_reg = 0x2404, 1238 .clkr = { 1239 .enable_reg = 0x2404, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "avsync_vp_clk", 1243 .parent_hws = (const struct clk_hw*[]){ 1244 &vp_clk_src.clkr.hw 1245 }, 1246 .num_parents = 1, 1247 .flags = CLK_SET_RATE_PARENT, 1248 .ops = &clk_branch2_ops, 1249 }, 1250 }, 1251 }; 1252 1253 static struct clk_branch camss_ahb_clk = { 1254 .halt_reg = 0x348c, 1255 .clkr = { 1256 .enable_reg = 0x348c, 1257 .enable_mask = BIT(0), 1258 .hw.init = &(struct clk_init_data){ 1259 .name = "camss_ahb_clk", 1260 .parent_hws = (const struct clk_hw*[]){ 1261 &mmss_ahb_clk_src.clkr.hw 1262 }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch camss_cci_cci_ahb_clk = { 1271 .halt_reg = 0x3348, 1272 .clkr = { 1273 .enable_reg = 0x3348, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "camss_cci_cci_ahb_clk", 1277 .parent_hws = (const struct clk_hw*[]){ 1278 &mmss_ahb_clk_src.clkr.hw 1279 }, 1280 .num_parents = 1, 1281 .ops = &clk_branch2_ops, 1282 }, 1283 }, 1284 }; 1285 1286 static struct clk_branch camss_cci_cci_clk = { 1287 .halt_reg = 0x3344, 1288 .clkr = { 1289 .enable_reg = 0x3344, 1290 .enable_mask = BIT(0), 1291 .hw.init = &(struct clk_init_data){ 1292 .name = "camss_cci_cci_clk", 1293 .parent_hws = (const struct clk_hw*[]){ 1294 &cci_clk_src.clkr.hw 1295 }, 1296 .num_parents = 1, 1297 .flags = CLK_SET_RATE_PARENT, 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch camss_csi0_ahb_clk = { 1304 .halt_reg = 0x30bc, 1305 .clkr = { 1306 .enable_reg = 0x30bc, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "camss_csi0_ahb_clk", 1310 .parent_hws = (const struct clk_hw*[]){ 1311 &mmss_ahb_clk_src.clkr.hw 1312 }, 1313 .num_parents = 1, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch camss_csi0_clk = { 1320 .halt_reg = 0x30b4, 1321 .clkr = { 1322 .enable_reg = 0x30b4, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "camss_csi0_clk", 1326 .parent_hws = (const struct clk_hw*[]){ 1327 &csi0_clk_src.clkr.hw 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch camss_csi0phy_clk = { 1337 .halt_reg = 0x30c4, 1338 .clkr = { 1339 .enable_reg = 0x30c4, 1340 .enable_mask = BIT(0), 1341 .hw.init = &(struct clk_init_data){ 1342 .name = "camss_csi0phy_clk", 1343 .parent_hws = (const struct clk_hw*[]){ 1344 &csi0_clk_src.clkr.hw 1345 }, 1346 .num_parents = 1, 1347 .flags = CLK_SET_RATE_PARENT, 1348 .ops = &clk_branch2_ops, 1349 }, 1350 }, 1351 }; 1352 1353 static struct clk_branch camss_csi0pix_clk = { 1354 .halt_reg = 0x30e4, 1355 .clkr = { 1356 .enable_reg = 0x30e4, 1357 .enable_mask = BIT(0), 1358 .hw.init = &(struct clk_init_data){ 1359 .name = "camss_csi0pix_clk", 1360 .parent_hws = (const struct clk_hw*[]){ 1361 &csi0_clk_src.clkr.hw 1362 }, 1363 .num_parents = 1, 1364 .flags = CLK_SET_RATE_PARENT, 1365 .ops = &clk_branch2_ops, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_branch camss_csi0rdi_clk = { 1371 .halt_reg = 0x30d4, 1372 .clkr = { 1373 .enable_reg = 0x30d4, 1374 .enable_mask = BIT(0), 1375 .hw.init = &(struct clk_init_data){ 1376 .name = "camss_csi0rdi_clk", 1377 .parent_hws = (const struct clk_hw*[]){ 1378 &csi0_clk_src.clkr.hw 1379 }, 1380 .num_parents = 1, 1381 .flags = CLK_SET_RATE_PARENT, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385 }; 1386 1387 static struct clk_branch camss_csi1_ahb_clk = { 1388 .halt_reg = 0x3128, 1389 .clkr = { 1390 .enable_reg = 0x3128, 1391 .enable_mask = BIT(0), 1392 .hw.init = &(struct clk_init_data){ 1393 .name = "camss_csi1_ahb_clk", 1394 .parent_hws = (const struct clk_hw*[]){ 1395 &mmss_ahb_clk_src.clkr.hw 1396 }, 1397 .num_parents = 1, 1398 .flags = CLK_SET_RATE_PARENT, 1399 .ops = &clk_branch2_ops, 1400 }, 1401 }, 1402 }; 1403 1404 static struct clk_branch camss_csi1_clk = { 1405 .halt_reg = 0x3124, 1406 .clkr = { 1407 .enable_reg = 0x3124, 1408 .enable_mask = BIT(0), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "camss_csi1_clk", 1411 .parent_hws = (const struct clk_hw*[]){ 1412 &csi1_clk_src.clkr.hw 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 .ops = &clk_branch2_ops, 1417 }, 1418 }, 1419 }; 1420 1421 static struct clk_branch camss_csi1phy_clk = { 1422 .halt_reg = 0x3134, 1423 .clkr = { 1424 .enable_reg = 0x3134, 1425 .enable_mask = BIT(0), 1426 .hw.init = &(struct clk_init_data){ 1427 .name = "camss_csi1phy_clk", 1428 .parent_hws = (const struct clk_hw*[]){ 1429 &csi1_clk_src.clkr.hw 1430 }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436 }; 1437 1438 static struct clk_branch camss_csi1pix_clk = { 1439 .halt_reg = 0x3154, 1440 .clkr = { 1441 .enable_reg = 0x3154, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "camss_csi1pix_clk", 1445 .parent_hws = (const struct clk_hw*[]){ 1446 &csi1_clk_src.clkr.hw 1447 }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch camss_csi1rdi_clk = { 1456 .halt_reg = 0x3144, 1457 .clkr = { 1458 .enable_reg = 0x3144, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "camss_csi1rdi_clk", 1462 .parent_hws = (const struct clk_hw*[]){ 1463 &csi1_clk_src.clkr.hw 1464 }, 1465 .num_parents = 1, 1466 .flags = CLK_SET_RATE_PARENT, 1467 .ops = &clk_branch2_ops, 1468 }, 1469 }, 1470 }; 1471 1472 static struct clk_branch camss_csi2_ahb_clk = { 1473 .halt_reg = 0x3188, 1474 .clkr = { 1475 .enable_reg = 0x3188, 1476 .enable_mask = BIT(0), 1477 .hw.init = &(struct clk_init_data){ 1478 .name = "camss_csi2_ahb_clk", 1479 .parent_hws = (const struct clk_hw*[]){ 1480 &mmss_ahb_clk_src.clkr.hw 1481 }, 1482 .num_parents = 1, 1483 .ops = &clk_branch2_ops, 1484 }, 1485 }, 1486 }; 1487 1488 static struct clk_branch camss_csi2_clk = { 1489 .halt_reg = 0x3184, 1490 .clkr = { 1491 .enable_reg = 0x3184, 1492 .enable_mask = BIT(0), 1493 .hw.init = &(struct clk_init_data){ 1494 .name = "camss_csi2_clk", 1495 .parent_hws = (const struct clk_hw*[]){ 1496 &csi2_clk_src.clkr.hw 1497 }, 1498 .num_parents = 1, 1499 .flags = CLK_SET_RATE_PARENT, 1500 .ops = &clk_branch2_ops, 1501 }, 1502 }, 1503 }; 1504 1505 static struct clk_branch camss_csi2phy_clk = { 1506 .halt_reg = 0x3194, 1507 .clkr = { 1508 .enable_reg = 0x3194, 1509 .enable_mask = BIT(0), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "camss_csi2phy_clk", 1512 .parent_hws = (const struct clk_hw*[]){ 1513 &csi2_clk_src.clkr.hw 1514 }, 1515 .num_parents = 1, 1516 .flags = CLK_SET_RATE_PARENT, 1517 .ops = &clk_branch2_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static struct clk_branch camss_csi2pix_clk = { 1523 .halt_reg = 0x31b4, 1524 .clkr = { 1525 .enable_reg = 0x31b4, 1526 .enable_mask = BIT(0), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "camss_csi2pix_clk", 1529 .parent_hws = (const struct clk_hw*[]){ 1530 &csi2_clk_src.clkr.hw 1531 }, 1532 .num_parents = 1, 1533 .flags = CLK_SET_RATE_PARENT, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch camss_csi2rdi_clk = { 1540 .halt_reg = 0x31a4, 1541 .clkr = { 1542 .enable_reg = 0x31a4, 1543 .enable_mask = BIT(0), 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "camss_csi2rdi_clk", 1546 .parent_hws = (const struct clk_hw*[]){ 1547 &csi2_clk_src.clkr.hw 1548 }, 1549 .num_parents = 1, 1550 .flags = CLK_SET_RATE_PARENT, 1551 .ops = &clk_branch2_ops, 1552 }, 1553 }, 1554 }; 1555 1556 static struct clk_branch camss_csi3_ahb_clk = { 1557 .halt_reg = 0x31e8, 1558 .clkr = { 1559 .enable_reg = 0x31e8, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(struct clk_init_data){ 1562 .name = "camss_csi3_ahb_clk", 1563 .parent_hws = (const struct clk_hw*[]){ 1564 &mmss_ahb_clk_src.clkr.hw 1565 }, 1566 .num_parents = 1, 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_branch camss_csi3_clk = { 1573 .halt_reg = 0x31e4, 1574 .clkr = { 1575 .enable_reg = 0x31e4, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "camss_csi3_clk", 1579 .parent_hws = (const struct clk_hw*[]){ 1580 &csi3_clk_src.clkr.hw 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch camss_csi3phy_clk = { 1590 .halt_reg = 0x31f4, 1591 .clkr = { 1592 .enable_reg = 0x31f4, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "camss_csi3phy_clk", 1596 .parent_hws = (const struct clk_hw*[]){ 1597 &csi3_clk_src.clkr.hw 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch camss_csi3pix_clk = { 1607 .halt_reg = 0x3214, 1608 .clkr = { 1609 .enable_reg = 0x3214, 1610 .enable_mask = BIT(0), 1611 .hw.init = &(struct clk_init_data){ 1612 .name = "camss_csi3pix_clk", 1613 .parent_hws = (const struct clk_hw*[]){ 1614 &csi3_clk_src.clkr.hw 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621 }; 1622 1623 static struct clk_branch camss_csi3rdi_clk = { 1624 .halt_reg = 0x3204, 1625 .clkr = { 1626 .enable_reg = 0x3204, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "camss_csi3rdi_clk", 1630 .parent_hws = (const struct clk_hw*[]){ 1631 &csi3_clk_src.clkr.hw 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638 }; 1639 1640 static struct clk_branch camss_csi_vfe0_clk = { 1641 .halt_reg = 0x3704, 1642 .clkr = { 1643 .enable_reg = 0x3704, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(struct clk_init_data){ 1646 .name = "camss_csi_vfe0_clk", 1647 .parent_hws = (const struct clk_hw*[]){ 1648 &vfe0_clk_src.clkr.hw 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655 }; 1656 1657 static struct clk_branch camss_csi_vfe1_clk = { 1658 .halt_reg = 0x3714, 1659 .clkr = { 1660 .enable_reg = 0x3714, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(struct clk_init_data){ 1663 .name = "camss_csi_vfe1_clk", 1664 .parent_hws = (const struct clk_hw*[]){ 1665 &vfe1_clk_src.clkr.hw 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_branch camss_gp0_clk = { 1675 .halt_reg = 0x3444, 1676 .clkr = { 1677 .enable_reg = 0x3444, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "camss_gp0_clk", 1681 .parent_hws = (const struct clk_hw*[]){ 1682 &camss_gp0_clk_src.clkr.hw 1683 }, 1684 .num_parents = 1, 1685 .flags = CLK_SET_RATE_PARENT, 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689 }; 1690 1691 static struct clk_branch camss_gp1_clk = { 1692 .halt_reg = 0x3474, 1693 .clkr = { 1694 .enable_reg = 0x3474, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "camss_gp1_clk", 1698 .parent_hws = (const struct clk_hw*[]){ 1699 &camss_gp1_clk_src.clkr.hw 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706 }; 1707 1708 static struct clk_branch camss_ispif_ahb_clk = { 1709 .halt_reg = 0x3224, 1710 .clkr = { 1711 .enable_reg = 0x3224, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "camss_ispif_ahb_clk", 1715 .parent_hws = (const struct clk_hw*[]){ 1716 &mmss_ahb_clk_src.clkr.hw 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_branch camss_jpeg_jpeg0_clk = { 1726 .halt_reg = 0x35a8, 1727 .clkr = { 1728 .enable_reg = 0x35a8, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "camss_jpeg_jpeg0_clk", 1732 .parent_hws = (const struct clk_hw*[]){ 1733 &jpeg0_clk_src.clkr.hw 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch camss_jpeg_jpeg1_clk = { 1743 .halt_reg = 0x35ac, 1744 .clkr = { 1745 .enable_reg = 0x35ac, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "camss_jpeg_jpeg1_clk", 1749 .parent_hws = (const struct clk_hw*[]){ 1750 &jpeg1_clk_src.clkr.hw 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch camss_jpeg_jpeg2_clk = { 1760 .halt_reg = 0x35b0, 1761 .clkr = { 1762 .enable_reg = 0x35b0, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "camss_jpeg_jpeg2_clk", 1766 .parent_hws = (const struct clk_hw*[]){ 1767 &jpeg2_clk_src.clkr.hw 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch camss_jpeg_jpeg_ahb_clk = { 1777 .halt_reg = 0x35b4, 1778 .clkr = { 1779 .enable_reg = 0x35b4, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "camss_jpeg_jpeg_ahb_clk", 1783 .parent_hws = (const struct clk_hw*[]){ 1784 &mmss_ahb_clk_src.clkr.hw 1785 }, 1786 .num_parents = 1, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790 }; 1791 1792 static struct clk_branch camss_jpeg_jpeg_axi_clk = { 1793 .halt_reg = 0x35b8, 1794 .clkr = { 1795 .enable_reg = 0x35b8, 1796 .enable_mask = BIT(0), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "camss_jpeg_jpeg_axi_clk", 1799 .parent_hws = (const struct clk_hw*[]){ 1800 &mmss_axi_clk_src.clkr.hw 1801 }, 1802 .num_parents = 1, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806 }; 1807 1808 static struct clk_branch camss_mclk0_clk = { 1809 .halt_reg = 0x3384, 1810 .clkr = { 1811 .enable_reg = 0x3384, 1812 .enable_mask = BIT(0), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "camss_mclk0_clk", 1815 .parent_hws = (const struct clk_hw*[]){ 1816 &mclk0_clk_src.clkr.hw 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 .ops = &clk_branch2_ops, 1821 }, 1822 }, 1823 }; 1824 1825 static struct clk_branch camss_mclk1_clk = { 1826 .halt_reg = 0x33b4, 1827 .clkr = { 1828 .enable_reg = 0x33b4, 1829 .enable_mask = BIT(0), 1830 .hw.init = &(struct clk_init_data){ 1831 .name = "camss_mclk1_clk", 1832 .parent_hws = (const struct clk_hw*[]){ 1833 &mclk1_clk_src.clkr.hw 1834 }, 1835 .num_parents = 1, 1836 .flags = CLK_SET_RATE_PARENT, 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840 }; 1841 1842 static struct clk_branch camss_mclk2_clk = { 1843 .halt_reg = 0x33e4, 1844 .clkr = { 1845 .enable_reg = 0x33e4, 1846 .enable_mask = BIT(0), 1847 .hw.init = &(struct clk_init_data){ 1848 .name = "camss_mclk2_clk", 1849 .parent_hws = (const struct clk_hw*[]){ 1850 &mclk2_clk_src.clkr.hw 1851 }, 1852 .num_parents = 1, 1853 .flags = CLK_SET_RATE_PARENT, 1854 .ops = &clk_branch2_ops, 1855 }, 1856 }, 1857 }; 1858 1859 static struct clk_branch camss_mclk3_clk = { 1860 .halt_reg = 0x3414, 1861 .clkr = { 1862 .enable_reg = 0x3414, 1863 .enable_mask = BIT(0), 1864 .hw.init = &(struct clk_init_data){ 1865 .name = "camss_mclk3_clk", 1866 .parent_hws = (const struct clk_hw*[]){ 1867 &mclk3_clk_src.clkr.hw 1868 }, 1869 .num_parents = 1, 1870 .flags = CLK_SET_RATE_PARENT, 1871 .ops = &clk_branch2_ops, 1872 }, 1873 }, 1874 }; 1875 1876 static struct clk_branch camss_micro_ahb_clk = { 1877 .halt_reg = 0x3494, 1878 .clkr = { 1879 .enable_reg = 0x3494, 1880 .enable_mask = BIT(0), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "camss_micro_ahb_clk", 1883 .parent_hws = (const struct clk_hw*[]){ 1884 &mmss_ahb_clk_src.clkr.hw 1885 }, 1886 .num_parents = 1, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch camss_phy0_csi0phytimer_clk = { 1893 .halt_reg = 0x3024, 1894 .clkr = { 1895 .enable_reg = 0x3024, 1896 .enable_mask = BIT(0), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "camss_phy0_csi0phytimer_clk", 1899 .parent_hws = (const struct clk_hw*[]){ 1900 &csi0phytimer_clk_src.clkr.hw 1901 }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch camss_phy1_csi1phytimer_clk = { 1910 .halt_reg = 0x3054, 1911 .clkr = { 1912 .enable_reg = 0x3054, 1913 .enable_mask = BIT(0), 1914 .hw.init = &(struct clk_init_data){ 1915 .name = "camss_phy1_csi1phytimer_clk", 1916 .parent_hws = (const struct clk_hw*[]){ 1917 &csi1phytimer_clk_src.clkr.hw 1918 }, 1919 .num_parents = 1, 1920 .flags = CLK_SET_RATE_PARENT, 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924 }; 1925 1926 static struct clk_branch camss_phy2_csi2phytimer_clk = { 1927 .halt_reg = 0x3084, 1928 .clkr = { 1929 .enable_reg = 0x3084, 1930 .enable_mask = BIT(0), 1931 .hw.init = &(struct clk_init_data){ 1932 .name = "camss_phy2_csi2phytimer_clk", 1933 .parent_hws = (const struct clk_hw*[]){ 1934 &csi2phytimer_clk_src.clkr.hw 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch camss_top_ahb_clk = { 1944 .halt_reg = 0x3484, 1945 .clkr = { 1946 .enable_reg = 0x3484, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "camss_top_ahb_clk", 1950 .parent_hws = (const struct clk_hw*[]){ 1951 &mmss_ahb_clk_src.clkr.hw 1952 }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch camss_vfe_cpp_ahb_clk = { 1961 .halt_reg = 0x36b4, 1962 .clkr = { 1963 .enable_reg = 0x36b4, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "camss_vfe_cpp_ahb_clk", 1967 .parent_hws = (const struct clk_hw*[]){ 1968 &mmss_ahb_clk_src.clkr.hw 1969 }, 1970 .num_parents = 1, 1971 .flags = CLK_SET_RATE_PARENT, 1972 .ops = &clk_branch2_ops, 1973 }, 1974 }, 1975 }; 1976 1977 static struct clk_branch camss_vfe_cpp_clk = { 1978 .halt_reg = 0x36b0, 1979 .clkr = { 1980 .enable_reg = 0x36b0, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(struct clk_init_data){ 1983 .name = "camss_vfe_cpp_clk", 1984 .parent_hws = (const struct clk_hw*[]){ 1985 &cpp_clk_src.clkr.hw 1986 }, 1987 .num_parents = 1, 1988 .flags = CLK_SET_RATE_PARENT, 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch camss_vfe_vfe0_clk = { 1995 .halt_reg = 0x36a8, 1996 .clkr = { 1997 .enable_reg = 0x36a8, 1998 .enable_mask = BIT(0), 1999 .hw.init = &(struct clk_init_data){ 2000 .name = "camss_vfe_vfe0_clk", 2001 .parent_hws = (const struct clk_hw*[]){ 2002 &vfe0_clk_src.clkr.hw 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch camss_vfe_vfe1_clk = { 2012 .halt_reg = 0x36ac, 2013 .clkr = { 2014 .enable_reg = 0x36ac, 2015 .enable_mask = BIT(0), 2016 .hw.init = &(struct clk_init_data){ 2017 .name = "camss_vfe_vfe1_clk", 2018 .parent_hws = (const struct clk_hw*[]){ 2019 &vfe1_clk_src.clkr.hw 2020 }, 2021 .num_parents = 1, 2022 .flags = CLK_SET_RATE_PARENT, 2023 .ops = &clk_branch2_ops, 2024 }, 2025 }, 2026 }; 2027 2028 static struct clk_branch camss_vfe_vfe_ahb_clk = { 2029 .halt_reg = 0x36b8, 2030 .clkr = { 2031 .enable_reg = 0x36b8, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(struct clk_init_data){ 2034 .name = "camss_vfe_vfe_ahb_clk", 2035 .parent_hws = (const struct clk_hw*[]){ 2036 &mmss_ahb_clk_src.clkr.hw 2037 }, 2038 .num_parents = 1, 2039 .flags = CLK_SET_RATE_PARENT, 2040 .ops = &clk_branch2_ops, 2041 }, 2042 }, 2043 }; 2044 2045 static struct clk_branch camss_vfe_vfe_axi_clk = { 2046 .halt_reg = 0x36bc, 2047 .clkr = { 2048 .enable_reg = 0x36bc, 2049 .enable_mask = BIT(0), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "camss_vfe_vfe_axi_clk", 2052 .parent_hws = (const struct clk_hw*[]){ 2053 &mmss_axi_clk_src.clkr.hw 2054 }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch mdss_ahb_clk = { 2063 .halt_reg = 0x2308, 2064 .clkr = { 2065 .enable_reg = 0x2308, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "mdss_ahb_clk", 2069 .parent_hws = (const struct clk_hw*[]){ 2070 &mmss_ahb_clk_src.clkr.hw 2071 }, 2072 .num_parents = 1, 2073 .flags = CLK_SET_RATE_PARENT, 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch mdss_axi_clk = { 2080 .halt_reg = 0x2310, 2081 .clkr = { 2082 .enable_reg = 0x2310, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "mdss_axi_clk", 2086 .parent_hws = (const struct clk_hw*[]){ 2087 &mmss_axi_clk_src.clkr.hw 2088 }, 2089 .num_parents = 1, 2090 .flags = CLK_SET_RATE_PARENT, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094 }; 2095 2096 static struct clk_branch mdss_byte0_clk = { 2097 .halt_reg = 0x233c, 2098 .clkr = { 2099 .enable_reg = 0x233c, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "mdss_byte0_clk", 2103 .parent_hws = (const struct clk_hw*[]){ 2104 &byte0_clk_src.clkr.hw 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch mdss_byte1_clk = { 2114 .halt_reg = 0x2340, 2115 .clkr = { 2116 .enable_reg = 0x2340, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(struct clk_init_data){ 2119 .name = "mdss_byte1_clk", 2120 .parent_hws = (const struct clk_hw*[]){ 2121 &byte1_clk_src.clkr.hw 2122 }, 2123 .num_parents = 1, 2124 .flags = CLK_SET_RATE_PARENT, 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128 }; 2129 2130 static struct clk_branch mdss_edpaux_clk = { 2131 .halt_reg = 0x2334, 2132 .clkr = { 2133 .enable_reg = 0x2334, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "mdss_edpaux_clk", 2137 .parent_hws = (const struct clk_hw*[]){ 2138 &edpaux_clk_src.clkr.hw 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch mdss_edplink_clk = { 2148 .halt_reg = 0x2330, 2149 .clkr = { 2150 .enable_reg = 0x2330, 2151 .enable_mask = BIT(0), 2152 .hw.init = &(struct clk_init_data){ 2153 .name = "mdss_edplink_clk", 2154 .parent_hws = (const struct clk_hw*[]){ 2155 &edplink_clk_src.clkr.hw 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch mdss_edppixel_clk = { 2165 .halt_reg = 0x232c, 2166 .clkr = { 2167 .enable_reg = 0x232c, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "mdss_edppixel_clk", 2171 .parent_hws = (const struct clk_hw*[]){ 2172 &edppixel_clk_src.clkr.hw 2173 }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch mdss_esc0_clk = { 2182 .halt_reg = 0x2344, 2183 .clkr = { 2184 .enable_reg = 0x2344, 2185 .enable_mask = BIT(0), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "mdss_esc0_clk", 2188 .parent_hws = (const struct clk_hw*[]){ 2189 &esc0_clk_src.clkr.hw 2190 }, 2191 .num_parents = 1, 2192 .flags = CLK_SET_RATE_PARENT, 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196 }; 2197 2198 static struct clk_branch mdss_esc1_clk = { 2199 .halt_reg = 0x2348, 2200 .clkr = { 2201 .enable_reg = 0x2348, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(struct clk_init_data){ 2204 .name = "mdss_esc1_clk", 2205 .parent_hws = (const struct clk_hw*[]){ 2206 &esc1_clk_src.clkr.hw 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch mdss_extpclk_clk = { 2216 .halt_reg = 0x2324, 2217 .clkr = { 2218 .enable_reg = 0x2324, 2219 .enable_mask = BIT(0), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "mdss_extpclk_clk", 2222 .parent_hws = (const struct clk_hw*[]){ 2223 &extpclk_clk_src.clkr.hw 2224 }, 2225 .num_parents = 1, 2226 .flags = CLK_SET_RATE_PARENT, 2227 .ops = &clk_branch2_ops, 2228 }, 2229 }, 2230 }; 2231 2232 static struct clk_branch mdss_hdmi_ahb_clk = { 2233 .halt_reg = 0x230c, 2234 .clkr = { 2235 .enable_reg = 0x230c, 2236 .enable_mask = BIT(0), 2237 .hw.init = &(struct clk_init_data){ 2238 .name = "mdss_hdmi_ahb_clk", 2239 .parent_hws = (const struct clk_hw*[]){ 2240 &mmss_ahb_clk_src.clkr.hw 2241 }, 2242 .num_parents = 1, 2243 .flags = CLK_SET_RATE_PARENT, 2244 .ops = &clk_branch2_ops, 2245 }, 2246 }, 2247 }; 2248 2249 static struct clk_branch mdss_hdmi_clk = { 2250 .halt_reg = 0x2338, 2251 .clkr = { 2252 .enable_reg = 0x2338, 2253 .enable_mask = BIT(0), 2254 .hw.init = &(struct clk_init_data){ 2255 .name = "mdss_hdmi_clk", 2256 .parent_hws = (const struct clk_hw*[]){ 2257 &hdmi_clk_src.clkr.hw 2258 }, 2259 .num_parents = 1, 2260 .flags = CLK_SET_RATE_PARENT, 2261 .ops = &clk_branch2_ops, 2262 }, 2263 }, 2264 }; 2265 2266 static struct clk_branch mdss_mdp_clk = { 2267 .halt_reg = 0x231c, 2268 .clkr = { 2269 .enable_reg = 0x231c, 2270 .enable_mask = BIT(0), 2271 .hw.init = &(struct clk_init_data){ 2272 .name = "mdss_mdp_clk", 2273 .parent_hws = (const struct clk_hw*[]){ 2274 &mdp_clk_src.clkr.hw 2275 }, 2276 .num_parents = 1, 2277 .flags = CLK_SET_RATE_PARENT, 2278 .ops = &clk_branch2_ops, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch mdss_mdp_lut_clk = { 2284 .halt_reg = 0x2320, 2285 .clkr = { 2286 .enable_reg = 0x2320, 2287 .enable_mask = BIT(0), 2288 .hw.init = &(struct clk_init_data){ 2289 .name = "mdss_mdp_lut_clk", 2290 .parent_hws = (const struct clk_hw*[]){ 2291 &mdp_clk_src.clkr.hw 2292 }, 2293 .num_parents = 1, 2294 .flags = CLK_SET_RATE_PARENT, 2295 .ops = &clk_branch2_ops, 2296 }, 2297 }, 2298 }; 2299 2300 static struct clk_branch mdss_pclk0_clk = { 2301 .halt_reg = 0x2314, 2302 .clkr = { 2303 .enable_reg = 0x2314, 2304 .enable_mask = BIT(0), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "mdss_pclk0_clk", 2307 .parent_hws = (const struct clk_hw*[]){ 2308 &pclk0_clk_src.clkr.hw 2309 }, 2310 .num_parents = 1, 2311 .flags = CLK_SET_RATE_PARENT, 2312 .ops = &clk_branch2_ops, 2313 }, 2314 }, 2315 }; 2316 2317 static struct clk_branch mdss_pclk1_clk = { 2318 .halt_reg = 0x2318, 2319 .clkr = { 2320 .enable_reg = 0x2318, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "mdss_pclk1_clk", 2324 .parent_hws = (const struct clk_hw*[]){ 2325 &pclk1_clk_src.clkr.hw 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 .ops = &clk_branch2_ops, 2330 }, 2331 }, 2332 }; 2333 2334 static struct clk_branch mdss_vsync_clk = { 2335 .halt_reg = 0x2328, 2336 .clkr = { 2337 .enable_reg = 0x2328, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "mdss_vsync_clk", 2341 .parent_hws = (const struct clk_hw*[]){ 2342 &vsync_clk_src.clkr.hw 2343 }, 2344 .num_parents = 1, 2345 .flags = CLK_SET_RATE_PARENT, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch mmss_rbcpr_ahb_clk = { 2352 .halt_reg = 0x4088, 2353 .clkr = { 2354 .enable_reg = 0x4088, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(struct clk_init_data){ 2357 .name = "mmss_rbcpr_ahb_clk", 2358 .parent_hws = (const struct clk_hw*[]){ 2359 &mmss_ahb_clk_src.clkr.hw 2360 }, 2361 .num_parents = 1, 2362 .flags = CLK_SET_RATE_PARENT, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch mmss_rbcpr_clk = { 2369 .halt_reg = 0x4084, 2370 .clkr = { 2371 .enable_reg = 0x4084, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "mmss_rbcpr_clk", 2375 .parent_hws = (const struct clk_hw*[]){ 2376 &rbcpr_clk_src.clkr.hw 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch mmss_misc_ahb_clk = { 2386 .halt_reg = 0x502c, 2387 .clkr = { 2388 .enable_reg = 0x502c, 2389 .enable_mask = BIT(0), 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "mmss_misc_ahb_clk", 2392 .parent_hws = (const struct clk_hw*[]){ 2393 &mmss_ahb_clk_src.clkr.hw 2394 }, 2395 .num_parents = 1, 2396 .flags = CLK_SET_RATE_PARENT, 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch mmss_mmssnoc_ahb_clk = { 2403 .halt_reg = 0x5024, 2404 .clkr = { 2405 .enable_reg = 0x5024, 2406 .enable_mask = BIT(0), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "mmss_mmssnoc_ahb_clk", 2409 .parent_hws = (const struct clk_hw*[]){ 2410 &mmss_ahb_clk_src.clkr.hw 2411 }, 2412 .num_parents = 1, 2413 .ops = &clk_branch2_ops, 2414 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2415 }, 2416 }, 2417 }; 2418 2419 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { 2420 .halt_reg = 0x5028, 2421 .clkr = { 2422 .enable_reg = 0x5028, 2423 .enable_mask = BIT(0), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "mmss_mmssnoc_bto_ahb_clk", 2426 .parent_hws = (const struct clk_hw*[]){ 2427 &mmss_ahb_clk_src.clkr.hw 2428 }, 2429 .num_parents = 1, 2430 .ops = &clk_branch2_ops, 2431 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2432 }, 2433 }, 2434 }; 2435 2436 static struct clk_branch mmss_mmssnoc_axi_clk = { 2437 .halt_reg = 0x506c, 2438 .clkr = { 2439 .enable_reg = 0x506c, 2440 .enable_mask = BIT(0), 2441 .hw.init = &(struct clk_init_data){ 2442 .name = "mmss_mmssnoc_axi_clk", 2443 .parent_hws = (const struct clk_hw*[]){ 2444 &mmss_axi_clk_src.clkr.hw 2445 }, 2446 .num_parents = 1, 2447 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2448 .ops = &clk_branch2_ops, 2449 }, 2450 }, 2451 }; 2452 2453 static struct clk_branch mmss_s0_axi_clk = { 2454 .halt_reg = 0x5064, 2455 .clkr = { 2456 .enable_reg = 0x5064, 2457 .enable_mask = BIT(0), 2458 .hw.init = &(struct clk_init_data){ 2459 .name = "mmss_s0_axi_clk", 2460 .parent_hws = (const struct clk_hw*[]){ 2461 &mmss_axi_clk_src.clkr.hw 2462 }, 2463 .num_parents = 1, 2464 .ops = &clk_branch2_ops, 2465 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2466 }, 2467 }, 2468 }; 2469 2470 static struct clk_branch ocmemcx_ahb_clk = { 2471 .halt_reg = 0x405c, 2472 .clkr = { 2473 .enable_reg = 0x405c, 2474 .enable_mask = BIT(0), 2475 .hw.init = &(struct clk_init_data){ 2476 .name = "ocmemcx_ahb_clk", 2477 .parent_hws = (const struct clk_hw*[]){ 2478 &mmss_ahb_clk_src.clkr.hw 2479 }, 2480 .num_parents = 1, 2481 .flags = CLK_SET_RATE_PARENT, 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485 }; 2486 2487 static struct clk_branch ocmemcx_ocmemnoc_clk = { 2488 .halt_reg = 0x4058, 2489 .clkr = { 2490 .enable_reg = 0x4058, 2491 .enable_mask = BIT(0), 2492 .hw.init = &(struct clk_init_data){ 2493 .name = "ocmemcx_ocmemnoc_clk", 2494 .parent_hws = (const struct clk_hw*[]){ 2495 &ocmemnoc_clk_src.clkr.hw 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch oxili_ocmemgx_clk = { 2505 .halt_reg = 0x402c, 2506 .clkr = { 2507 .enable_reg = 0x402c, 2508 .enable_mask = BIT(0), 2509 .hw.init = &(struct clk_init_data){ 2510 .name = "oxili_ocmemgx_clk", 2511 .parent_hws = (const struct clk_hw*[]){ 2512 &gfx3d_clk_src.clkr.hw 2513 }, 2514 .num_parents = 1, 2515 .flags = CLK_SET_RATE_PARENT, 2516 .ops = &clk_branch2_ops, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch oxili_gfx3d_clk = { 2522 .halt_reg = 0x4028, 2523 .clkr = { 2524 .enable_reg = 0x4028, 2525 .enable_mask = BIT(0), 2526 .hw.init = &(struct clk_init_data){ 2527 .name = "oxili_gfx3d_clk", 2528 .parent_hws = (const struct clk_hw*[]){ 2529 &gfx3d_clk_src.clkr.hw 2530 }, 2531 .num_parents = 1, 2532 .flags = CLK_SET_RATE_PARENT, 2533 .ops = &clk_branch2_ops, 2534 }, 2535 }, 2536 }; 2537 2538 static struct clk_branch oxili_rbbmtimer_clk = { 2539 .halt_reg = 0x40b0, 2540 .clkr = { 2541 .enable_reg = 0x40b0, 2542 .enable_mask = BIT(0), 2543 .hw.init = &(struct clk_init_data){ 2544 .name = "oxili_rbbmtimer_clk", 2545 .parent_hws = (const struct clk_hw*[]){ 2546 &rbbmtimer_clk_src.clkr.hw 2547 }, 2548 .num_parents = 1, 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553 }; 2554 2555 static struct clk_branch oxilicx_ahb_clk = { 2556 .halt_reg = 0x403c, 2557 .clkr = { 2558 .enable_reg = 0x403c, 2559 .enable_mask = BIT(0), 2560 .hw.init = &(struct clk_init_data){ 2561 .name = "oxilicx_ahb_clk", 2562 .parent_hws = (const struct clk_hw*[]){ 2563 &mmss_ahb_clk_src.clkr.hw 2564 }, 2565 .num_parents = 1, 2566 .flags = CLK_SET_RATE_PARENT, 2567 .ops = &clk_branch2_ops, 2568 }, 2569 }, 2570 }; 2571 2572 static struct clk_branch venus0_ahb_clk = { 2573 .halt_reg = 0x1030, 2574 .clkr = { 2575 .enable_reg = 0x1030, 2576 .enable_mask = BIT(0), 2577 .hw.init = &(struct clk_init_data){ 2578 .name = "venus0_ahb_clk", 2579 .parent_hws = (const struct clk_hw*[]){ 2580 &mmss_ahb_clk_src.clkr.hw 2581 }, 2582 .num_parents = 1, 2583 .flags = CLK_SET_RATE_PARENT, 2584 .ops = &clk_branch2_ops, 2585 }, 2586 }, 2587 }; 2588 2589 static struct clk_branch venus0_axi_clk = { 2590 .halt_reg = 0x1034, 2591 .clkr = { 2592 .enable_reg = 0x1034, 2593 .enable_mask = BIT(0), 2594 .hw.init = &(struct clk_init_data){ 2595 .name = "venus0_axi_clk", 2596 .parent_hws = (const struct clk_hw*[]){ 2597 &mmss_axi_clk_src.clkr.hw 2598 }, 2599 .num_parents = 1, 2600 .flags = CLK_SET_RATE_PARENT, 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604 }; 2605 2606 static struct clk_branch venus0_core0_vcodec_clk = { 2607 .halt_reg = 0x1048, 2608 .clkr = { 2609 .enable_reg = 0x1048, 2610 .enable_mask = BIT(0), 2611 .hw.init = &(struct clk_init_data){ 2612 .name = "venus0_core0_vcodec_clk", 2613 .parent_hws = (const struct clk_hw*[]){ 2614 &vcodec0_clk_src.clkr.hw 2615 }, 2616 .num_parents = 1, 2617 .flags = CLK_SET_RATE_PARENT, 2618 .ops = &clk_branch2_ops, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch venus0_core1_vcodec_clk = { 2624 .halt_reg = 0x104c, 2625 .clkr = { 2626 .enable_reg = 0x104c, 2627 .enable_mask = BIT(0), 2628 .hw.init = &(struct clk_init_data){ 2629 .name = "venus0_core1_vcodec_clk", 2630 .parent_hws = (const struct clk_hw*[]){ 2631 &vcodec0_clk_src.clkr.hw 2632 }, 2633 .num_parents = 1, 2634 .flags = CLK_SET_RATE_PARENT, 2635 .ops = &clk_branch2_ops, 2636 }, 2637 }, 2638 }; 2639 2640 static struct clk_branch venus0_ocmemnoc_clk = { 2641 .halt_reg = 0x1038, 2642 .clkr = { 2643 .enable_reg = 0x1038, 2644 .enable_mask = BIT(0), 2645 .hw.init = &(struct clk_init_data){ 2646 .name = "venus0_ocmemnoc_clk", 2647 .parent_hws = (const struct clk_hw*[]){ 2648 &ocmemnoc_clk_src.clkr.hw 2649 }, 2650 .num_parents = 1, 2651 .flags = CLK_SET_RATE_PARENT, 2652 .ops = &clk_branch2_ops, 2653 }, 2654 }, 2655 }; 2656 2657 static struct clk_branch venus0_vcodec0_clk = { 2658 .halt_reg = 0x1028, 2659 .clkr = { 2660 .enable_reg = 0x1028, 2661 .enable_mask = BIT(0), 2662 .hw.init = &(struct clk_init_data){ 2663 .name = "venus0_vcodec0_clk", 2664 .parent_hws = (const struct clk_hw*[]){ 2665 &vcodec0_clk_src.clkr.hw 2666 }, 2667 .num_parents = 1, 2668 .flags = CLK_SET_RATE_PARENT, 2669 .ops = &clk_branch2_ops, 2670 }, 2671 }, 2672 }; 2673 2674 static struct clk_branch vpu_ahb_clk = { 2675 .halt_reg = 0x1430, 2676 .clkr = { 2677 .enable_reg = 0x1430, 2678 .enable_mask = BIT(0), 2679 .hw.init = &(struct clk_init_data){ 2680 .name = "vpu_ahb_clk", 2681 .parent_hws = (const struct clk_hw*[]){ 2682 &mmss_ahb_clk_src.clkr.hw 2683 }, 2684 .num_parents = 1, 2685 .flags = CLK_SET_RATE_PARENT, 2686 .ops = &clk_branch2_ops, 2687 }, 2688 }, 2689 }; 2690 2691 static struct clk_branch vpu_axi_clk = { 2692 .halt_reg = 0x143c, 2693 .clkr = { 2694 .enable_reg = 0x143c, 2695 .enable_mask = BIT(0), 2696 .hw.init = &(struct clk_init_data){ 2697 .name = "vpu_axi_clk", 2698 .parent_hws = (const struct clk_hw*[]){ 2699 &mmss_axi_clk_src.clkr.hw 2700 }, 2701 .num_parents = 1, 2702 .flags = CLK_SET_RATE_PARENT, 2703 .ops = &clk_branch2_ops, 2704 }, 2705 }, 2706 }; 2707 2708 static struct clk_branch vpu_bus_clk = { 2709 .halt_reg = 0x1440, 2710 .clkr = { 2711 .enable_reg = 0x1440, 2712 .enable_mask = BIT(0), 2713 .hw.init = &(struct clk_init_data){ 2714 .name = "vpu_bus_clk", 2715 .parent_hws = (const struct clk_hw*[]){ 2716 &vpu_bus_clk_src.clkr.hw 2717 }, 2718 .num_parents = 1, 2719 .flags = CLK_SET_RATE_PARENT, 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct clk_branch vpu_cxo_clk = { 2726 .halt_reg = 0x1434, 2727 .clkr = { 2728 .enable_reg = 0x1434, 2729 .enable_mask = BIT(0), 2730 .hw.init = &(struct clk_init_data){ 2731 .name = "vpu_cxo_clk", 2732 .parent_data = (const struct clk_parent_data[]){ 2733 { .fw_name = "xo", .name = "xo_board" }, 2734 }, 2735 .num_parents = 1, 2736 .flags = CLK_SET_RATE_PARENT, 2737 .ops = &clk_branch2_ops, 2738 }, 2739 }, 2740 }; 2741 2742 static struct clk_branch vpu_maple_clk = { 2743 .halt_reg = 0x142c, 2744 .clkr = { 2745 .enable_reg = 0x142c, 2746 .enable_mask = BIT(0), 2747 .hw.init = &(struct clk_init_data){ 2748 .name = "vpu_maple_clk", 2749 .parent_hws = (const struct clk_hw*[]){ 2750 &maple_clk_src.clkr.hw 2751 }, 2752 .num_parents = 1, 2753 .flags = CLK_SET_RATE_PARENT, 2754 .ops = &clk_branch2_ops, 2755 }, 2756 }, 2757 }; 2758 2759 static struct clk_branch vpu_sleep_clk = { 2760 .halt_reg = 0x1438, 2761 .clkr = { 2762 .enable_reg = 0x1438, 2763 .enable_mask = BIT(0), 2764 .hw.init = &(struct clk_init_data){ 2765 .name = "vpu_sleep_clk", 2766 .parent_data = (const struct clk_parent_data[]){ 2767 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 2768 }, 2769 .num_parents = 1, 2770 .flags = CLK_SET_RATE_PARENT, 2771 .ops = &clk_branch2_ops, 2772 }, 2773 }, 2774 }; 2775 2776 static struct clk_branch vpu_vdp_clk = { 2777 .halt_reg = 0x1428, 2778 .clkr = { 2779 .enable_reg = 0x1428, 2780 .enable_mask = BIT(0), 2781 .hw.init = &(struct clk_init_data){ 2782 .name = "vpu_vdp_clk", 2783 .parent_hws = (const struct clk_hw*[]){ 2784 &vdp_clk_src.clkr.hw 2785 }, 2786 .num_parents = 1, 2787 .flags = CLK_SET_RATE_PARENT, 2788 .ops = &clk_branch2_ops, 2789 }, 2790 }, 2791 }; 2792 2793 static const struct pll_config mmpll1_config = { 2794 .l = 60, 2795 .m = 25, 2796 .n = 32, 2797 .vco_val = 0x0, 2798 .vco_mask = 0x3 << 20, 2799 .pre_div_val = 0x0, 2800 .pre_div_mask = 0x7 << 12, 2801 .post_div_val = 0x0, 2802 .post_div_mask = 0x3 << 8, 2803 .mn_ena_mask = BIT(24), 2804 .main_output_mask = BIT(0), 2805 }; 2806 2807 static const struct pll_config mmpll3_config = { 2808 .l = 48, 2809 .m = 7, 2810 .n = 16, 2811 .vco_val = 0x0, 2812 .vco_mask = 0x3 << 20, 2813 .pre_div_val = 0x0, 2814 .pre_div_mask = 0x7 << 12, 2815 .post_div_val = 0x0, 2816 .post_div_mask = 0x3 << 8, 2817 .mn_ena_mask = BIT(24), 2818 .main_output_mask = BIT(0), 2819 .aux_output_mask = BIT(1), 2820 }; 2821 2822 static struct gdsc venus0_gdsc = { 2823 .gdscr = 0x1024, 2824 .pd = { 2825 .name = "venus0", 2826 }, 2827 .pwrsts = PWRSTS_OFF_ON, 2828 }; 2829 2830 static struct gdsc venus0_core0_gdsc = { 2831 .gdscr = 0x1040, 2832 .pd = { 2833 .name = "venus0_core0", 2834 }, 2835 .pwrsts = PWRSTS_OFF_ON, 2836 }; 2837 2838 static struct gdsc venus0_core1_gdsc = { 2839 .gdscr = 0x1044, 2840 .pd = { 2841 .name = "venus0_core1", 2842 }, 2843 .pwrsts = PWRSTS_OFF_ON, 2844 }; 2845 2846 static struct gdsc mdss_gdsc = { 2847 .gdscr = 0x2304, 2848 .cxcs = (unsigned int []){ 0x231c, 0x2320 }, 2849 .cxc_count = 2, 2850 .pd = { 2851 .name = "mdss", 2852 }, 2853 .pwrsts = PWRSTS_OFF_ON, 2854 }; 2855 2856 static struct gdsc camss_jpeg_gdsc = { 2857 .gdscr = 0x35a4, 2858 .pd = { 2859 .name = "camss_jpeg", 2860 }, 2861 .pwrsts = PWRSTS_OFF_ON, 2862 }; 2863 2864 static struct gdsc camss_vfe_gdsc = { 2865 .gdscr = 0x36a4, 2866 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 }, 2867 .cxc_count = 3, 2868 .pd = { 2869 .name = "camss_vfe", 2870 }, 2871 .pwrsts = PWRSTS_OFF_ON, 2872 }; 2873 2874 static struct gdsc oxili_gdsc = { 2875 .gdscr = 0x4024, 2876 .cxcs = (unsigned int []){ 0x4028 }, 2877 .cxc_count = 1, 2878 .pd = { 2879 .name = "oxili", 2880 }, 2881 .pwrsts = PWRSTS_OFF_ON, 2882 }; 2883 2884 static struct gdsc oxilicx_gdsc = { 2885 .gdscr = 0x4034, 2886 .pd = { 2887 .name = "oxilicx", 2888 }, 2889 .pwrsts = PWRSTS_OFF_ON, 2890 }; 2891 2892 static struct clk_regmap *mmcc_apq8084_clocks[] = { 2893 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, 2894 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, 2895 [MMPLL0] = &mmpll0.clkr, 2896 [MMPLL0_VOTE] = &mmpll0_vote, 2897 [MMPLL1] = &mmpll1.clkr, 2898 [MMPLL1_VOTE] = &mmpll1_vote, 2899 [MMPLL2] = &mmpll2.clkr, 2900 [MMPLL3] = &mmpll3.clkr, 2901 [MMPLL4] = &mmpll4.clkr, 2902 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2903 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2904 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2905 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2906 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 2907 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2908 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2909 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2910 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2911 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2912 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, 2913 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2914 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2915 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, 2916 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 2917 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, 2918 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2919 [VP_CLK_SRC] = &vp_clk_src.clkr, 2920 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2921 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2922 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2923 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2924 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2925 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2926 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2927 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2928 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2929 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2930 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2931 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2932 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2933 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, 2934 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, 2935 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2936 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2937 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2938 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2939 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 2940 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 2941 [MAPLE_CLK_SRC] = &maple_clk_src.clkr, 2942 [VDP_CLK_SRC] = &vdp_clk_src.clkr, 2943 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr, 2944 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr, 2945 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr, 2946 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr, 2947 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr, 2948 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr, 2949 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr, 2950 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr, 2951 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr, 2952 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 2953 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, 2954 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, 2955 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2956 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2957 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 2958 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2959 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2960 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2961 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2962 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 2963 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2964 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2965 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2966 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2967 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 2968 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2969 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2970 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2971 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2972 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 2973 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2974 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2975 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2976 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2977 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 2978 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 2979 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2980 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, 2981 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, 2982 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, 2983 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, 2984 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, 2985 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2986 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2987 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2988 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2989 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2990 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, 2991 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, 2992 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, 2993 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2994 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, 2995 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, 2996 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, 2997 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, 2998 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, 2999 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, 3000 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3001 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3002 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3003 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3004 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, 3005 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, 3006 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, 3007 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3008 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3009 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3010 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3011 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3012 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3013 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 3014 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3015 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3016 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3017 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3018 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3019 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3020 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, 3021 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, 3022 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, 3023 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, 3024 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, 3025 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, 3026 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, 3027 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, 3028 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr, 3029 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, 3030 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, 3031 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, 3032 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr, 3033 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr, 3034 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, 3035 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, 3036 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr, 3037 [VPU_AXI_CLK] = &vpu_axi_clk.clkr, 3038 [VPU_BUS_CLK] = &vpu_bus_clk.clkr, 3039 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr, 3040 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr, 3041 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr, 3042 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr, 3043 }; 3044 3045 static const struct qcom_reset_map mmcc_apq8084_resets[] = { 3046 [MMSS_SPDM_RESET] = { 0x0200 }, 3047 [MMSS_SPDM_RM_RESET] = { 0x0300 }, 3048 [VENUS0_RESET] = { 0x1020 }, 3049 [VPU_RESET] = { 0x1400 }, 3050 [MDSS_RESET] = { 0x2300 }, 3051 [AVSYNC_RESET] = { 0x2400 }, 3052 [CAMSS_PHY0_RESET] = { 0x3020 }, 3053 [CAMSS_PHY1_RESET] = { 0x3050 }, 3054 [CAMSS_PHY2_RESET] = { 0x3080 }, 3055 [CAMSS_CSI0_RESET] = { 0x30b0 }, 3056 [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, 3057 [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, 3058 [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, 3059 [CAMSS_CSI1_RESET] = { 0x3120 }, 3060 [CAMSS_CSI1PHY_RESET] = { 0x3130 }, 3061 [CAMSS_CSI1RDI_RESET] = { 0x3140 }, 3062 [CAMSS_CSI1PIX_RESET] = { 0x3150 }, 3063 [CAMSS_CSI2_RESET] = { 0x3180 }, 3064 [CAMSS_CSI2PHY_RESET] = { 0x3190 }, 3065 [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, 3066 [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, 3067 [CAMSS_CSI3_RESET] = { 0x31e0 }, 3068 [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, 3069 [CAMSS_CSI3RDI_RESET] = { 0x3200 }, 3070 [CAMSS_CSI3PIX_RESET] = { 0x3210 }, 3071 [CAMSS_ISPIF_RESET] = { 0x3220 }, 3072 [CAMSS_CCI_RESET] = { 0x3340 }, 3073 [CAMSS_MCLK0_RESET] = { 0x3380 }, 3074 [CAMSS_MCLK1_RESET] = { 0x33b0 }, 3075 [CAMSS_MCLK2_RESET] = { 0x33e0 }, 3076 [CAMSS_MCLK3_RESET] = { 0x3410 }, 3077 [CAMSS_GP0_RESET] = { 0x3440 }, 3078 [CAMSS_GP1_RESET] = { 0x3470 }, 3079 [CAMSS_TOP_RESET] = { 0x3480 }, 3080 [CAMSS_AHB_RESET] = { 0x3488 }, 3081 [CAMSS_MICRO_RESET] = { 0x3490 }, 3082 [CAMSS_JPEG_RESET] = { 0x35a0 }, 3083 [CAMSS_VFE_RESET] = { 0x36a0 }, 3084 [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, 3085 [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, 3086 [OXILI_RESET] = { 0x4020 }, 3087 [OXILICX_RESET] = { 0x4030 }, 3088 [OCMEMCX_RESET] = { 0x4050 }, 3089 [MMSS_RBCRP_RESET] = { 0x4080 }, 3090 [MMSSNOCAHB_RESET] = { 0x5020 }, 3091 [MMSSNOCAXI_RESET] = { 0x5060 }, 3092 }; 3093 3094 static struct gdsc *mmcc_apq8084_gdscs[] = { 3095 [VENUS0_GDSC] = &venus0_gdsc, 3096 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc, 3097 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc, 3098 [MDSS_GDSC] = &mdss_gdsc, 3099 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, 3100 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, 3101 [OXILI_GDSC] = &oxili_gdsc, 3102 [OXILICX_GDSC] = &oxilicx_gdsc, 3103 }; 3104 3105 static const struct regmap_config mmcc_apq8084_regmap_config = { 3106 .reg_bits = 32, 3107 .reg_stride = 4, 3108 .val_bits = 32, 3109 .max_register = 0x5104, 3110 .fast_io = true, 3111 }; 3112 3113 static const struct qcom_cc_desc mmcc_apq8084_desc = { 3114 .config = &mmcc_apq8084_regmap_config, 3115 .clks = mmcc_apq8084_clocks, 3116 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks), 3117 .resets = mmcc_apq8084_resets, 3118 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets), 3119 .gdscs = mmcc_apq8084_gdscs, 3120 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs), 3121 }; 3122 3123 static const struct of_device_id mmcc_apq8084_match_table[] = { 3124 { .compatible = "qcom,mmcc-apq8084" }, 3125 { } 3126 }; 3127 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table); 3128 3129 static int mmcc_apq8084_probe(struct platform_device *pdev) 3130 { 3131 int ret; 3132 struct regmap *regmap; 3133 3134 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc); 3135 if (ret) 3136 return ret; 3137 3138 regmap = dev_get_regmap(&pdev->dev, NULL); 3139 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 3140 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 3141 3142 return 0; 3143 } 3144 3145 static struct platform_driver mmcc_apq8084_driver = { 3146 .probe = mmcc_apq8084_probe, 3147 .driver = { 3148 .name = "mmcc-apq8084", 3149 .of_match_table = mmcc_apq8084_match_table, 3150 }, 3151 }; 3152 module_platform_driver(mmcc_apq8084_driver); 3153 3154 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver"); 3155 MODULE_LICENSE("GPL v2"); 3156 MODULE_ALIAS("platform:mmcc-apq8084"); 3157