1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,mmcc-apq8084.h> 13 #include <dt-bindings/reset/qcom,mmcc-apq8084.h> 14 15 #include "common.h" 16 #include "clk-regmap.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-branch.h" 20 #include "reset.h" 21 #include "gdsc.h" 22 23 enum { 24 P_XO, 25 P_MMPLL0, 26 P_EDPLINK, 27 P_MMPLL1, 28 P_HDMIPLL, 29 P_GPLL0, 30 P_EDPVCO, 31 P_MMPLL4, 32 P_DSI0PLL, 33 P_DSI0PLL_BYTE, 34 P_MMPLL2, 35 P_MMPLL3, 36 P_GPLL1, 37 P_DSI1PLL, 38 P_DSI1PLL_BYTE, 39 P_MMSLEEP, 40 }; 41 42 static struct clk_pll mmpll0 = { 43 .l_reg = 0x0004, 44 .m_reg = 0x0008, 45 .n_reg = 0x000c, 46 .config_reg = 0x0014, 47 .mode_reg = 0x0000, 48 .status_reg = 0x001c, 49 .status_bit = 17, 50 .clkr.hw.init = &(struct clk_init_data){ 51 .name = "mmpll0", 52 .parent_data = (const struct clk_parent_data[]){ 53 { .fw_name = "xo", .name = "xo_board" }, 54 }, 55 .num_parents = 1, 56 .ops = &clk_pll_ops, 57 }, 58 }; 59 60 static struct clk_regmap mmpll0_vote = { 61 .enable_reg = 0x0100, 62 .enable_mask = BIT(0), 63 .hw.init = &(struct clk_init_data){ 64 .name = "mmpll0_vote", 65 .parent_hws = (const struct clk_hw*[]){ 66 &mmpll0.clkr.hw 67 }, 68 .num_parents = 1, 69 .ops = &clk_pll_vote_ops, 70 }, 71 }; 72 73 static struct clk_pll mmpll1 = { 74 .l_reg = 0x0044, 75 .m_reg = 0x0048, 76 .n_reg = 0x004c, 77 .config_reg = 0x0050, 78 .mode_reg = 0x0040, 79 .status_reg = 0x005c, 80 .status_bit = 17, 81 .clkr.hw.init = &(struct clk_init_data){ 82 .name = "mmpll1", 83 .parent_data = (const struct clk_parent_data[]){ 84 { .fw_name = "xo", .name = "xo_board" }, 85 }, 86 .num_parents = 1, 87 .ops = &clk_pll_ops, 88 }, 89 }; 90 91 static struct clk_regmap mmpll1_vote = { 92 .enable_reg = 0x0100, 93 .enable_mask = BIT(1), 94 .hw.init = &(struct clk_init_data){ 95 .name = "mmpll1_vote", 96 .parent_hws = (const struct clk_hw*[]){ 97 &mmpll1.clkr.hw 98 }, 99 .num_parents = 1, 100 .ops = &clk_pll_vote_ops, 101 }, 102 }; 103 104 static struct clk_pll mmpll2 = { 105 .l_reg = 0x4104, 106 .m_reg = 0x4108, 107 .n_reg = 0x410c, 108 .config_reg = 0x4110, 109 .mode_reg = 0x4100, 110 .status_reg = 0x411c, 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "mmpll2", 113 .parent_data = (const struct clk_parent_data[]){ 114 { .fw_name = "xo", .name = "xo_board" }, 115 }, 116 .num_parents = 1, 117 .ops = &clk_pll_ops, 118 }, 119 }; 120 121 static struct clk_pll mmpll3 = { 122 .l_reg = 0x0084, 123 .m_reg = 0x0088, 124 .n_reg = 0x008c, 125 .config_reg = 0x0090, 126 .mode_reg = 0x0080, 127 .status_reg = 0x009c, 128 .status_bit = 17, 129 .clkr.hw.init = &(struct clk_init_data){ 130 .name = "mmpll3", 131 .parent_data = (const struct clk_parent_data[]){ 132 { .fw_name = "xo", .name = "xo_board" }, 133 }, 134 .num_parents = 1, 135 .ops = &clk_pll_ops, 136 }, 137 }; 138 139 static struct clk_pll mmpll4 = { 140 .l_reg = 0x00a4, 141 .m_reg = 0x00a8, 142 .n_reg = 0x00ac, 143 .config_reg = 0x00b0, 144 .mode_reg = 0x0080, 145 .status_reg = 0x00bc, 146 .clkr.hw.init = &(struct clk_init_data){ 147 .name = "mmpll4", 148 .parent_data = (const struct clk_parent_data[]){ 149 { .fw_name = "xo", .name = "xo_board" }, 150 }, 151 .num_parents = 1, 152 .ops = &clk_pll_ops, 153 }, 154 }; 155 156 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 157 { P_XO, 0 }, 158 { P_MMPLL0, 1 }, 159 { P_MMPLL1, 2 }, 160 { P_GPLL0, 5 } 161 }; 162 163 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = { 164 { .fw_name = "xo", .name = "xo_board" }, 165 { .hw = &mmpll0_vote.hw }, 166 { .hw = &mmpll1_vote.hw }, 167 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 168 }; 169 170 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 171 { P_XO, 0 }, 172 { P_MMPLL0, 1 }, 173 { P_HDMIPLL, 4 }, 174 { P_GPLL0, 5 }, 175 { P_DSI0PLL, 2 }, 176 { P_DSI1PLL, 3 } 177 }; 178 179 static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 180 { .fw_name = "xo", .name = "xo_board" }, 181 { .hw = &mmpll0_vote.hw }, 182 { .fw_name = "hdmipll", .name = "hdmipll" }, 183 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 184 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 185 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 186 }; 187 188 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { 189 { P_XO, 0 }, 190 { P_MMPLL0, 1 }, 191 { P_MMPLL1, 2 }, 192 { P_GPLL0, 5 }, 193 { P_MMPLL2, 3 } 194 }; 195 196 static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = { 197 { .fw_name = "xo", .name = "xo_board" }, 198 { .hw = &mmpll0_vote.hw }, 199 { .hw = &mmpll1_vote.hw }, 200 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 201 { .hw = &mmpll2.clkr.hw }, 202 }; 203 204 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { 205 { P_XO, 0 }, 206 { P_MMPLL0, 1 }, 207 { P_MMPLL1, 2 }, 208 { P_GPLL0, 5 }, 209 { P_MMPLL3, 3 } 210 }; 211 212 static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = { 213 { .fw_name = "xo", .name = "xo_board" }, 214 { .hw = &mmpll0_vote.hw }, 215 { .hw = &mmpll1_vote.hw }, 216 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, 217 { .hw = &mmpll3.clkr.hw }, 218 }; 219 220 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { 221 { P_XO, 0 }, 222 { P_EDPLINK, 4 }, 223 { P_HDMIPLL, 3 }, 224 { P_EDPVCO, 5 }, 225 { P_DSI0PLL, 1 }, 226 { P_DSI1PLL, 2 } 227 }; 228 229 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = { 230 { .fw_name = "xo", .name = "xo_board" }, 231 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 232 { .fw_name = "hdmipll", .name = "hdmipll" }, 233 { .fw_name = "edp_vco_div", .name = "edp_vco_div" }, 234 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 235 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 236 }; 237 238 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 239 { P_XO, 0 }, 240 { P_EDPLINK, 4 }, 241 { P_HDMIPLL, 3 }, 242 { P_GPLL0, 5 }, 243 { P_DSI0PLL, 1 }, 244 { P_DSI1PLL, 2 } 245 }; 246 247 static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = { 248 { .fw_name = "xo", .name = "xo_board" }, 249 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 250 { .fw_name = "hdmipll", .name = "hdmipll" }, 251 { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, 252 { .fw_name = "dsi0pll", .name = "dsi0pll" }, 253 { .fw_name = "dsi1pll", .name = "dsi1pll" }, 254 }; 255 256 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 257 { P_XO, 0 }, 258 { P_EDPLINK, 4 }, 259 { P_HDMIPLL, 3 }, 260 { P_GPLL0, 5 }, 261 { P_DSI0PLL_BYTE, 1 }, 262 { P_DSI1PLL_BYTE, 2 } 263 }; 264 265 static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 266 { .fw_name = "xo", .name = "xo_board" }, 267 { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, 268 { .fw_name = "hdmipll", .name = "hdmipll" }, 269 { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, 270 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 271 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }, 272 }; 273 274 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { 275 { P_XO, 0 }, 276 { P_MMPLL0, 1 }, 277 { P_MMPLL1, 2 }, 278 { P_GPLL0, 5 }, 279 { P_MMPLL4, 3 } 280 }; 281 282 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = { 283 { .fw_name = "xo", .name = "xo_board" }, 284 { .hw = &mmpll0.clkr.hw }, 285 { .hw = &mmpll1.clkr.hw }, 286 { .hw = &mmpll4.clkr.hw }, 287 { .fw_name = "gpll0", .name = "gpll0" }, 288 }; 289 290 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { 291 { P_XO, 0 }, 292 { P_MMPLL0, 1 }, 293 { P_MMPLL1, 2 }, 294 { P_MMPLL4, 3 }, 295 { P_GPLL0, 5 }, 296 { P_GPLL1, 4 } 297 }; 298 299 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = { 300 { .fw_name = "xo", .name = "xo_board" }, 301 { .hw = &mmpll0.clkr.hw }, 302 { .hw = &mmpll1.clkr.hw }, 303 { .hw = &mmpll4.clkr.hw }, 304 { .fw_name = "gpll1", .name = "gpll1" }, 305 { .fw_name = "gpll0", .name = "gpll0" }, 306 }; 307 308 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { 309 { P_XO, 0 }, 310 { P_MMPLL0, 1 }, 311 { P_MMPLL1, 2 }, 312 { P_MMPLL4, 3 }, 313 { P_GPLL0, 5 }, 314 { P_GPLL1, 4 }, 315 { P_MMSLEEP, 6 } 316 }; 317 318 static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 319 { .fw_name = "xo", .name = "xo_board" }, 320 { .hw = &mmpll0.clkr.hw }, 321 { .hw = &mmpll1.clkr.hw }, 322 { .hw = &mmpll4.clkr.hw }, 323 { .fw_name = "gpll1", .name = "gpll1" }, 324 { .fw_name = "gpll0", .name = "gpll0" }, 325 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 326 }; 327 328 static struct clk_rcg2 mmss_ahb_clk_src = { 329 .cmd_rcgr = 0x5000, 330 .hid_width = 5, 331 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 332 .clkr.hw.init = &(struct clk_init_data){ 333 .name = "mmss_ahb_clk_src", 334 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 335 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 336 .ops = &clk_rcg2_ops, 337 }, 338 }; 339 340 static const struct freq_tbl ftbl_mmss_axi_clk[] = { 341 F(19200000, P_XO, 1, 0, 0), 342 F(37500000, P_GPLL0, 16, 0, 0), 343 F(50000000, P_GPLL0, 12, 0, 0), 344 F(75000000, P_GPLL0, 8, 0, 0), 345 F(100000000, P_GPLL0, 6, 0, 0), 346 F(150000000, P_GPLL0, 4, 0, 0), 347 F(333430000, P_MMPLL1, 3.5, 0, 0), 348 F(400000000, P_MMPLL0, 2, 0, 0), 349 F(466800000, P_MMPLL1, 2.5, 0, 0), 350 { } 351 }; 352 353 static struct clk_rcg2 mmss_axi_clk_src = { 354 .cmd_rcgr = 0x5040, 355 .hid_width = 5, 356 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 357 .freq_tbl = ftbl_mmss_axi_clk, 358 .clkr.hw.init = &(struct clk_init_data){ 359 .name = "mmss_axi_clk_src", 360 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 361 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 362 .ops = &clk_rcg2_ops, 363 }, 364 }; 365 366 static const struct freq_tbl ftbl_ocmemnoc_clk[] = { 367 F(19200000, P_XO, 1, 0, 0), 368 F(37500000, P_GPLL0, 16, 0, 0), 369 F(50000000, P_GPLL0, 12, 0, 0), 370 F(75000000, P_GPLL0, 8, 0, 0), 371 F(109090000, P_GPLL0, 5.5, 0, 0), 372 F(150000000, P_GPLL0, 4, 0, 0), 373 F(228570000, P_MMPLL0, 3.5, 0, 0), 374 F(320000000, P_MMPLL0, 2.5, 0, 0), 375 { } 376 }; 377 378 static struct clk_rcg2 ocmemnoc_clk_src = { 379 .cmd_rcgr = 0x5090, 380 .hid_width = 5, 381 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 382 .freq_tbl = ftbl_ocmemnoc_clk, 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "ocmemnoc_clk_src", 385 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 386 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 387 .ops = &clk_rcg2_ops, 388 }, 389 }; 390 391 static const struct freq_tbl ftbl_camss_csi0_3_clk[] = { 392 F(100000000, P_GPLL0, 6, 0, 0), 393 F(200000000, P_MMPLL0, 4, 0, 0), 394 { } 395 }; 396 397 static struct clk_rcg2 csi0_clk_src = { 398 .cmd_rcgr = 0x3090, 399 .hid_width = 5, 400 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 401 .freq_tbl = ftbl_camss_csi0_3_clk, 402 .clkr.hw.init = &(struct clk_init_data){ 403 .name = "csi0_clk_src", 404 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 405 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 406 .ops = &clk_rcg2_ops, 407 }, 408 }; 409 410 static struct clk_rcg2 csi1_clk_src = { 411 .cmd_rcgr = 0x3100, 412 .hid_width = 5, 413 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 414 .freq_tbl = ftbl_camss_csi0_3_clk, 415 .clkr.hw.init = &(struct clk_init_data){ 416 .name = "csi1_clk_src", 417 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 418 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 419 .ops = &clk_rcg2_ops, 420 }, 421 }; 422 423 static struct clk_rcg2 csi2_clk_src = { 424 .cmd_rcgr = 0x3160, 425 .hid_width = 5, 426 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 427 .freq_tbl = ftbl_camss_csi0_3_clk, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "csi2_clk_src", 430 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 431 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 432 .ops = &clk_rcg2_ops, 433 }, 434 }; 435 436 static struct clk_rcg2 csi3_clk_src = { 437 .cmd_rcgr = 0x31c0, 438 .hid_width = 5, 439 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 440 .freq_tbl = ftbl_camss_csi0_3_clk, 441 .clkr.hw.init = &(struct clk_init_data){ 442 .name = "csi3_clk_src", 443 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 444 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 445 .ops = &clk_rcg2_ops, 446 }, 447 }; 448 449 static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { 450 F(37500000, P_GPLL0, 16, 0, 0), 451 F(50000000, P_GPLL0, 12, 0, 0), 452 F(60000000, P_GPLL0, 10, 0, 0), 453 F(80000000, P_GPLL0, 7.5, 0, 0), 454 F(100000000, P_GPLL0, 6, 0, 0), 455 F(109090000, P_GPLL0, 5.5, 0, 0), 456 F(133330000, P_GPLL0, 4.5, 0, 0), 457 F(200000000, P_GPLL0, 3, 0, 0), 458 F(228570000, P_MMPLL0, 3.5, 0, 0), 459 F(266670000, P_MMPLL0, 3, 0, 0), 460 F(320000000, P_MMPLL0, 2.5, 0, 0), 461 F(465000000, P_MMPLL4, 2, 0, 0), 462 F(600000000, P_GPLL0, 1, 0, 0), 463 { } 464 }; 465 466 static struct clk_rcg2 vfe0_clk_src = { 467 .cmd_rcgr = 0x3600, 468 .hid_width = 5, 469 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 470 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 471 .clkr.hw.init = &(struct clk_init_data){ 472 .name = "vfe0_clk_src", 473 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 474 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 475 .ops = &clk_rcg2_ops, 476 }, 477 }; 478 479 static struct clk_rcg2 vfe1_clk_src = { 480 .cmd_rcgr = 0x3620, 481 .hid_width = 5, 482 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 483 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, 484 .clkr.hw.init = &(struct clk_init_data){ 485 .name = "vfe1_clk_src", 486 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 487 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 488 .ops = &clk_rcg2_ops, 489 }, 490 }; 491 492 static const struct freq_tbl ftbl_mdss_mdp_clk[] = { 493 F(37500000, P_GPLL0, 16, 0, 0), 494 F(60000000, P_GPLL0, 10, 0, 0), 495 F(75000000, P_GPLL0, 8, 0, 0), 496 F(85710000, P_GPLL0, 7, 0, 0), 497 F(100000000, P_GPLL0, 6, 0, 0), 498 F(150000000, P_GPLL0, 4, 0, 0), 499 F(160000000, P_MMPLL0, 5, 0, 0), 500 F(200000000, P_MMPLL0, 4, 0, 0), 501 F(228570000, P_MMPLL0, 3.5, 0, 0), 502 F(300000000, P_GPLL0, 2, 0, 0), 503 F(320000000, P_MMPLL0, 2.5, 0, 0), 504 { } 505 }; 506 507 static struct clk_rcg2 mdp_clk_src = { 508 .cmd_rcgr = 0x2040, 509 .hid_width = 5, 510 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, 511 .freq_tbl = ftbl_mdss_mdp_clk, 512 .clkr.hw.init = &(struct clk_init_data){ 513 .name = "mdp_clk_src", 514 .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0, 515 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), 516 .ops = &clk_rcg2_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 gfx3d_clk_src = { 521 .cmd_rcgr = 0x4000, 522 .hid_width = 5, 523 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, 524 .clkr.hw.init = &(struct clk_init_data){ 525 .name = "gfx3d_clk_src", 526 .parent_data = mmcc_xo_mmpll0_1_2_gpll0, 527 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0), 528 .ops = &clk_rcg2_ops, 529 }, 530 }; 531 532 static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { 533 F(75000000, P_GPLL0, 8, 0, 0), 534 F(133330000, P_GPLL0, 4.5, 0, 0), 535 F(200000000, P_GPLL0, 3, 0, 0), 536 F(228570000, P_MMPLL0, 3.5, 0, 0), 537 F(266670000, P_MMPLL0, 3, 0, 0), 538 F(320000000, P_MMPLL0, 2.5, 0, 0), 539 { } 540 }; 541 542 static struct clk_rcg2 jpeg0_clk_src = { 543 .cmd_rcgr = 0x3500, 544 .hid_width = 5, 545 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 546 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 547 .clkr.hw.init = &(struct clk_init_data){ 548 .name = "jpeg0_clk_src", 549 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 550 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 551 .ops = &clk_rcg2_ops, 552 }, 553 }; 554 555 static struct clk_rcg2 jpeg1_clk_src = { 556 .cmd_rcgr = 0x3520, 557 .hid_width = 5, 558 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 559 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 560 .clkr.hw.init = &(struct clk_init_data){ 561 .name = "jpeg1_clk_src", 562 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 563 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 564 .ops = &clk_rcg2_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 jpeg2_clk_src = { 569 .cmd_rcgr = 0x3540, 570 .hid_width = 5, 571 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 572 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, 573 .clkr.hw.init = &(struct clk_init_data){ 574 .name = "jpeg2_clk_src", 575 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 576 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 577 .ops = &clk_rcg2_ops, 578 }, 579 }; 580 581 static struct clk_rcg2 pclk0_clk_src = { 582 .cmd_rcgr = 0x2000, 583 .mnd_width = 8, 584 .hid_width = 5, 585 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 586 .clkr.hw.init = &(struct clk_init_data){ 587 .name = "pclk0_clk_src", 588 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 589 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 590 .ops = &clk_pixel_ops, 591 .flags = CLK_SET_RATE_PARENT, 592 }, 593 }; 594 595 static struct clk_rcg2 pclk1_clk_src = { 596 .cmd_rcgr = 0x2020, 597 .mnd_width = 8, 598 .hid_width = 5, 599 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 600 .clkr.hw.init = &(struct clk_init_data){ 601 .name = "pclk1_clk_src", 602 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 603 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 604 .ops = &clk_pixel_ops, 605 .flags = CLK_SET_RATE_PARENT, 606 }, 607 }; 608 609 static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = { 610 F(50000000, P_GPLL0, 12, 0, 0), 611 F(100000000, P_GPLL0, 6, 0, 0), 612 F(133330000, P_GPLL0, 4.5, 0, 0), 613 F(200000000, P_MMPLL0, 4, 0, 0), 614 F(266670000, P_MMPLL0, 3, 0, 0), 615 F(465000000, P_MMPLL3, 2, 0, 0), 616 { } 617 }; 618 619 static struct clk_rcg2 vcodec0_clk_src = { 620 .cmd_rcgr = 0x1000, 621 .mnd_width = 8, 622 .hid_width = 5, 623 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, 624 .freq_tbl = ftbl_venus0_vcodec0_clk, 625 .clkr.hw.init = &(struct clk_init_data){ 626 .name = "vcodec0_clk_src", 627 .parent_data = mmcc_xo_mmpll0_1_3_gpll0, 628 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), 629 .ops = &clk_rcg2_ops, 630 }, 631 }; 632 633 static const struct freq_tbl ftbl_avsync_vp_clk[] = { 634 F(150000000, P_GPLL0, 4, 0, 0), 635 F(320000000, P_MMPLL0, 2.5, 0, 0), 636 { } 637 }; 638 639 static struct clk_rcg2 vp_clk_src = { 640 .cmd_rcgr = 0x2430, 641 .hid_width = 5, 642 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 643 .freq_tbl = ftbl_avsync_vp_clk, 644 .clkr.hw.init = &(struct clk_init_data){ 645 .name = "vp_clk_src", 646 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 647 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static const struct freq_tbl ftbl_camss_cci_cci_clk[] = { 653 F(19200000, P_XO, 1, 0, 0), 654 { } 655 }; 656 657 static struct clk_rcg2 cci_clk_src = { 658 .cmd_rcgr = 0x3300, 659 .mnd_width = 8, 660 .hid_width = 5, 661 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 662 .freq_tbl = ftbl_camss_cci_cci_clk, 663 .clkr.hw.init = &(struct clk_init_data){ 664 .name = "cci_clk_src", 665 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 666 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 667 .ops = &clk_rcg2_ops, 668 }, 669 }; 670 671 static const struct freq_tbl ftbl_camss_gp0_1_clk[] = { 672 F(10000, P_XO, 16, 1, 120), 673 F(24000, P_XO, 16, 1, 50), 674 F(6000000, P_GPLL0, 10, 1, 10), 675 F(12000000, P_GPLL0, 10, 1, 5), 676 F(13000000, P_GPLL0, 4, 13, 150), 677 F(24000000, P_GPLL0, 5, 1, 5), 678 { } 679 }; 680 681 static struct clk_rcg2 camss_gp0_clk_src = { 682 .cmd_rcgr = 0x3420, 683 .mnd_width = 8, 684 .hid_width = 5, 685 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 686 .freq_tbl = ftbl_camss_gp0_1_clk, 687 .clkr.hw.init = &(struct clk_init_data){ 688 .name = "camss_gp0_clk_src", 689 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 690 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep), 691 .ops = &clk_rcg2_ops, 692 }, 693 }; 694 695 static struct clk_rcg2 camss_gp1_clk_src = { 696 .cmd_rcgr = 0x3450, 697 .mnd_width = 8, 698 .hid_width = 5, 699 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map, 700 .freq_tbl = ftbl_camss_gp0_1_clk, 701 .clkr.hw.init = &(struct clk_init_data){ 702 .name = "camss_gp1_clk_src", 703 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep, 704 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep), 705 .ops = &clk_rcg2_ops, 706 }, 707 }; 708 709 static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = { 710 F(4800000, P_XO, 4, 0, 0), 711 F(6000000, P_GPLL0, 10, 1, 10), 712 F(8000000, P_GPLL0, 15, 1, 5), 713 F(9600000, P_XO, 2, 0, 0), 714 F(16000000, P_MMPLL0, 10, 1, 5), 715 F(19200000, P_XO, 1, 0, 0), 716 F(24000000, P_GPLL0, 5, 1, 5), 717 F(32000000, P_MMPLL0, 5, 1, 5), 718 F(48000000, P_GPLL0, 12.5, 0, 0), 719 F(64000000, P_MMPLL0, 12.5, 0, 0), 720 { } 721 }; 722 723 static struct clk_rcg2 mclk0_clk_src = { 724 .cmd_rcgr = 0x3360, 725 .mnd_width = 8, 726 .hid_width = 5, 727 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 728 .freq_tbl = ftbl_camss_mclk0_3_clk, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "mclk0_clk_src", 731 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 732 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 733 .ops = &clk_rcg2_ops, 734 }, 735 }; 736 737 static struct clk_rcg2 mclk1_clk_src = { 738 .cmd_rcgr = 0x3390, 739 .mnd_width = 8, 740 .hid_width = 5, 741 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 742 .freq_tbl = ftbl_camss_mclk0_3_clk, 743 .clkr.hw.init = &(struct clk_init_data){ 744 .name = "mclk1_clk_src", 745 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 746 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 747 .ops = &clk_rcg2_ops, 748 }, 749 }; 750 751 static struct clk_rcg2 mclk2_clk_src = { 752 .cmd_rcgr = 0x33c0, 753 .mnd_width = 8, 754 .hid_width = 5, 755 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 756 .freq_tbl = ftbl_camss_mclk0_3_clk, 757 .clkr.hw.init = &(struct clk_init_data){ 758 .name = "mclk2_clk_src", 759 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 760 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 761 .ops = &clk_rcg2_ops, 762 }, 763 }; 764 765 static struct clk_rcg2 mclk3_clk_src = { 766 .cmd_rcgr = 0x33f0, 767 .mnd_width = 8, 768 .hid_width = 5, 769 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map, 770 .freq_tbl = ftbl_camss_mclk0_3_clk, 771 .clkr.hw.init = &(struct clk_init_data){ 772 .name = "mclk3_clk_src", 773 .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0, 774 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0), 775 .ops = &clk_rcg2_ops, 776 }, 777 }; 778 779 static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { 780 F(100000000, P_GPLL0, 6, 0, 0), 781 F(200000000, P_MMPLL0, 4, 0, 0), 782 { } 783 }; 784 785 static struct clk_rcg2 csi0phytimer_clk_src = { 786 .cmd_rcgr = 0x3000, 787 .hid_width = 5, 788 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 789 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 790 .clkr.hw.init = &(struct clk_init_data){ 791 .name = "csi0phytimer_clk_src", 792 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 793 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 794 .ops = &clk_rcg2_ops, 795 }, 796 }; 797 798 static struct clk_rcg2 csi1phytimer_clk_src = { 799 .cmd_rcgr = 0x3030, 800 .hid_width = 5, 801 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 802 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 803 .clkr.hw.init = &(struct clk_init_data){ 804 .name = "csi1phytimer_clk_src", 805 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 806 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 807 .ops = &clk_rcg2_ops, 808 }, 809 }; 810 811 static struct clk_rcg2 csi2phytimer_clk_src = { 812 .cmd_rcgr = 0x3060, 813 .hid_width = 5, 814 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 815 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "csi2phytimer_clk_src", 818 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 819 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 820 .ops = &clk_rcg2_ops, 821 }, 822 }; 823 824 static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { 825 F(133330000, P_GPLL0, 4.5, 0, 0), 826 F(266670000, P_MMPLL0, 3, 0, 0), 827 F(320000000, P_MMPLL0, 2.5, 0, 0), 828 F(372000000, P_MMPLL4, 2.5, 0, 0), 829 F(465000000, P_MMPLL4, 2, 0, 0), 830 F(600000000, P_GPLL0, 1, 0, 0), 831 { } 832 }; 833 834 static struct clk_rcg2 cpp_clk_src = { 835 .cmd_rcgr = 0x3640, 836 .hid_width = 5, 837 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map, 838 .freq_tbl = ftbl_camss_vfe_cpp_clk, 839 .clkr.hw.init = &(struct clk_init_data){ 840 .name = "cpp_clk_src", 841 .parent_data = mmcc_xo_mmpll0_1_4_gpll0, 842 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0), 843 .ops = &clk_rcg2_ops, 844 }, 845 }; 846 847 static struct clk_rcg2 byte0_clk_src = { 848 .cmd_rcgr = 0x2120, 849 .hid_width = 5, 850 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 851 .clkr.hw.init = &(struct clk_init_data){ 852 .name = "byte0_clk_src", 853 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 854 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 855 .ops = &clk_byte2_ops, 856 .flags = CLK_SET_RATE_PARENT, 857 }, 858 }; 859 860 static struct clk_rcg2 byte1_clk_src = { 861 .cmd_rcgr = 0x2140, 862 .hid_width = 5, 863 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 864 .clkr.hw.init = &(struct clk_init_data){ 865 .name = "byte1_clk_src", 866 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 867 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 868 .ops = &clk_byte2_ops, 869 .flags = CLK_SET_RATE_PARENT, 870 }, 871 }; 872 873 static const struct freq_tbl ftbl_mdss_edpaux_clk[] = { 874 F(19200000, P_XO, 1, 0, 0), 875 { } 876 }; 877 878 static struct clk_rcg2 edpaux_clk_src = { 879 .cmd_rcgr = 0x20e0, 880 .hid_width = 5, 881 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 882 .freq_tbl = ftbl_mdss_edpaux_clk, 883 .clkr.hw.init = &(struct clk_init_data){ 884 .name = "edpaux_clk_src", 885 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 886 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 887 .ops = &clk_rcg2_ops, 888 }, 889 }; 890 891 static const struct freq_tbl ftbl_mdss_edplink_clk[] = { 892 F(135000000, P_EDPLINK, 2, 0, 0), 893 F(270000000, P_EDPLINK, 11, 0, 0), 894 { } 895 }; 896 897 static struct clk_rcg2 edplink_clk_src = { 898 .cmd_rcgr = 0x20c0, 899 .hid_width = 5, 900 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 901 .freq_tbl = ftbl_mdss_edplink_clk, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "edplink_clk_src", 904 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 905 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 906 .ops = &clk_rcg2_ops, 907 .flags = CLK_SET_RATE_PARENT, 908 }, 909 }; 910 911 static const struct freq_tbl edp_pixel_freq_tbl[] = { 912 { .src = P_EDPVCO }, 913 { } 914 }; 915 916 static struct clk_rcg2 edppixel_clk_src = { 917 .cmd_rcgr = 0x20a0, 918 .mnd_width = 8, 919 .hid_width = 5, 920 .parent_map = mmcc_xo_dsi_hdmi_edp_map, 921 .freq_tbl = edp_pixel_freq_tbl, 922 .clkr.hw.init = &(struct clk_init_data){ 923 .name = "edppixel_clk_src", 924 .parent_data = mmcc_xo_dsi_hdmi_edp, 925 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), 926 .ops = &clk_edp_pixel_ops, 927 }, 928 }; 929 930 static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = { 931 F(19200000, P_XO, 1, 0, 0), 932 { } 933 }; 934 935 static struct clk_rcg2 esc0_clk_src = { 936 .cmd_rcgr = 0x2160, 937 .hid_width = 5, 938 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 939 .freq_tbl = ftbl_mdss_esc0_1_clk, 940 .clkr.hw.init = &(struct clk_init_data){ 941 .name = "esc0_clk_src", 942 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 943 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 944 .ops = &clk_rcg2_ops, 945 }, 946 }; 947 948 static struct clk_rcg2 esc1_clk_src = { 949 .cmd_rcgr = 0x2180, 950 .hid_width = 5, 951 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, 952 .freq_tbl = ftbl_mdss_esc0_1_clk, 953 .clkr.hw.init = &(struct clk_init_data){ 954 .name = "esc1_clk_src", 955 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, 956 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static const struct freq_tbl extpclk_freq_tbl[] = { 962 { .src = P_HDMIPLL }, 963 { } 964 }; 965 966 static struct clk_rcg2 extpclk_clk_src = { 967 .cmd_rcgr = 0x2060, 968 .hid_width = 5, 969 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, 970 .freq_tbl = extpclk_freq_tbl, 971 .clkr.hw.init = &(struct clk_init_data){ 972 .name = "extpclk_clk_src", 973 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, 974 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), 975 .ops = &clk_byte_ops, 976 .flags = CLK_SET_RATE_PARENT, 977 }, 978 }; 979 980 static const struct freq_tbl ftbl_mdss_hdmi_clk[] = { 981 F(19200000, P_XO, 1, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 hdmi_clk_src = { 986 .cmd_rcgr = 0x2100, 987 .hid_width = 5, 988 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 989 .freq_tbl = ftbl_mdss_hdmi_clk, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "hdmi_clk_src", 992 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 993 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 994 .ops = &clk_rcg2_ops, 995 }, 996 }; 997 998 static const struct freq_tbl ftbl_mdss_vsync_clk[] = { 999 F(19200000, P_XO, 1, 0, 0), 1000 { } 1001 }; 1002 1003 static struct clk_rcg2 vsync_clk_src = { 1004 .cmd_rcgr = 0x2080, 1005 .hid_width = 5, 1006 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1007 .freq_tbl = ftbl_mdss_vsync_clk, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "vsync_clk_src", 1010 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1011 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1012 .ops = &clk_rcg2_ops, 1013 }, 1014 }; 1015 1016 static const struct freq_tbl ftbl_mmss_rbcpr_clk[] = { 1017 F(50000000, P_GPLL0, 12, 0, 0), 1018 { } 1019 }; 1020 1021 static struct clk_rcg2 rbcpr_clk_src = { 1022 .cmd_rcgr = 0x4060, 1023 .hid_width = 5, 1024 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1025 .freq_tbl = ftbl_mmss_rbcpr_clk, 1026 .clkr.hw.init = &(struct clk_init_data){ 1027 .name = "rbcpr_clk_src", 1028 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1029 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1030 .ops = &clk_rcg2_ops, 1031 }, 1032 }; 1033 1034 static const struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = { 1035 F(19200000, P_XO, 1, 0, 0), 1036 { } 1037 }; 1038 1039 static struct clk_rcg2 rbbmtimer_clk_src = { 1040 .cmd_rcgr = 0x4090, 1041 .hid_width = 5, 1042 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1043 .freq_tbl = ftbl_oxili_rbbmtimer_clk, 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 .name = "rbbmtimer_clk_src", 1046 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1047 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1048 .ops = &clk_rcg2_ops, 1049 }, 1050 }; 1051 1052 static const struct freq_tbl ftbl_vpu_maple_clk[] = { 1053 F(50000000, P_GPLL0, 12, 0, 0), 1054 F(100000000, P_GPLL0, 6, 0, 0), 1055 F(133330000, P_GPLL0, 4.5, 0, 0), 1056 F(200000000, P_MMPLL0, 4, 0, 0), 1057 F(266670000, P_MMPLL0, 3, 0, 0), 1058 F(465000000, P_MMPLL3, 2, 0, 0), 1059 { } 1060 }; 1061 1062 static struct clk_rcg2 maple_clk_src = { 1063 .cmd_rcgr = 0x1320, 1064 .hid_width = 5, 1065 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1066 .freq_tbl = ftbl_vpu_maple_clk, 1067 .clkr.hw.init = &(struct clk_init_data){ 1068 .name = "maple_clk_src", 1069 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1070 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1071 .ops = &clk_rcg2_ops, 1072 }, 1073 }; 1074 1075 static const struct freq_tbl ftbl_vpu_vdp_clk[] = { 1076 F(50000000, P_GPLL0, 12, 0, 0), 1077 F(100000000, P_GPLL0, 6, 0, 0), 1078 F(200000000, P_MMPLL0, 4, 0, 0), 1079 F(320000000, P_MMPLL0, 2.5, 0, 0), 1080 F(400000000, P_MMPLL0, 2, 0, 0), 1081 { } 1082 }; 1083 1084 static struct clk_rcg2 vdp_clk_src = { 1085 .cmd_rcgr = 0x1300, 1086 .hid_width = 5, 1087 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1088 .freq_tbl = ftbl_vpu_vdp_clk, 1089 .clkr.hw.init = &(struct clk_init_data){ 1090 .name = "vdp_clk_src", 1091 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1092 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1093 .ops = &clk_rcg2_ops, 1094 }, 1095 }; 1096 1097 static const struct freq_tbl ftbl_vpu_bus_clk[] = { 1098 F(40000000, P_GPLL0, 15, 0, 0), 1099 F(80000000, P_MMPLL0, 10, 0, 0), 1100 { } 1101 }; 1102 1103 static struct clk_rcg2 vpu_bus_clk_src = { 1104 .cmd_rcgr = 0x1340, 1105 .hid_width = 5, 1106 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, 1107 .freq_tbl = ftbl_vpu_bus_clk, 1108 .clkr.hw.init = &(struct clk_init_data){ 1109 .name = "vpu_bus_clk_src", 1110 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, 1111 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), 1112 .ops = &clk_rcg2_ops, 1113 }, 1114 }; 1115 1116 static struct clk_branch mmss_cxo_clk = { 1117 .halt_reg = 0x5104, 1118 .clkr = { 1119 .enable_reg = 0x5104, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(struct clk_init_data){ 1122 .name = "mmss_cxo_clk", 1123 .parent_data = (const struct clk_parent_data[]){ 1124 { .fw_name = "xo", .name = "xo_board" }, 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_branch2_ops, 1129 }, 1130 }, 1131 }; 1132 1133 static struct clk_branch mmss_sleepclk_clk = { 1134 .halt_reg = 0x5100, 1135 .clkr = { 1136 .enable_reg = 0x5100, 1137 .enable_mask = BIT(0), 1138 .hw.init = &(struct clk_init_data){ 1139 .name = "mmss_sleepclk_clk", 1140 .parent_data = (const struct clk_parent_data[]){ 1141 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 1142 }, 1143 .num_parents = 1, 1144 .flags = CLK_SET_RATE_PARENT, 1145 .ops = &clk_branch2_ops, 1146 }, 1147 }, 1148 }; 1149 1150 static struct clk_branch avsync_ahb_clk = { 1151 .halt_reg = 0x2414, 1152 .clkr = { 1153 .enable_reg = 0x2414, 1154 .enable_mask = BIT(0), 1155 .hw.init = &(struct clk_init_data){ 1156 .name = "avsync_ahb_clk", 1157 .parent_hws = (const struct clk_hw*[]){ 1158 &mmss_ahb_clk_src.clkr.hw 1159 }, 1160 .num_parents = 1, 1161 .flags = CLK_SET_RATE_PARENT, 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch avsync_edppixel_clk = { 1168 .halt_reg = 0x2418, 1169 .clkr = { 1170 .enable_reg = 0x2418, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(struct clk_init_data){ 1173 .name = "avsync_edppixel_clk", 1174 .parent_hws = (const struct clk_hw*[]){ 1175 &edppixel_clk_src.clkr.hw 1176 }, 1177 .num_parents = 1, 1178 .flags = CLK_SET_RATE_PARENT, 1179 .ops = &clk_branch2_ops, 1180 }, 1181 }, 1182 }; 1183 1184 static struct clk_branch avsync_extpclk_clk = { 1185 .halt_reg = 0x2410, 1186 .clkr = { 1187 .enable_reg = 0x2410, 1188 .enable_mask = BIT(0), 1189 .hw.init = &(struct clk_init_data){ 1190 .name = "avsync_extpclk_clk", 1191 .parent_hws = (const struct clk_hw*[]){ 1192 &extpclk_clk_src.clkr.hw 1193 }, 1194 .num_parents = 1, 1195 .flags = CLK_SET_RATE_PARENT, 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch avsync_pclk0_clk = { 1202 .halt_reg = 0x241c, 1203 .clkr = { 1204 .enable_reg = 0x241c, 1205 .enable_mask = BIT(0), 1206 .hw.init = &(struct clk_init_data){ 1207 .name = "avsync_pclk0_clk", 1208 .parent_hws = (const struct clk_hw*[]){ 1209 &pclk0_clk_src.clkr.hw 1210 }, 1211 .num_parents = 1, 1212 .flags = CLK_SET_RATE_PARENT, 1213 .ops = &clk_branch2_ops, 1214 }, 1215 }, 1216 }; 1217 1218 static struct clk_branch avsync_pclk1_clk = { 1219 .halt_reg = 0x2420, 1220 .clkr = { 1221 .enable_reg = 0x2420, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "avsync_pclk1_clk", 1225 .parent_hws = (const struct clk_hw*[]){ 1226 &pclk1_clk_src.clkr.hw 1227 }, 1228 .num_parents = 1, 1229 .flags = CLK_SET_RATE_PARENT, 1230 .ops = &clk_branch2_ops, 1231 }, 1232 }, 1233 }; 1234 1235 static struct clk_branch avsync_vp_clk = { 1236 .halt_reg = 0x2404, 1237 .clkr = { 1238 .enable_reg = 0x2404, 1239 .enable_mask = BIT(0), 1240 .hw.init = &(struct clk_init_data){ 1241 .name = "avsync_vp_clk", 1242 .parent_hws = (const struct clk_hw*[]){ 1243 &vp_clk_src.clkr.hw 1244 }, 1245 .num_parents = 1, 1246 .flags = CLK_SET_RATE_PARENT, 1247 .ops = &clk_branch2_ops, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch camss_ahb_clk = { 1253 .halt_reg = 0x348c, 1254 .clkr = { 1255 .enable_reg = 0x348c, 1256 .enable_mask = BIT(0), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "camss_ahb_clk", 1259 .parent_hws = (const struct clk_hw*[]){ 1260 &mmss_ahb_clk_src.clkr.hw 1261 }, 1262 .num_parents = 1, 1263 .flags = CLK_SET_RATE_PARENT, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch camss_cci_cci_ahb_clk = { 1270 .halt_reg = 0x3348, 1271 .clkr = { 1272 .enable_reg = 0x3348, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "camss_cci_cci_ahb_clk", 1276 .parent_hws = (const struct clk_hw*[]){ 1277 &mmss_ahb_clk_src.clkr.hw 1278 }, 1279 .num_parents = 1, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch camss_cci_cci_clk = { 1286 .halt_reg = 0x3344, 1287 .clkr = { 1288 .enable_reg = 0x3344, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "camss_cci_cci_clk", 1292 .parent_hws = (const struct clk_hw*[]){ 1293 &cci_clk_src.clkr.hw 1294 }, 1295 .num_parents = 1, 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_branch camss_csi0_ahb_clk = { 1303 .halt_reg = 0x30bc, 1304 .clkr = { 1305 .enable_reg = 0x30bc, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "camss_csi0_ahb_clk", 1309 .parent_hws = (const struct clk_hw*[]){ 1310 &mmss_ahb_clk_src.clkr.hw 1311 }, 1312 .num_parents = 1, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch camss_csi0_clk = { 1319 .halt_reg = 0x30b4, 1320 .clkr = { 1321 .enable_reg = 0x30b4, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data){ 1324 .name = "camss_csi0_clk", 1325 .parent_hws = (const struct clk_hw*[]){ 1326 &csi0_clk_src.clkr.hw 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch camss_csi0phy_clk = { 1336 .halt_reg = 0x30c4, 1337 .clkr = { 1338 .enable_reg = 0x30c4, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "camss_csi0phy_clk", 1342 .parent_hws = (const struct clk_hw*[]){ 1343 &csi0_clk_src.clkr.hw 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch camss_csi0pix_clk = { 1353 .halt_reg = 0x30e4, 1354 .clkr = { 1355 .enable_reg = 0x30e4, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "camss_csi0pix_clk", 1359 .parent_hws = (const struct clk_hw*[]){ 1360 &csi0_clk_src.clkr.hw 1361 }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch camss_csi0rdi_clk = { 1370 .halt_reg = 0x30d4, 1371 .clkr = { 1372 .enable_reg = 0x30d4, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(struct clk_init_data){ 1375 .name = "camss_csi0rdi_clk", 1376 .parent_hws = (const struct clk_hw*[]){ 1377 &csi0_clk_src.clkr.hw 1378 }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch camss_csi1_ahb_clk = { 1387 .halt_reg = 0x3128, 1388 .clkr = { 1389 .enable_reg = 0x3128, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "camss_csi1_ahb_clk", 1393 .parent_hws = (const struct clk_hw*[]){ 1394 &mmss_ahb_clk_src.clkr.hw 1395 }, 1396 .num_parents = 1, 1397 .flags = CLK_SET_RATE_PARENT, 1398 .ops = &clk_branch2_ops, 1399 }, 1400 }, 1401 }; 1402 1403 static struct clk_branch camss_csi1_clk = { 1404 .halt_reg = 0x3124, 1405 .clkr = { 1406 .enable_reg = 0x3124, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "camss_csi1_clk", 1410 .parent_hws = (const struct clk_hw*[]){ 1411 &csi1_clk_src.clkr.hw 1412 }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch camss_csi1phy_clk = { 1421 .halt_reg = 0x3134, 1422 .clkr = { 1423 .enable_reg = 0x3134, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "camss_csi1phy_clk", 1427 .parent_hws = (const struct clk_hw*[]){ 1428 &csi1_clk_src.clkr.hw 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 .ops = &clk_branch2_ops, 1433 }, 1434 }, 1435 }; 1436 1437 static struct clk_branch camss_csi1pix_clk = { 1438 .halt_reg = 0x3154, 1439 .clkr = { 1440 .enable_reg = 0x3154, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "camss_csi1pix_clk", 1444 .parent_hws = (const struct clk_hw*[]){ 1445 &csi1_clk_src.clkr.hw 1446 }, 1447 .num_parents = 1, 1448 .flags = CLK_SET_RATE_PARENT, 1449 .ops = &clk_branch2_ops, 1450 }, 1451 }, 1452 }; 1453 1454 static struct clk_branch camss_csi1rdi_clk = { 1455 .halt_reg = 0x3144, 1456 .clkr = { 1457 .enable_reg = 0x3144, 1458 .enable_mask = BIT(0), 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "camss_csi1rdi_clk", 1461 .parent_hws = (const struct clk_hw*[]){ 1462 &csi1_clk_src.clkr.hw 1463 }, 1464 .num_parents = 1, 1465 .flags = CLK_SET_RATE_PARENT, 1466 .ops = &clk_branch2_ops, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch camss_csi2_ahb_clk = { 1472 .halt_reg = 0x3188, 1473 .clkr = { 1474 .enable_reg = 0x3188, 1475 .enable_mask = BIT(0), 1476 .hw.init = &(struct clk_init_data){ 1477 .name = "camss_csi2_ahb_clk", 1478 .parent_hws = (const struct clk_hw*[]){ 1479 &mmss_ahb_clk_src.clkr.hw 1480 }, 1481 .num_parents = 1, 1482 .ops = &clk_branch2_ops, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_branch camss_csi2_clk = { 1488 .halt_reg = 0x3184, 1489 .clkr = { 1490 .enable_reg = 0x3184, 1491 .enable_mask = BIT(0), 1492 .hw.init = &(struct clk_init_data){ 1493 .name = "camss_csi2_clk", 1494 .parent_hws = (const struct clk_hw*[]){ 1495 &csi2_clk_src.clkr.hw 1496 }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch camss_csi2phy_clk = { 1505 .halt_reg = 0x3194, 1506 .clkr = { 1507 .enable_reg = 0x3194, 1508 .enable_mask = BIT(0), 1509 .hw.init = &(struct clk_init_data){ 1510 .name = "camss_csi2phy_clk", 1511 .parent_hws = (const struct clk_hw*[]){ 1512 &csi2_clk_src.clkr.hw 1513 }, 1514 .num_parents = 1, 1515 .flags = CLK_SET_RATE_PARENT, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch camss_csi2pix_clk = { 1522 .halt_reg = 0x31b4, 1523 .clkr = { 1524 .enable_reg = 0x31b4, 1525 .enable_mask = BIT(0), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "camss_csi2pix_clk", 1528 .parent_hws = (const struct clk_hw*[]){ 1529 &csi2_clk_src.clkr.hw 1530 }, 1531 .num_parents = 1, 1532 .flags = CLK_SET_RATE_PARENT, 1533 .ops = &clk_branch2_ops, 1534 }, 1535 }, 1536 }; 1537 1538 static struct clk_branch camss_csi2rdi_clk = { 1539 .halt_reg = 0x31a4, 1540 .clkr = { 1541 .enable_reg = 0x31a4, 1542 .enable_mask = BIT(0), 1543 .hw.init = &(struct clk_init_data){ 1544 .name = "camss_csi2rdi_clk", 1545 .parent_hws = (const struct clk_hw*[]){ 1546 &csi2_clk_src.clkr.hw 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch camss_csi3_ahb_clk = { 1556 .halt_reg = 0x31e8, 1557 .clkr = { 1558 .enable_reg = 0x31e8, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(struct clk_init_data){ 1561 .name = "camss_csi3_ahb_clk", 1562 .parent_hws = (const struct clk_hw*[]){ 1563 &mmss_ahb_clk_src.clkr.hw 1564 }, 1565 .num_parents = 1, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch camss_csi3_clk = { 1572 .halt_reg = 0x31e4, 1573 .clkr = { 1574 .enable_reg = 0x31e4, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(struct clk_init_data){ 1577 .name = "camss_csi3_clk", 1578 .parent_hws = (const struct clk_hw*[]){ 1579 &csi3_clk_src.clkr.hw 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch camss_csi3phy_clk = { 1589 .halt_reg = 0x31f4, 1590 .clkr = { 1591 .enable_reg = 0x31f4, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(struct clk_init_data){ 1594 .name = "camss_csi3phy_clk", 1595 .parent_hws = (const struct clk_hw*[]){ 1596 &csi3_clk_src.clkr.hw 1597 }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch camss_csi3pix_clk = { 1606 .halt_reg = 0x3214, 1607 .clkr = { 1608 .enable_reg = 0x3214, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "camss_csi3pix_clk", 1612 .parent_hws = (const struct clk_hw*[]){ 1613 &csi3_clk_src.clkr.hw 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620 }; 1621 1622 static struct clk_branch camss_csi3rdi_clk = { 1623 .halt_reg = 0x3204, 1624 .clkr = { 1625 .enable_reg = 0x3204, 1626 .enable_mask = BIT(0), 1627 .hw.init = &(struct clk_init_data){ 1628 .name = "camss_csi3rdi_clk", 1629 .parent_hws = (const struct clk_hw*[]){ 1630 &csi3_clk_src.clkr.hw 1631 }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch camss_csi_vfe0_clk = { 1640 .halt_reg = 0x3704, 1641 .clkr = { 1642 .enable_reg = 0x3704, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(struct clk_init_data){ 1645 .name = "camss_csi_vfe0_clk", 1646 .parent_hws = (const struct clk_hw*[]){ 1647 &vfe0_clk_src.clkr.hw 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch camss_csi_vfe1_clk = { 1657 .halt_reg = 0x3714, 1658 .clkr = { 1659 .enable_reg = 0x3714, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "camss_csi_vfe1_clk", 1663 .parent_hws = (const struct clk_hw*[]){ 1664 &vfe1_clk_src.clkr.hw 1665 }, 1666 .num_parents = 1, 1667 .flags = CLK_SET_RATE_PARENT, 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch camss_gp0_clk = { 1674 .halt_reg = 0x3444, 1675 .clkr = { 1676 .enable_reg = 0x3444, 1677 .enable_mask = BIT(0), 1678 .hw.init = &(struct clk_init_data){ 1679 .name = "camss_gp0_clk", 1680 .parent_hws = (const struct clk_hw*[]){ 1681 &camss_gp0_clk_src.clkr.hw 1682 }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch camss_gp1_clk = { 1691 .halt_reg = 0x3474, 1692 .clkr = { 1693 .enable_reg = 0x3474, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "camss_gp1_clk", 1697 .parent_hws = (const struct clk_hw*[]){ 1698 &camss_gp1_clk_src.clkr.hw 1699 }, 1700 .num_parents = 1, 1701 .flags = CLK_SET_RATE_PARENT, 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch camss_ispif_ahb_clk = { 1708 .halt_reg = 0x3224, 1709 .clkr = { 1710 .enable_reg = 0x3224, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(struct clk_init_data){ 1713 .name = "camss_ispif_ahb_clk", 1714 .parent_hws = (const struct clk_hw*[]){ 1715 &mmss_ahb_clk_src.clkr.hw 1716 }, 1717 .num_parents = 1, 1718 .flags = CLK_SET_RATE_PARENT, 1719 .ops = &clk_branch2_ops, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch camss_jpeg_jpeg0_clk = { 1725 .halt_reg = 0x35a8, 1726 .clkr = { 1727 .enable_reg = 0x35a8, 1728 .enable_mask = BIT(0), 1729 .hw.init = &(struct clk_init_data){ 1730 .name = "camss_jpeg_jpeg0_clk", 1731 .parent_hws = (const struct clk_hw*[]){ 1732 &jpeg0_clk_src.clkr.hw 1733 }, 1734 .num_parents = 1, 1735 .flags = CLK_SET_RATE_PARENT, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static struct clk_branch camss_jpeg_jpeg1_clk = { 1742 .halt_reg = 0x35ac, 1743 .clkr = { 1744 .enable_reg = 0x35ac, 1745 .enable_mask = BIT(0), 1746 .hw.init = &(struct clk_init_data){ 1747 .name = "camss_jpeg_jpeg1_clk", 1748 .parent_hws = (const struct clk_hw*[]){ 1749 &jpeg1_clk_src.clkr.hw 1750 }, 1751 .num_parents = 1, 1752 .flags = CLK_SET_RATE_PARENT, 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch camss_jpeg_jpeg2_clk = { 1759 .halt_reg = 0x35b0, 1760 .clkr = { 1761 .enable_reg = 0x35b0, 1762 .enable_mask = BIT(0), 1763 .hw.init = &(struct clk_init_data){ 1764 .name = "camss_jpeg_jpeg2_clk", 1765 .parent_hws = (const struct clk_hw*[]){ 1766 &jpeg2_clk_src.clkr.hw 1767 }, 1768 .num_parents = 1, 1769 .flags = CLK_SET_RATE_PARENT, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch camss_jpeg_jpeg_ahb_clk = { 1776 .halt_reg = 0x35b4, 1777 .clkr = { 1778 .enable_reg = 0x35b4, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "camss_jpeg_jpeg_ahb_clk", 1782 .parent_hws = (const struct clk_hw*[]){ 1783 &mmss_ahb_clk_src.clkr.hw 1784 }, 1785 .num_parents = 1, 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch camss_jpeg_jpeg_axi_clk = { 1792 .halt_reg = 0x35b8, 1793 .clkr = { 1794 .enable_reg = 0x35b8, 1795 .enable_mask = BIT(0), 1796 .hw.init = &(struct clk_init_data){ 1797 .name = "camss_jpeg_jpeg_axi_clk", 1798 .parent_hws = (const struct clk_hw*[]){ 1799 &mmss_axi_clk_src.clkr.hw 1800 }, 1801 .num_parents = 1, 1802 .ops = &clk_branch2_ops, 1803 }, 1804 }, 1805 }; 1806 1807 static struct clk_branch camss_mclk0_clk = { 1808 .halt_reg = 0x3384, 1809 .clkr = { 1810 .enable_reg = 0x3384, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "camss_mclk0_clk", 1814 .parent_hws = (const struct clk_hw*[]){ 1815 &mclk0_clk_src.clkr.hw 1816 }, 1817 .num_parents = 1, 1818 .flags = CLK_SET_RATE_PARENT, 1819 .ops = &clk_branch2_ops, 1820 }, 1821 }, 1822 }; 1823 1824 static struct clk_branch camss_mclk1_clk = { 1825 .halt_reg = 0x33b4, 1826 .clkr = { 1827 .enable_reg = 0x33b4, 1828 .enable_mask = BIT(0), 1829 .hw.init = &(struct clk_init_data){ 1830 .name = "camss_mclk1_clk", 1831 .parent_hws = (const struct clk_hw*[]){ 1832 &mclk1_clk_src.clkr.hw 1833 }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT, 1836 .ops = &clk_branch2_ops, 1837 }, 1838 }, 1839 }; 1840 1841 static struct clk_branch camss_mclk2_clk = { 1842 .halt_reg = 0x33e4, 1843 .clkr = { 1844 .enable_reg = 0x33e4, 1845 .enable_mask = BIT(0), 1846 .hw.init = &(struct clk_init_data){ 1847 .name = "camss_mclk2_clk", 1848 .parent_hws = (const struct clk_hw*[]){ 1849 &mclk2_clk_src.clkr.hw 1850 }, 1851 .num_parents = 1, 1852 .flags = CLK_SET_RATE_PARENT, 1853 .ops = &clk_branch2_ops, 1854 }, 1855 }, 1856 }; 1857 1858 static struct clk_branch camss_mclk3_clk = { 1859 .halt_reg = 0x3414, 1860 .clkr = { 1861 .enable_reg = 0x3414, 1862 .enable_mask = BIT(0), 1863 .hw.init = &(struct clk_init_data){ 1864 .name = "camss_mclk3_clk", 1865 .parent_hws = (const struct clk_hw*[]){ 1866 &mclk3_clk_src.clkr.hw 1867 }, 1868 .num_parents = 1, 1869 .flags = CLK_SET_RATE_PARENT, 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch camss_micro_ahb_clk = { 1876 .halt_reg = 0x3494, 1877 .clkr = { 1878 .enable_reg = 0x3494, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(struct clk_init_data){ 1881 .name = "camss_micro_ahb_clk", 1882 .parent_hws = (const struct clk_hw*[]){ 1883 &mmss_ahb_clk_src.clkr.hw 1884 }, 1885 .num_parents = 1, 1886 .ops = &clk_branch2_ops, 1887 }, 1888 }, 1889 }; 1890 1891 static struct clk_branch camss_phy0_csi0phytimer_clk = { 1892 .halt_reg = 0x3024, 1893 .clkr = { 1894 .enable_reg = 0x3024, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "camss_phy0_csi0phytimer_clk", 1898 .parent_hws = (const struct clk_hw*[]){ 1899 &csi0phytimer_clk_src.clkr.hw 1900 }, 1901 .num_parents = 1, 1902 .flags = CLK_SET_RATE_PARENT, 1903 .ops = &clk_branch2_ops, 1904 }, 1905 }, 1906 }; 1907 1908 static struct clk_branch camss_phy1_csi1phytimer_clk = { 1909 .halt_reg = 0x3054, 1910 .clkr = { 1911 .enable_reg = 0x3054, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "camss_phy1_csi1phytimer_clk", 1915 .parent_hws = (const struct clk_hw*[]){ 1916 &csi1phytimer_clk_src.clkr.hw 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch camss_phy2_csi2phytimer_clk = { 1926 .halt_reg = 0x3084, 1927 .clkr = { 1928 .enable_reg = 0x3084, 1929 .enable_mask = BIT(0), 1930 .hw.init = &(struct clk_init_data){ 1931 .name = "camss_phy2_csi2phytimer_clk", 1932 .parent_hws = (const struct clk_hw*[]){ 1933 &csi2phytimer_clk_src.clkr.hw 1934 }, 1935 .num_parents = 1, 1936 .flags = CLK_SET_RATE_PARENT, 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940 }; 1941 1942 static struct clk_branch camss_top_ahb_clk = { 1943 .halt_reg = 0x3484, 1944 .clkr = { 1945 .enable_reg = 0x3484, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(struct clk_init_data){ 1948 .name = "camss_top_ahb_clk", 1949 .parent_hws = (const struct clk_hw*[]){ 1950 &mmss_ahb_clk_src.clkr.hw 1951 }, 1952 .num_parents = 1, 1953 .flags = CLK_SET_RATE_PARENT, 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch camss_vfe_cpp_ahb_clk = { 1960 .halt_reg = 0x36b4, 1961 .clkr = { 1962 .enable_reg = 0x36b4, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(struct clk_init_data){ 1965 .name = "camss_vfe_cpp_ahb_clk", 1966 .parent_hws = (const struct clk_hw*[]){ 1967 &mmss_ahb_clk_src.clkr.hw 1968 }, 1969 .num_parents = 1, 1970 .flags = CLK_SET_RATE_PARENT, 1971 .ops = &clk_branch2_ops, 1972 }, 1973 }, 1974 }; 1975 1976 static struct clk_branch camss_vfe_cpp_clk = { 1977 .halt_reg = 0x36b0, 1978 .clkr = { 1979 .enable_reg = 0x36b0, 1980 .enable_mask = BIT(0), 1981 .hw.init = &(struct clk_init_data){ 1982 .name = "camss_vfe_cpp_clk", 1983 .parent_hws = (const struct clk_hw*[]){ 1984 &cpp_clk_src.clkr.hw 1985 }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch camss_vfe_vfe0_clk = { 1994 .halt_reg = 0x36a8, 1995 .clkr = { 1996 .enable_reg = 0x36a8, 1997 .enable_mask = BIT(0), 1998 .hw.init = &(struct clk_init_data){ 1999 .name = "camss_vfe_vfe0_clk", 2000 .parent_hws = (const struct clk_hw*[]){ 2001 &vfe0_clk_src.clkr.hw 2002 }, 2003 .num_parents = 1, 2004 .flags = CLK_SET_RATE_PARENT, 2005 .ops = &clk_branch2_ops, 2006 }, 2007 }, 2008 }; 2009 2010 static struct clk_branch camss_vfe_vfe1_clk = { 2011 .halt_reg = 0x36ac, 2012 .clkr = { 2013 .enable_reg = 0x36ac, 2014 .enable_mask = BIT(0), 2015 .hw.init = &(struct clk_init_data){ 2016 .name = "camss_vfe_vfe1_clk", 2017 .parent_hws = (const struct clk_hw*[]){ 2018 &vfe1_clk_src.clkr.hw 2019 }, 2020 .num_parents = 1, 2021 .flags = CLK_SET_RATE_PARENT, 2022 .ops = &clk_branch2_ops, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_branch camss_vfe_vfe_ahb_clk = { 2028 .halt_reg = 0x36b8, 2029 .clkr = { 2030 .enable_reg = 0x36b8, 2031 .enable_mask = BIT(0), 2032 .hw.init = &(struct clk_init_data){ 2033 .name = "camss_vfe_vfe_ahb_clk", 2034 .parent_hws = (const struct clk_hw*[]){ 2035 &mmss_ahb_clk_src.clkr.hw 2036 }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch camss_vfe_vfe_axi_clk = { 2045 .halt_reg = 0x36bc, 2046 .clkr = { 2047 .enable_reg = 0x36bc, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "camss_vfe_vfe_axi_clk", 2051 .parent_hws = (const struct clk_hw*[]){ 2052 &mmss_axi_clk_src.clkr.hw 2053 }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch mdss_ahb_clk = { 2062 .halt_reg = 0x2308, 2063 .clkr = { 2064 .enable_reg = 0x2308, 2065 .enable_mask = BIT(0), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "mdss_ahb_clk", 2068 .parent_hws = (const struct clk_hw*[]){ 2069 &mmss_ahb_clk_src.clkr.hw 2070 }, 2071 .num_parents = 1, 2072 .flags = CLK_SET_RATE_PARENT, 2073 .ops = &clk_branch2_ops, 2074 }, 2075 }, 2076 }; 2077 2078 static struct clk_branch mdss_axi_clk = { 2079 .halt_reg = 0x2310, 2080 .clkr = { 2081 .enable_reg = 0x2310, 2082 .enable_mask = BIT(0), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "mdss_axi_clk", 2085 .parent_hws = (const struct clk_hw*[]){ 2086 &mmss_axi_clk_src.clkr.hw 2087 }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch mdss_byte0_clk = { 2096 .halt_reg = 0x233c, 2097 .clkr = { 2098 .enable_reg = 0x233c, 2099 .enable_mask = BIT(0), 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "mdss_byte0_clk", 2102 .parent_hws = (const struct clk_hw*[]){ 2103 &byte0_clk_src.clkr.hw 2104 }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT, 2107 .ops = &clk_branch2_ops, 2108 }, 2109 }, 2110 }; 2111 2112 static struct clk_branch mdss_byte1_clk = { 2113 .halt_reg = 0x2340, 2114 .clkr = { 2115 .enable_reg = 0x2340, 2116 .enable_mask = BIT(0), 2117 .hw.init = &(struct clk_init_data){ 2118 .name = "mdss_byte1_clk", 2119 .parent_hws = (const struct clk_hw*[]){ 2120 &byte1_clk_src.clkr.hw 2121 }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT, 2124 .ops = &clk_branch2_ops, 2125 }, 2126 }, 2127 }; 2128 2129 static struct clk_branch mdss_edpaux_clk = { 2130 .halt_reg = 0x2334, 2131 .clkr = { 2132 .enable_reg = 0x2334, 2133 .enable_mask = BIT(0), 2134 .hw.init = &(struct clk_init_data){ 2135 .name = "mdss_edpaux_clk", 2136 .parent_hws = (const struct clk_hw*[]){ 2137 &edpaux_clk_src.clkr.hw 2138 }, 2139 .num_parents = 1, 2140 .flags = CLK_SET_RATE_PARENT, 2141 .ops = &clk_branch2_ops, 2142 }, 2143 }, 2144 }; 2145 2146 static struct clk_branch mdss_edplink_clk = { 2147 .halt_reg = 0x2330, 2148 .clkr = { 2149 .enable_reg = 0x2330, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "mdss_edplink_clk", 2153 .parent_hws = (const struct clk_hw*[]){ 2154 &edplink_clk_src.clkr.hw 2155 }, 2156 .num_parents = 1, 2157 .flags = CLK_SET_RATE_PARENT, 2158 .ops = &clk_branch2_ops, 2159 }, 2160 }, 2161 }; 2162 2163 static struct clk_branch mdss_edppixel_clk = { 2164 .halt_reg = 0x232c, 2165 .clkr = { 2166 .enable_reg = 0x232c, 2167 .enable_mask = BIT(0), 2168 .hw.init = &(struct clk_init_data){ 2169 .name = "mdss_edppixel_clk", 2170 .parent_hws = (const struct clk_hw*[]){ 2171 &edppixel_clk_src.clkr.hw 2172 }, 2173 .num_parents = 1, 2174 .flags = CLK_SET_RATE_PARENT, 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch mdss_esc0_clk = { 2181 .halt_reg = 0x2344, 2182 .clkr = { 2183 .enable_reg = 0x2344, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(struct clk_init_data){ 2186 .name = "mdss_esc0_clk", 2187 .parent_hws = (const struct clk_hw*[]){ 2188 &esc0_clk_src.clkr.hw 2189 }, 2190 .num_parents = 1, 2191 .flags = CLK_SET_RATE_PARENT, 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct clk_branch mdss_esc1_clk = { 2198 .halt_reg = 0x2348, 2199 .clkr = { 2200 .enable_reg = 0x2348, 2201 .enable_mask = BIT(0), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "mdss_esc1_clk", 2204 .parent_hws = (const struct clk_hw*[]){ 2205 &esc1_clk_src.clkr.hw 2206 }, 2207 .num_parents = 1, 2208 .flags = CLK_SET_RATE_PARENT, 2209 .ops = &clk_branch2_ops, 2210 }, 2211 }, 2212 }; 2213 2214 static struct clk_branch mdss_extpclk_clk = { 2215 .halt_reg = 0x2324, 2216 .clkr = { 2217 .enable_reg = 0x2324, 2218 .enable_mask = BIT(0), 2219 .hw.init = &(struct clk_init_data){ 2220 .name = "mdss_extpclk_clk", 2221 .parent_hws = (const struct clk_hw*[]){ 2222 &extpclk_clk_src.clkr.hw 2223 }, 2224 .num_parents = 1, 2225 .flags = CLK_SET_RATE_PARENT, 2226 .ops = &clk_branch2_ops, 2227 }, 2228 }, 2229 }; 2230 2231 static struct clk_branch mdss_hdmi_ahb_clk = { 2232 .halt_reg = 0x230c, 2233 .clkr = { 2234 .enable_reg = 0x230c, 2235 .enable_mask = BIT(0), 2236 .hw.init = &(struct clk_init_data){ 2237 .name = "mdss_hdmi_ahb_clk", 2238 .parent_hws = (const struct clk_hw*[]){ 2239 &mmss_ahb_clk_src.clkr.hw 2240 }, 2241 .num_parents = 1, 2242 .flags = CLK_SET_RATE_PARENT, 2243 .ops = &clk_branch2_ops, 2244 }, 2245 }, 2246 }; 2247 2248 static struct clk_branch mdss_hdmi_clk = { 2249 .halt_reg = 0x2338, 2250 .clkr = { 2251 .enable_reg = 0x2338, 2252 .enable_mask = BIT(0), 2253 .hw.init = &(struct clk_init_data){ 2254 .name = "mdss_hdmi_clk", 2255 .parent_hws = (const struct clk_hw*[]){ 2256 &hdmi_clk_src.clkr.hw 2257 }, 2258 .num_parents = 1, 2259 .flags = CLK_SET_RATE_PARENT, 2260 .ops = &clk_branch2_ops, 2261 }, 2262 }, 2263 }; 2264 2265 static struct clk_branch mdss_mdp_clk = { 2266 .halt_reg = 0x231c, 2267 .clkr = { 2268 .enable_reg = 0x231c, 2269 .enable_mask = BIT(0), 2270 .hw.init = &(struct clk_init_data){ 2271 .name = "mdss_mdp_clk", 2272 .parent_hws = (const struct clk_hw*[]){ 2273 &mdp_clk_src.clkr.hw 2274 }, 2275 .num_parents = 1, 2276 .flags = CLK_SET_RATE_PARENT, 2277 .ops = &clk_branch2_ops, 2278 }, 2279 }, 2280 }; 2281 2282 static struct clk_branch mdss_mdp_lut_clk = { 2283 .halt_reg = 0x2320, 2284 .clkr = { 2285 .enable_reg = 0x2320, 2286 .enable_mask = BIT(0), 2287 .hw.init = &(struct clk_init_data){ 2288 .name = "mdss_mdp_lut_clk", 2289 .parent_hws = (const struct clk_hw*[]){ 2290 &mdp_clk_src.clkr.hw 2291 }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch mdss_pclk0_clk = { 2300 .halt_reg = 0x2314, 2301 .clkr = { 2302 .enable_reg = 0x2314, 2303 .enable_mask = BIT(0), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "mdss_pclk0_clk", 2306 .parent_hws = (const struct clk_hw*[]){ 2307 &pclk0_clk_src.clkr.hw 2308 }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch mdss_pclk1_clk = { 2317 .halt_reg = 0x2318, 2318 .clkr = { 2319 .enable_reg = 0x2318, 2320 .enable_mask = BIT(0), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "mdss_pclk1_clk", 2323 .parent_hws = (const struct clk_hw*[]){ 2324 &pclk1_clk_src.clkr.hw 2325 }, 2326 .num_parents = 1, 2327 .flags = CLK_SET_RATE_PARENT, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch mdss_vsync_clk = { 2334 .halt_reg = 0x2328, 2335 .clkr = { 2336 .enable_reg = 0x2328, 2337 .enable_mask = BIT(0), 2338 .hw.init = &(struct clk_init_data){ 2339 .name = "mdss_vsync_clk", 2340 .parent_hws = (const struct clk_hw*[]){ 2341 &vsync_clk_src.clkr.hw 2342 }, 2343 .num_parents = 1, 2344 .flags = CLK_SET_RATE_PARENT, 2345 .ops = &clk_branch2_ops, 2346 }, 2347 }, 2348 }; 2349 2350 static struct clk_branch mmss_rbcpr_ahb_clk = { 2351 .halt_reg = 0x4088, 2352 .clkr = { 2353 .enable_reg = 0x4088, 2354 .enable_mask = BIT(0), 2355 .hw.init = &(struct clk_init_data){ 2356 .name = "mmss_rbcpr_ahb_clk", 2357 .parent_hws = (const struct clk_hw*[]){ 2358 &mmss_ahb_clk_src.clkr.hw 2359 }, 2360 .num_parents = 1, 2361 .flags = CLK_SET_RATE_PARENT, 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch mmss_rbcpr_clk = { 2368 .halt_reg = 0x4084, 2369 .clkr = { 2370 .enable_reg = 0x4084, 2371 .enable_mask = BIT(0), 2372 .hw.init = &(struct clk_init_data){ 2373 .name = "mmss_rbcpr_clk", 2374 .parent_hws = (const struct clk_hw*[]){ 2375 &rbcpr_clk_src.clkr.hw 2376 }, 2377 .num_parents = 1, 2378 .flags = CLK_SET_RATE_PARENT, 2379 .ops = &clk_branch2_ops, 2380 }, 2381 }, 2382 }; 2383 2384 static struct clk_branch mmss_misc_ahb_clk = { 2385 .halt_reg = 0x502c, 2386 .clkr = { 2387 .enable_reg = 0x502c, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(struct clk_init_data){ 2390 .name = "mmss_misc_ahb_clk", 2391 .parent_hws = (const struct clk_hw*[]){ 2392 &mmss_ahb_clk_src.clkr.hw 2393 }, 2394 .num_parents = 1, 2395 .flags = CLK_SET_RATE_PARENT, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch mmss_mmssnoc_ahb_clk = { 2402 .halt_reg = 0x5024, 2403 .clkr = { 2404 .enable_reg = 0x5024, 2405 .enable_mask = BIT(0), 2406 .hw.init = &(struct clk_init_data){ 2407 .name = "mmss_mmssnoc_ahb_clk", 2408 .parent_hws = (const struct clk_hw*[]){ 2409 &mmss_ahb_clk_src.clkr.hw 2410 }, 2411 .num_parents = 1, 2412 .ops = &clk_branch2_ops, 2413 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2414 }, 2415 }, 2416 }; 2417 2418 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { 2419 .halt_reg = 0x5028, 2420 .clkr = { 2421 .enable_reg = 0x5028, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "mmss_mmssnoc_bto_ahb_clk", 2425 .parent_hws = (const struct clk_hw*[]){ 2426 &mmss_ahb_clk_src.clkr.hw 2427 }, 2428 .num_parents = 1, 2429 .ops = &clk_branch2_ops, 2430 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch mmss_mmssnoc_axi_clk = { 2436 .halt_reg = 0x506c, 2437 .clkr = { 2438 .enable_reg = 0x506c, 2439 .enable_mask = BIT(0), 2440 .hw.init = &(struct clk_init_data){ 2441 .name = "mmss_mmssnoc_axi_clk", 2442 .parent_hws = (const struct clk_hw*[]){ 2443 &mmss_axi_clk_src.clkr.hw 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2447 .ops = &clk_branch2_ops, 2448 }, 2449 }, 2450 }; 2451 2452 static struct clk_branch mmss_s0_axi_clk = { 2453 .halt_reg = 0x5064, 2454 .clkr = { 2455 .enable_reg = 0x5064, 2456 .enable_mask = BIT(0), 2457 .hw.init = &(struct clk_init_data){ 2458 .name = "mmss_s0_axi_clk", 2459 .parent_hws = (const struct clk_hw*[]){ 2460 &mmss_axi_clk_src.clkr.hw 2461 }, 2462 .num_parents = 1, 2463 .ops = &clk_branch2_ops, 2464 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch ocmemcx_ahb_clk = { 2470 .halt_reg = 0x405c, 2471 .clkr = { 2472 .enable_reg = 0x405c, 2473 .enable_mask = BIT(0), 2474 .hw.init = &(struct clk_init_data){ 2475 .name = "ocmemcx_ahb_clk", 2476 .parent_hws = (const struct clk_hw*[]){ 2477 &mmss_ahb_clk_src.clkr.hw 2478 }, 2479 .num_parents = 1, 2480 .flags = CLK_SET_RATE_PARENT, 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch ocmemcx_ocmemnoc_clk = { 2487 .halt_reg = 0x4058, 2488 .clkr = { 2489 .enable_reg = 0x4058, 2490 .enable_mask = BIT(0), 2491 .hw.init = &(struct clk_init_data){ 2492 .name = "ocmemcx_ocmemnoc_clk", 2493 .parent_hws = (const struct clk_hw*[]){ 2494 &ocmemnoc_clk_src.clkr.hw 2495 }, 2496 .num_parents = 1, 2497 .flags = CLK_SET_RATE_PARENT, 2498 .ops = &clk_branch2_ops, 2499 }, 2500 }, 2501 }; 2502 2503 static struct clk_branch oxili_ocmemgx_clk = { 2504 .halt_reg = 0x402c, 2505 .clkr = { 2506 .enable_reg = 0x402c, 2507 .enable_mask = BIT(0), 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "oxili_ocmemgx_clk", 2510 .parent_hws = (const struct clk_hw*[]){ 2511 &gfx3d_clk_src.clkr.hw 2512 }, 2513 .num_parents = 1, 2514 .flags = CLK_SET_RATE_PARENT, 2515 .ops = &clk_branch2_ops, 2516 }, 2517 }, 2518 }; 2519 2520 static struct clk_branch oxili_gfx3d_clk = { 2521 .halt_reg = 0x4028, 2522 .clkr = { 2523 .enable_reg = 0x4028, 2524 .enable_mask = BIT(0), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "oxili_gfx3d_clk", 2527 .parent_hws = (const struct clk_hw*[]){ 2528 &gfx3d_clk_src.clkr.hw 2529 }, 2530 .num_parents = 1, 2531 .flags = CLK_SET_RATE_PARENT, 2532 .ops = &clk_branch2_ops, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch oxili_rbbmtimer_clk = { 2538 .halt_reg = 0x40b0, 2539 .clkr = { 2540 .enable_reg = 0x40b0, 2541 .enable_mask = BIT(0), 2542 .hw.init = &(struct clk_init_data){ 2543 .name = "oxili_rbbmtimer_clk", 2544 .parent_hws = (const struct clk_hw*[]){ 2545 &rbbmtimer_clk_src.clkr.hw 2546 }, 2547 .num_parents = 1, 2548 .flags = CLK_SET_RATE_PARENT, 2549 .ops = &clk_branch2_ops, 2550 }, 2551 }, 2552 }; 2553 2554 static struct clk_branch oxilicx_ahb_clk = { 2555 .halt_reg = 0x403c, 2556 .clkr = { 2557 .enable_reg = 0x403c, 2558 .enable_mask = BIT(0), 2559 .hw.init = &(struct clk_init_data){ 2560 .name = "oxilicx_ahb_clk", 2561 .parent_hws = (const struct clk_hw*[]){ 2562 &mmss_ahb_clk_src.clkr.hw 2563 }, 2564 .num_parents = 1, 2565 .flags = CLK_SET_RATE_PARENT, 2566 .ops = &clk_branch2_ops, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_branch venus0_ahb_clk = { 2572 .halt_reg = 0x1030, 2573 .clkr = { 2574 .enable_reg = 0x1030, 2575 .enable_mask = BIT(0), 2576 .hw.init = &(struct clk_init_data){ 2577 .name = "venus0_ahb_clk", 2578 .parent_hws = (const struct clk_hw*[]){ 2579 &mmss_ahb_clk_src.clkr.hw 2580 }, 2581 .num_parents = 1, 2582 .flags = CLK_SET_RATE_PARENT, 2583 .ops = &clk_branch2_ops, 2584 }, 2585 }, 2586 }; 2587 2588 static struct clk_branch venus0_axi_clk = { 2589 .halt_reg = 0x1034, 2590 .clkr = { 2591 .enable_reg = 0x1034, 2592 .enable_mask = BIT(0), 2593 .hw.init = &(struct clk_init_data){ 2594 .name = "venus0_axi_clk", 2595 .parent_hws = (const struct clk_hw*[]){ 2596 &mmss_axi_clk_src.clkr.hw 2597 }, 2598 .num_parents = 1, 2599 .flags = CLK_SET_RATE_PARENT, 2600 .ops = &clk_branch2_ops, 2601 }, 2602 }, 2603 }; 2604 2605 static struct clk_branch venus0_core0_vcodec_clk = { 2606 .halt_reg = 0x1048, 2607 .clkr = { 2608 .enable_reg = 0x1048, 2609 .enable_mask = BIT(0), 2610 .hw.init = &(struct clk_init_data){ 2611 .name = "venus0_core0_vcodec_clk", 2612 .parent_hws = (const struct clk_hw*[]){ 2613 &vcodec0_clk_src.clkr.hw 2614 }, 2615 .num_parents = 1, 2616 .flags = CLK_SET_RATE_PARENT, 2617 .ops = &clk_branch2_ops, 2618 }, 2619 }, 2620 }; 2621 2622 static struct clk_branch venus0_core1_vcodec_clk = { 2623 .halt_reg = 0x104c, 2624 .clkr = { 2625 .enable_reg = 0x104c, 2626 .enable_mask = BIT(0), 2627 .hw.init = &(struct clk_init_data){ 2628 .name = "venus0_core1_vcodec_clk", 2629 .parent_hws = (const struct clk_hw*[]){ 2630 &vcodec0_clk_src.clkr.hw 2631 }, 2632 .num_parents = 1, 2633 .flags = CLK_SET_RATE_PARENT, 2634 .ops = &clk_branch2_ops, 2635 }, 2636 }, 2637 }; 2638 2639 static struct clk_branch venus0_ocmemnoc_clk = { 2640 .halt_reg = 0x1038, 2641 .clkr = { 2642 .enable_reg = 0x1038, 2643 .enable_mask = BIT(0), 2644 .hw.init = &(struct clk_init_data){ 2645 .name = "venus0_ocmemnoc_clk", 2646 .parent_hws = (const struct clk_hw*[]){ 2647 &ocmemnoc_clk_src.clkr.hw 2648 }, 2649 .num_parents = 1, 2650 .flags = CLK_SET_RATE_PARENT, 2651 .ops = &clk_branch2_ops, 2652 }, 2653 }, 2654 }; 2655 2656 static struct clk_branch venus0_vcodec0_clk = { 2657 .halt_reg = 0x1028, 2658 .clkr = { 2659 .enable_reg = 0x1028, 2660 .enable_mask = BIT(0), 2661 .hw.init = &(struct clk_init_data){ 2662 .name = "venus0_vcodec0_clk", 2663 .parent_hws = (const struct clk_hw*[]){ 2664 &vcodec0_clk_src.clkr.hw 2665 }, 2666 .num_parents = 1, 2667 .flags = CLK_SET_RATE_PARENT, 2668 .ops = &clk_branch2_ops, 2669 }, 2670 }, 2671 }; 2672 2673 static struct clk_branch vpu_ahb_clk = { 2674 .halt_reg = 0x1430, 2675 .clkr = { 2676 .enable_reg = 0x1430, 2677 .enable_mask = BIT(0), 2678 .hw.init = &(struct clk_init_data){ 2679 .name = "vpu_ahb_clk", 2680 .parent_hws = (const struct clk_hw*[]){ 2681 &mmss_ahb_clk_src.clkr.hw 2682 }, 2683 .num_parents = 1, 2684 .flags = CLK_SET_RATE_PARENT, 2685 .ops = &clk_branch2_ops, 2686 }, 2687 }, 2688 }; 2689 2690 static struct clk_branch vpu_axi_clk = { 2691 .halt_reg = 0x143c, 2692 .clkr = { 2693 .enable_reg = 0x143c, 2694 .enable_mask = BIT(0), 2695 .hw.init = &(struct clk_init_data){ 2696 .name = "vpu_axi_clk", 2697 .parent_hws = (const struct clk_hw*[]){ 2698 &mmss_axi_clk_src.clkr.hw 2699 }, 2700 .num_parents = 1, 2701 .flags = CLK_SET_RATE_PARENT, 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch vpu_bus_clk = { 2708 .halt_reg = 0x1440, 2709 .clkr = { 2710 .enable_reg = 0x1440, 2711 .enable_mask = BIT(0), 2712 .hw.init = &(struct clk_init_data){ 2713 .name = "vpu_bus_clk", 2714 .parent_hws = (const struct clk_hw*[]){ 2715 &vpu_bus_clk_src.clkr.hw 2716 }, 2717 .num_parents = 1, 2718 .flags = CLK_SET_RATE_PARENT, 2719 .ops = &clk_branch2_ops, 2720 }, 2721 }, 2722 }; 2723 2724 static struct clk_branch vpu_cxo_clk = { 2725 .halt_reg = 0x1434, 2726 .clkr = { 2727 .enable_reg = 0x1434, 2728 .enable_mask = BIT(0), 2729 .hw.init = &(struct clk_init_data){ 2730 .name = "vpu_cxo_clk", 2731 .parent_data = (const struct clk_parent_data[]){ 2732 { .fw_name = "xo", .name = "xo_board" }, 2733 }, 2734 .num_parents = 1, 2735 .flags = CLK_SET_RATE_PARENT, 2736 .ops = &clk_branch2_ops, 2737 }, 2738 }, 2739 }; 2740 2741 static struct clk_branch vpu_maple_clk = { 2742 .halt_reg = 0x142c, 2743 .clkr = { 2744 .enable_reg = 0x142c, 2745 .enable_mask = BIT(0), 2746 .hw.init = &(struct clk_init_data){ 2747 .name = "vpu_maple_clk", 2748 .parent_hws = (const struct clk_hw*[]){ 2749 &maple_clk_src.clkr.hw 2750 }, 2751 .num_parents = 1, 2752 .flags = CLK_SET_RATE_PARENT, 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch vpu_sleep_clk = { 2759 .halt_reg = 0x1438, 2760 .clkr = { 2761 .enable_reg = 0x1438, 2762 .enable_mask = BIT(0), 2763 .hw.init = &(struct clk_init_data){ 2764 .name = "vpu_sleep_clk", 2765 .parent_data = (const struct clk_parent_data[]){ 2766 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 2767 }, 2768 .num_parents = 1, 2769 .flags = CLK_SET_RATE_PARENT, 2770 .ops = &clk_branch2_ops, 2771 }, 2772 }, 2773 }; 2774 2775 static struct clk_branch vpu_vdp_clk = { 2776 .halt_reg = 0x1428, 2777 .clkr = { 2778 .enable_reg = 0x1428, 2779 .enable_mask = BIT(0), 2780 .hw.init = &(struct clk_init_data){ 2781 .name = "vpu_vdp_clk", 2782 .parent_hws = (const struct clk_hw*[]){ 2783 &vdp_clk_src.clkr.hw 2784 }, 2785 .num_parents = 1, 2786 .flags = CLK_SET_RATE_PARENT, 2787 .ops = &clk_branch2_ops, 2788 }, 2789 }, 2790 }; 2791 2792 static const struct pll_config mmpll1_config = { 2793 .l = 60, 2794 .m = 25, 2795 .n = 32, 2796 .vco_val = 0x0, 2797 .vco_mask = 0x3 << 20, 2798 .pre_div_val = 0x0, 2799 .pre_div_mask = 0x7 << 12, 2800 .post_div_val = 0x0, 2801 .post_div_mask = 0x3 << 8, 2802 .mn_ena_mask = BIT(24), 2803 .main_output_mask = BIT(0), 2804 }; 2805 2806 static const struct pll_config mmpll3_config = { 2807 .l = 48, 2808 .m = 7, 2809 .n = 16, 2810 .vco_val = 0x0, 2811 .vco_mask = 0x3 << 20, 2812 .pre_div_val = 0x0, 2813 .pre_div_mask = 0x7 << 12, 2814 .post_div_val = 0x0, 2815 .post_div_mask = 0x3 << 8, 2816 .mn_ena_mask = BIT(24), 2817 .main_output_mask = BIT(0), 2818 .aux_output_mask = BIT(1), 2819 }; 2820 2821 static struct gdsc venus0_gdsc = { 2822 .gdscr = 0x1024, 2823 .pd = { 2824 .name = "venus0", 2825 }, 2826 .pwrsts = PWRSTS_OFF_ON, 2827 }; 2828 2829 static struct gdsc venus0_core0_gdsc = { 2830 .gdscr = 0x1040, 2831 .pd = { 2832 .name = "venus0_core0", 2833 }, 2834 .pwrsts = PWRSTS_OFF_ON, 2835 }; 2836 2837 static struct gdsc venus0_core1_gdsc = { 2838 .gdscr = 0x1044, 2839 .pd = { 2840 .name = "venus0_core1", 2841 }, 2842 .pwrsts = PWRSTS_OFF_ON, 2843 }; 2844 2845 static struct gdsc mdss_gdsc = { 2846 .gdscr = 0x2304, 2847 .cxcs = (unsigned int []){ 0x231c, 0x2320 }, 2848 .cxc_count = 2, 2849 .pd = { 2850 .name = "mdss", 2851 }, 2852 .pwrsts = PWRSTS_OFF_ON, 2853 }; 2854 2855 static struct gdsc camss_jpeg_gdsc = { 2856 .gdscr = 0x35a4, 2857 .pd = { 2858 .name = "camss_jpeg", 2859 }, 2860 .pwrsts = PWRSTS_OFF_ON, 2861 }; 2862 2863 static struct gdsc camss_vfe_gdsc = { 2864 .gdscr = 0x36a4, 2865 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 }, 2866 .cxc_count = 3, 2867 .pd = { 2868 .name = "camss_vfe", 2869 }, 2870 .pwrsts = PWRSTS_OFF_ON, 2871 }; 2872 2873 static struct gdsc oxili_gdsc = { 2874 .gdscr = 0x4024, 2875 .cxcs = (unsigned int []){ 0x4028 }, 2876 .cxc_count = 1, 2877 .pd = { 2878 .name = "oxili", 2879 }, 2880 .pwrsts = PWRSTS_OFF_ON, 2881 }; 2882 2883 static struct gdsc oxilicx_gdsc = { 2884 .gdscr = 0x4034, 2885 .pd = { 2886 .name = "oxilicx", 2887 }, 2888 .pwrsts = PWRSTS_OFF_ON, 2889 }; 2890 2891 static struct clk_regmap *mmcc_apq8084_clocks[] = { 2892 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, 2893 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, 2894 [MMPLL0] = &mmpll0.clkr, 2895 [MMPLL0_VOTE] = &mmpll0_vote, 2896 [MMPLL1] = &mmpll1.clkr, 2897 [MMPLL1_VOTE] = &mmpll1_vote, 2898 [MMPLL2] = &mmpll2.clkr, 2899 [MMPLL3] = &mmpll3.clkr, 2900 [MMPLL4] = &mmpll4.clkr, 2901 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2902 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2903 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2904 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2905 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 2906 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2907 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2908 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2909 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2910 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2911 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, 2912 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2913 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2914 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, 2915 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, 2916 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, 2917 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2918 [VP_CLK_SRC] = &vp_clk_src.clkr, 2919 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2920 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2921 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2922 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2923 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2924 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2925 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2926 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2927 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2928 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2929 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2930 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2931 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2932 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, 2933 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, 2934 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2935 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2936 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2937 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2938 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 2939 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 2940 [MAPLE_CLK_SRC] = &maple_clk_src.clkr, 2941 [VDP_CLK_SRC] = &vdp_clk_src.clkr, 2942 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr, 2943 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr, 2944 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr, 2945 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr, 2946 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr, 2947 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr, 2948 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr, 2949 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr, 2950 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr, 2951 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 2952 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, 2953 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, 2954 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2955 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2956 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, 2957 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2958 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2959 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2960 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2961 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, 2962 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2963 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2964 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2965 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2966 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, 2967 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2968 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2969 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2970 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2971 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, 2972 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2973 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2974 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2975 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2976 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 2977 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 2978 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2979 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, 2980 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, 2981 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, 2982 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, 2983 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, 2984 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2985 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2986 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2987 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2988 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2989 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, 2990 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, 2991 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, 2992 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2993 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, 2994 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, 2995 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, 2996 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, 2997 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, 2998 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, 2999 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 3000 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 3001 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 3002 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 3003 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, 3004 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, 3005 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, 3006 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 3007 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 3008 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 3009 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, 3010 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 3011 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 3012 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 3013 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 3014 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 3015 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 3016 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr, 3017 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr, 3018 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, 3019 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, 3020 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, 3021 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, 3022 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, 3023 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, 3024 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, 3025 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, 3026 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, 3027 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr, 3028 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, 3029 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, 3030 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, 3031 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr, 3032 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr, 3033 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, 3034 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, 3035 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr, 3036 [VPU_AXI_CLK] = &vpu_axi_clk.clkr, 3037 [VPU_BUS_CLK] = &vpu_bus_clk.clkr, 3038 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr, 3039 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr, 3040 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr, 3041 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr, 3042 }; 3043 3044 static const struct qcom_reset_map mmcc_apq8084_resets[] = { 3045 [MMSS_SPDM_RESET] = { 0x0200 }, 3046 [MMSS_SPDM_RM_RESET] = { 0x0300 }, 3047 [VENUS0_RESET] = { 0x1020 }, 3048 [VPU_RESET] = { 0x1400 }, 3049 [MDSS_RESET] = { 0x2300 }, 3050 [AVSYNC_RESET] = { 0x2400 }, 3051 [CAMSS_PHY0_RESET] = { 0x3020 }, 3052 [CAMSS_PHY1_RESET] = { 0x3050 }, 3053 [CAMSS_PHY2_RESET] = { 0x3080 }, 3054 [CAMSS_CSI0_RESET] = { 0x30b0 }, 3055 [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, 3056 [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, 3057 [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, 3058 [CAMSS_CSI1_RESET] = { 0x3120 }, 3059 [CAMSS_CSI1PHY_RESET] = { 0x3130 }, 3060 [CAMSS_CSI1RDI_RESET] = { 0x3140 }, 3061 [CAMSS_CSI1PIX_RESET] = { 0x3150 }, 3062 [CAMSS_CSI2_RESET] = { 0x3180 }, 3063 [CAMSS_CSI2PHY_RESET] = { 0x3190 }, 3064 [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, 3065 [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, 3066 [CAMSS_CSI3_RESET] = { 0x31e0 }, 3067 [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, 3068 [CAMSS_CSI3RDI_RESET] = { 0x3200 }, 3069 [CAMSS_CSI3PIX_RESET] = { 0x3210 }, 3070 [CAMSS_ISPIF_RESET] = { 0x3220 }, 3071 [CAMSS_CCI_RESET] = { 0x3340 }, 3072 [CAMSS_MCLK0_RESET] = { 0x3380 }, 3073 [CAMSS_MCLK1_RESET] = { 0x33b0 }, 3074 [CAMSS_MCLK2_RESET] = { 0x33e0 }, 3075 [CAMSS_MCLK3_RESET] = { 0x3410 }, 3076 [CAMSS_GP0_RESET] = { 0x3440 }, 3077 [CAMSS_GP1_RESET] = { 0x3470 }, 3078 [CAMSS_TOP_RESET] = { 0x3480 }, 3079 [CAMSS_AHB_RESET] = { 0x3488 }, 3080 [CAMSS_MICRO_RESET] = { 0x3490 }, 3081 [CAMSS_JPEG_RESET] = { 0x35a0 }, 3082 [CAMSS_VFE_RESET] = { 0x36a0 }, 3083 [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, 3084 [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, 3085 [OXILI_RESET] = { 0x4020 }, 3086 [OXILICX_RESET] = { 0x4030 }, 3087 [OCMEMCX_RESET] = { 0x4050 }, 3088 [MMSS_RBCRP_RESET] = { 0x4080 }, 3089 [MMSSNOCAHB_RESET] = { 0x5020 }, 3090 [MMSSNOCAXI_RESET] = { 0x5060 }, 3091 }; 3092 3093 static struct gdsc *mmcc_apq8084_gdscs[] = { 3094 [VENUS0_GDSC] = &venus0_gdsc, 3095 [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc, 3096 [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc, 3097 [MDSS_GDSC] = &mdss_gdsc, 3098 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, 3099 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, 3100 [OXILI_GDSC] = &oxili_gdsc, 3101 [OXILICX_GDSC] = &oxilicx_gdsc, 3102 }; 3103 3104 static const struct regmap_config mmcc_apq8084_regmap_config = { 3105 .reg_bits = 32, 3106 .reg_stride = 4, 3107 .val_bits = 32, 3108 .max_register = 0x5104, 3109 .fast_io = true, 3110 }; 3111 3112 static const struct qcom_cc_desc mmcc_apq8084_desc = { 3113 .config = &mmcc_apq8084_regmap_config, 3114 .clks = mmcc_apq8084_clocks, 3115 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks), 3116 .resets = mmcc_apq8084_resets, 3117 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets), 3118 .gdscs = mmcc_apq8084_gdscs, 3119 .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs), 3120 }; 3121 3122 static const struct of_device_id mmcc_apq8084_match_table[] = { 3123 { .compatible = "qcom,mmcc-apq8084" }, 3124 { } 3125 }; 3126 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table); 3127 3128 static int mmcc_apq8084_probe(struct platform_device *pdev) 3129 { 3130 int ret; 3131 struct regmap *regmap; 3132 3133 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc); 3134 if (ret) 3135 return ret; 3136 3137 regmap = dev_get_regmap(&pdev->dev, NULL); 3138 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 3139 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 3140 3141 return 0; 3142 } 3143 3144 static struct platform_driver mmcc_apq8084_driver = { 3145 .probe = mmcc_apq8084_probe, 3146 .driver = { 3147 .name = "mmcc-apq8084", 3148 .of_match_table = mmcc_apq8084_match_table, 3149 }, 3150 }; 3151 module_platform_driver(mmcc_apq8084_driver); 3152 3153 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver"); 3154 MODULE_LICENSE("GPL v2"); 3155 MODULE_ALIAS("platform:mmcc-apq8084"); 3156