1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_clock.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "common.h" 21 #include "gdsc.h" 22 23 enum { 24 P_BI_TCXO, 25 P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 26 P_SLEEP_CLK, 27 }; 28 29 static const struct pll_vco fabia_vco[] = { 30 { 249600000, 2000000000, 0 }, 31 }; 32 33 static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = { 34 .l = 0x20, 35 .alpha = 0x0, 36 .config_ctl_val = 0x20485699, 37 .config_ctl_hi_val = 0x00002067, 38 .test_ctl_val = 0x40000000, 39 .test_ctl_hi_val = 0x00000000, 40 .user_ctl_val = 0x00005105, 41 .user_ctl_hi_val = 0x00004805, 42 }; 43 44 static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 45 [CLK_ALPHA_PLL_TYPE_FABIA] = { 46 [PLL_OFF_L_VAL] = 0x04, 47 [PLL_OFF_CAL_L_VAL] = 0x8, 48 [PLL_OFF_USER_CTL] = 0x0c, 49 [PLL_OFF_USER_CTL_U] = 0x10, 50 [PLL_OFF_USER_CTL_U1] = 0x14, 51 [PLL_OFF_CONFIG_CTL] = 0x18, 52 [PLL_OFF_CONFIG_CTL_U] = 0x1C, 53 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 54 [PLL_OFF_TEST_CTL] = 0x24, 55 [PLL_OFF_TEST_CTL_U] = 0x28, 56 [PLL_OFF_STATUS] = 0x30, 57 [PLL_OFF_OPMODE] = 0x38, 58 [PLL_OFF_FRAC] = 0x40, 59 }, 60 }; 61 62 static struct clk_alpha_pll lpass_lpaaudio_dig_pll = { 63 .offset = 0x1000, 64 .vco_table = fabia_vco, 65 .num_vco = ARRAY_SIZE(fabia_vco), 66 .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA], 67 .clkr = { 68 .hw.init = &(struct clk_init_data){ 69 .name = "lpass_lpaaudio_dig_pll", 70 .parent_data = &(const struct clk_parent_data){ 71 .fw_name = "bi_tcxo", 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_fabia_ops, 75 }, 76 }, 77 }; 78 79 static const struct clk_div_table 80 post_div_table_lpass_lpaaudio_dig_pll_out_odd[] = { 81 { 0x5, 5 }, 82 { } 83 }; 84 85 static struct clk_alpha_pll_postdiv lpass_lpaaudio_dig_pll_out_odd = { 86 .offset = 0x1000, 87 .post_div_shift = 12, 88 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd, 89 .num_post_div = 90 ARRAY_SIZE(post_div_table_lpass_lpaaudio_dig_pll_out_odd), 91 .width = 4, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 93 .clkr.hw.init = &(struct clk_init_data){ 94 .name = "lpass_lpaaudio_dig_pll_out_odd", 95 .parent_hws = (const struct clk_hw*[]) { 96 &lpass_lpaaudio_dig_pll.clkr.hw, 97 }, 98 .num_parents = 1, 99 .flags = CLK_SET_RATE_PARENT, 100 .ops = &clk_alpha_pll_postdiv_fabia_ops, 101 }, 102 }; 103 104 static const struct parent_map lpass_core_cc_parent_map_0[] = { 105 { P_BI_TCXO, 0 }, 106 { P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5 }, 107 }; 108 109 static const struct clk_parent_data lpass_core_cc_parent_data_0[] = { 110 { .fw_name = "bi_tcxo" }, 111 { .hw = &lpass_lpaaudio_dig_pll_out_odd.clkr.hw }, 112 }; 113 114 static const struct parent_map lpass_core_cc_parent_map_2[] = { 115 { P_BI_TCXO, 0 }, 116 }; 117 118 static struct clk_rcg2 core_clk_src = { 119 .cmd_rcgr = 0x1d000, 120 .mnd_width = 8, 121 .hid_width = 5, 122 .parent_map = lpass_core_cc_parent_map_2, 123 .clkr.hw.init = &(struct clk_init_data){ 124 .name = "core_clk_src", 125 .parent_data = &(const struct clk_parent_data){ 126 .fw_name = "bi_tcxo", 127 }, 128 .num_parents = 1, 129 .ops = &clk_rcg2_ops, 130 }, 131 }; 132 133 static const struct freq_tbl ftbl_ext_mclk0_clk_src[] = { 134 F(9600000, P_BI_TCXO, 2, 0, 0), 135 F(19200000, P_BI_TCXO, 1, 0, 0), 136 { } 137 }; 138 139 static const struct freq_tbl ftbl_ext_lpaif_clk_src[] = { 140 F(256000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 32), 141 F(512000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 16), 142 F(768000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 16), 143 F(1024000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 8), 144 F(1536000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 8), 145 F(2048000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 4), 146 F(3072000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 4), 147 F(4096000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 2), 148 F(6144000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 2), 149 F(8192000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 0, 0), 150 F(9600000, P_BI_TCXO, 2, 0, 0), 151 F(12288000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 0, 0), 152 F(19200000, P_BI_TCXO, 1, 0, 0), 153 F(24576000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5, 0, 0), 154 { } 155 }; 156 157 static struct clk_rcg2 ext_mclk0_clk_src = { 158 .cmd_rcgr = 0x20000, 159 .mnd_width = 8, 160 .hid_width = 5, 161 .parent_map = lpass_core_cc_parent_map_0, 162 .freq_tbl = ftbl_ext_mclk0_clk_src, 163 .clkr.hw.init = &(struct clk_init_data){ 164 .name = "ext_mclk0_clk_src", 165 .parent_data = lpass_core_cc_parent_data_0, 166 .num_parents = 2, 167 .flags = CLK_SET_RATE_PARENT, 168 .ops = &clk_rcg2_ops, 169 }, 170 }; 171 172 static struct clk_rcg2 lpaif_pri_clk_src = { 173 .cmd_rcgr = 0x10000, 174 .mnd_width = 16, 175 .hid_width = 5, 176 .parent_map = lpass_core_cc_parent_map_0, 177 .freq_tbl = ftbl_ext_lpaif_clk_src, 178 .clkr.hw.init = &(struct clk_init_data){ 179 .name = "lpaif_pri_clk_src", 180 .parent_data = lpass_core_cc_parent_data_0, 181 .num_parents = 2, 182 .flags = CLK_SET_RATE_PARENT, 183 .ops = &clk_rcg2_ops, 184 }, 185 }; 186 187 static struct clk_rcg2 lpaif_sec_clk_src = { 188 .cmd_rcgr = 0x11000, 189 .mnd_width = 16, 190 .hid_width = 5, 191 .parent_map = lpass_core_cc_parent_map_0, 192 .freq_tbl = ftbl_ext_lpaif_clk_src, 193 .clkr.hw.init = &(struct clk_init_data){ 194 .name = "lpaif_sec_clk_src", 195 .parent_data = lpass_core_cc_parent_data_0, 196 .num_parents = 2, 197 .flags = CLK_SET_RATE_PARENT, 198 .ops = &clk_rcg2_ops, 199 }, 200 }; 201 202 static struct clk_branch lpass_audio_core_ext_mclk0_clk = { 203 .halt_reg = 0x20014, 204 .halt_check = BRANCH_HALT, 205 .hwcg_reg = 0x20014, 206 .hwcg_bit = 1, 207 .clkr = { 208 .enable_reg = 0x20014, 209 .enable_mask = BIT(0), 210 .hw.init = &(struct clk_init_data){ 211 .name = "lpass_audio_core_ext_mclk0_clk", 212 .parent_hws = (const struct clk_hw*[]) { 213 &ext_mclk0_clk_src.clkr.hw, 214 }, 215 .num_parents = 1, 216 .flags = CLK_SET_RATE_PARENT, 217 .ops = &clk_branch2_ops, 218 }, 219 }, 220 }; 221 222 static struct clk_branch lpass_audio_core_lpaif_pri_ibit_clk = { 223 .halt_reg = 0x10018, 224 .halt_check = BRANCH_HALT, 225 .hwcg_reg = 0x10018, 226 .hwcg_bit = 1, 227 .clkr = { 228 .enable_reg = 0x10018, 229 .enable_mask = BIT(0), 230 .hw.init = &(struct clk_init_data){ 231 .name = "lpass_audio_core_lpaif_pri_ibit_clk", 232 .parent_hws = (const struct clk_hw*[]) { 233 &lpaif_pri_clk_src.clkr.hw, 234 }, 235 .num_parents = 1, 236 .flags = CLK_SET_RATE_PARENT, 237 .ops = &clk_branch2_ops, 238 }, 239 }, 240 }; 241 242 static struct clk_branch lpass_audio_core_lpaif_sec_ibit_clk = { 243 .halt_reg = 0x11018, 244 .halt_check = BRANCH_HALT, 245 .hwcg_reg = 0x11018, 246 .hwcg_bit = 1, 247 .clkr = { 248 .enable_reg = 0x11018, 249 .enable_mask = BIT(0), 250 .hw.init = &(struct clk_init_data){ 251 .name = "lpass_audio_core_lpaif_sec_ibit_clk", 252 .parent_hws = (const struct clk_hw*[]) { 253 &lpaif_sec_clk_src.clkr.hw, 254 }, 255 .num_parents = 1, 256 .flags = CLK_SET_RATE_PARENT, 257 .ops = &clk_branch2_ops, 258 }, 259 }, 260 }; 261 262 static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = { 263 .halt_reg = 0x23000, 264 .halt_check = BRANCH_HALT, 265 .hwcg_reg = 0x23000, 266 .hwcg_bit = 1, 267 .clkr = { 268 .enable_reg = 0x23000, 269 .enable_mask = BIT(0), 270 .hw.init = &(struct clk_init_data){ 271 .name = "lpass_audio_core_sysnoc_mport_core_clk", 272 .parent_hws = (const struct clk_hw*[]) { 273 &core_clk_src.clkr.hw, 274 }, 275 .num_parents = 1, 276 .flags = CLK_SET_RATE_PARENT, 277 .ops = &clk_branch2_ops, 278 }, 279 }, 280 }; 281 282 static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = { 283 [EXT_MCLK0_CLK_SRC] = &ext_mclk0_clk_src.clkr, 284 [LPAIF_PRI_CLK_SRC] = &lpaif_pri_clk_src.clkr, 285 [LPAIF_SEC_CLK_SRC] = &lpaif_sec_clk_src.clkr, 286 [CORE_CLK_SRC] = &core_clk_src.clkr, 287 [LPASS_AUDIO_CORE_EXT_MCLK0_CLK] = &lpass_audio_core_ext_mclk0_clk.clkr, 288 [LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] = 289 &lpass_audio_core_lpaif_pri_ibit_clk.clkr, 290 [LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] = 291 &lpass_audio_core_lpaif_sec_ibit_clk.clkr, 292 [LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] = 293 &lpass_audio_core_sysnoc_mport_core_clk.clkr, 294 [LPASS_LPAAUDIO_DIG_PLL] = &lpass_lpaaudio_dig_pll.clkr, 295 [LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] = &lpass_lpaaudio_dig_pll_out_odd.clkr, 296 }; 297 298 static struct gdsc lpass_pdc_hm_gdsc = { 299 .gdscr = 0x3090, 300 .pd = { 301 .name = "lpass_pdc_hm_gdsc", 302 }, 303 .pwrsts = PWRSTS_OFF_ON, 304 .flags = VOTABLE, 305 }; 306 307 static struct gdsc lpass_audio_hm_gdsc = { 308 .gdscr = 0x9090, 309 .pd = { 310 .name = "lpass_audio_hm_gdsc", 311 }, 312 .pwrsts = PWRSTS_OFF_ON, 313 }; 314 315 static struct gdsc lpass_core_hm_gdsc = { 316 .gdscr = 0x0, 317 .pd = { 318 .name = "lpass_core_hm_gdsc", 319 }, 320 .pwrsts = PWRSTS_OFF_ON, 321 .flags = RETAIN_FF_ENABLE, 322 }; 323 324 static struct gdsc *lpass_core_hm_sc7180_gdscs[] = { 325 [LPASS_CORE_HM_GDSCR] = &lpass_core_hm_gdsc, 326 }; 327 328 static struct gdsc *lpass_audio_hm_sc7180_gdscs[] = { 329 [LPASS_PDC_HM_GDSCR] = &lpass_pdc_hm_gdsc, 330 [LPASS_AUDIO_HM_GDSCR] = &lpass_audio_hm_gdsc, 331 }; 332 333 static struct regmap_config lpass_core_cc_sc7180_regmap_config = { 334 .reg_bits = 32, 335 .reg_stride = 4, 336 .val_bits = 32, 337 .fast_io = true, 338 }; 339 340 static const struct qcom_cc_desc lpass_core_hm_sc7180_desc = { 341 .config = &lpass_core_cc_sc7180_regmap_config, 342 .gdscs = lpass_core_hm_sc7180_gdscs, 343 .num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7180_gdscs), 344 }; 345 346 static const struct qcom_cc_desc lpass_core_cc_sc7180_desc = { 347 .config = &lpass_core_cc_sc7180_regmap_config, 348 .clks = lpass_core_cc_sc7180_clocks, 349 .num_clks = ARRAY_SIZE(lpass_core_cc_sc7180_clocks), 350 }; 351 352 static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = { 353 .config = &lpass_core_cc_sc7180_regmap_config, 354 .gdscs = lpass_audio_hm_sc7180_gdscs, 355 .num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs), 356 }; 357 358 static int lpass_setup_runtime_pm(struct platform_device *pdev) 359 { 360 int ret; 361 362 pm_runtime_use_autosuspend(&pdev->dev); 363 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); 364 365 ret = devm_pm_runtime_enable(&pdev->dev); 366 if (ret) 367 return ret; 368 369 ret = devm_pm_clk_create(&pdev->dev); 370 if (ret) 371 return ret; 372 373 ret = pm_clk_add(&pdev->dev, "iface"); 374 if (ret < 0) 375 dev_err(&pdev->dev, "failed to acquire iface clock\n"); 376 377 return pm_runtime_resume_and_get(&pdev->dev); 378 } 379 380 static int lpass_core_cc_sc7180_probe(struct platform_device *pdev) 381 { 382 const struct qcom_cc_desc *desc; 383 struct regmap *regmap; 384 int ret; 385 386 ret = lpass_setup_runtime_pm(pdev); 387 if (ret) 388 return ret; 389 390 lpass_core_cc_sc7180_regmap_config.name = "lpass_audio_cc"; 391 desc = &lpass_audio_hm_sc7180_desc; 392 ret = qcom_cc_probe_by_index(pdev, 1, desc); 393 if (ret) 394 goto exit; 395 396 lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc"; 397 regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc); 398 if (IS_ERR(regmap)) { 399 ret = PTR_ERR(regmap); 400 goto exit; 401 } 402 403 /* Keep some clocks always-on */ 404 qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ 405 406 /* PLL settings */ 407 regmap_write(regmap, 0x1008, 0x20); 408 regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0)); 409 410 clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap, 411 &lpass_lpaaudio_dig_pll_config); 412 413 ret = qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7180_desc, regmap); 414 415 pm_runtime_mark_last_busy(&pdev->dev); 416 exit: 417 pm_runtime_put_autosuspend(&pdev->dev); 418 419 return ret; 420 } 421 422 static int lpass_hm_core_probe(struct platform_device *pdev) 423 { 424 const struct qcom_cc_desc *desc; 425 int ret; 426 427 ret = lpass_setup_runtime_pm(pdev); 428 if (ret) 429 return ret; 430 431 lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core"; 432 desc = &lpass_core_hm_sc7180_desc; 433 434 ret = qcom_cc_probe_by_index(pdev, 0, desc); 435 436 pm_runtime_mark_last_busy(&pdev->dev); 437 pm_runtime_put_autosuspend(&pdev->dev); 438 439 return ret; 440 } 441 442 static const struct of_device_id lpass_hm_sc7180_match_table[] = { 443 { 444 .compatible = "qcom,sc7180-lpasshm", 445 }, 446 { } 447 }; 448 MODULE_DEVICE_TABLE(of, lpass_hm_sc7180_match_table); 449 450 static const struct of_device_id lpass_core_cc_sc7180_match_table[] = { 451 { 452 .compatible = "qcom,sc7180-lpasscorecc", 453 }, 454 { } 455 }; 456 MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table); 457 458 static const struct dev_pm_ops lpass_pm_ops = { 459 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 460 }; 461 462 static struct platform_driver lpass_core_cc_sc7180_driver = { 463 .probe = lpass_core_cc_sc7180_probe, 464 .driver = { 465 .name = "lpass_core_cc-sc7180", 466 .of_match_table = lpass_core_cc_sc7180_match_table, 467 .pm = &lpass_pm_ops, 468 }, 469 }; 470 471 static struct platform_driver lpass_hm_sc7180_driver = { 472 .probe = lpass_hm_core_probe, 473 .driver = { 474 .name = "lpass_hm-sc7180", 475 .of_match_table = lpass_hm_sc7180_match_table, 476 .pm = &lpass_pm_ops, 477 }, 478 }; 479 480 static int __init lpass_sc7180_init(void) 481 { 482 int ret; 483 484 ret = platform_driver_register(&lpass_core_cc_sc7180_driver); 485 if (ret) 486 return ret; 487 488 ret = platform_driver_register(&lpass_hm_sc7180_driver); 489 if (ret) { 490 platform_driver_unregister(&lpass_core_cc_sc7180_driver); 491 return ret; 492 } 493 494 return 0; 495 } 496 subsys_initcall(lpass_sc7180_init); 497 498 static void __exit lpass_sc7180_exit(void) 499 { 500 platform_driver_unregister(&lpass_hm_sc7180_driver); 501 platform_driver_unregister(&lpass_core_cc_sc7180_driver); 502 } 503 module_exit(lpass_sc7180_exit); 504 505 MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7180 Driver"); 506 MODULE_LICENSE("GPL v2"); 507