1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 /* 7 * CMN PLL block expects the reference clock from on-board Wi-Fi block, 8 * and supplies fixed rate clocks as output to the networking hardware 9 * blocks and to GCC. The networking related blocks include PPE (packet 10 * process engine), the externally connected PHY or switch devices, and 11 * the PCS. 12 * 13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock 14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), 15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks 16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS 17 * with 31.25 MHZ. 18 * 19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, 20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output 21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. 22 * 23 * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to 24 * the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200 25 * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS 26 * are the same as those in the IPQ9574 SoC. 27 * 28 * +---------+ 29 * | GCC | 30 * +--+---+--+ 31 * AHB CLK| |SYS CLK 32 * V V 33 * +-------+---+------+ 34 * | +-------------> eth0-50mhz 35 * REF CLK | IPQ9574 | 36 * -------->+ +-------------> eth1-50mhz 37 * | CMN PLL block | 38 * | +-------------> eth2-50mhz 39 * | | 40 * +----+----+----+---+-------------> eth-25mhz 41 * | | | 42 * V V V 43 * GCC PCS NSS/PPE 44 */ 45 46 #include <linux/bitfield.h> 47 #include <linux/clk-provider.h> 48 #include <linux/delay.h> 49 #include <linux/err.h> 50 #include <linux/module.h> 51 #include <linux/platform_device.h> 52 #include <linux/pm_clock.h> 53 #include <linux/pm_runtime.h> 54 #include <linux/regmap.h> 55 56 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 57 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 58 #include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h> 59 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 60 #include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h> 61 #include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h> 62 63 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 64 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) 65 66 #define CMN_PLL_LOCKED 0x64 67 #define CMN_PLL_CLKS_LOCKED BIT(8) 68 69 #define CMN_PLL_POWER_ON_AND_RESET 0x780 70 #define CMN_ANA_EN_SW_RSTN BIT(6) 71 72 #define CMN_PLL_REFCLK_CONFIG 0x784 73 #define CMN_PLL_REFCLK_EXTERNAL BIT(9) 74 #define CMN_PLL_REFCLK_DIV GENMASK(8, 4) 75 #define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) 76 77 #define CMN_PLL_CTRL 0x78c 78 #define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) 79 80 #define CMN_PLL_DIVIDER_CTRL 0x794 81 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) 82 83 /** 84 * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information 85 * @id: Clock specifier to be supplied 86 * @name: Clock name to be registered 87 * @rate: Clock rate 88 */ 89 struct cmn_pll_fixed_output_clk { 90 unsigned int id; 91 const char *name; 92 unsigned long rate; 93 }; 94 95 /** 96 * struct clk_cmn_pll - CMN PLL hardware specific data 97 * @regmap: hardware regmap. 98 * @hw: handle between common and hardware-specific interfaces 99 */ 100 struct clk_cmn_pll { 101 struct regmap *regmap; 102 struct clk_hw hw; 103 }; 104 105 #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ 106 .id = _id, \ 107 .name = _name, \ 108 .rate = _rate, \ 109 } 110 111 #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) 112 113 static const struct regmap_config ipq_cmn_pll_regmap_config = { 114 .reg_bits = 32, 115 .reg_stride = 4, 116 .val_bits = 32, 117 .max_register = 0x7fc, 118 }; 119 120 static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { 121 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 122 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 123 CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 124 { /* Sentinel */ } 125 }; 126 127 static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = { 128 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 129 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 130 { /* Sentinel */ } 131 }; 132 133 static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = { 134 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 135 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 136 { /* Sentinel */ } 137 }; 138 139 static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = { 140 CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 141 CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 142 CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 143 CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 144 CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL), 145 CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 146 { /* Sentinel */ } 147 }; 148 149 static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { 150 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 151 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 152 CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 153 CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 154 CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), 155 CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 156 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 157 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 158 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 159 { /* Sentinel */ } 160 }; 161 162 static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 163 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 164 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 165 CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 166 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 167 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 168 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 169 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 170 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 171 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 172 { /* Sentinel */ } 173 }; 174 175 /* 176 * CMN PLL has the single parent clock, which supports the several 177 * possible parent clock rates, each parent clock rate is reflected 178 * by the specific reference index value in the hardware. 179 */ 180 static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) 181 { 182 int index = -EINVAL; 183 184 switch (parent_rate) { 185 case 25000000: 186 index = 3; 187 break; 188 case 31250000: 189 index = 4; 190 break; 191 case 40000000: 192 index = 6; 193 break; 194 case 48000000: 195 case 96000000: 196 /* 197 * Parent clock rate 48 MHZ and 96 MHZ take the same value 198 * of reference clock index. 96 MHZ needs the source clock 199 * divider to be programmed as 2. 200 */ 201 index = 7; 202 break; 203 case 50000000: 204 index = 8; 205 break; 206 default: 207 break; 208 } 209 210 return index; 211 } 212 213 static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, 214 unsigned long parent_rate) 215 { 216 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 217 u32 val, factor, ref_div; 218 219 /* 220 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted 221 * by HW according to the parent clock rate. 222 */ 223 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); 224 factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); 225 if (WARN_ON(factor == 0)) 226 factor = 1; 227 228 regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val); 229 ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val); 230 if (WARN_ON(ref_div == 0)) 231 ref_div = 1; 232 233 return div_u64((u64)parent_rate * 2 * factor, ref_div); 234 } 235 236 static int clk_cmn_pll_determine_rate(struct clk_hw *hw, 237 struct clk_rate_request *req) 238 { 239 int ret; 240 241 /* Validate the rate of the single parent clock. */ 242 ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); 243 244 return ret < 0 ? ret : 0; 245 } 246 247 /* 248 * This function is used to initialize the CMN PLL to enable the fixed 249 * rate output clocks. It is expected to be configured once. 250 */ 251 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, 252 unsigned long parent_rate) 253 { 254 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 255 int ret, index; 256 u32 val; 257 258 /* 259 * Configure the reference input clock selection as per the given 260 * parent clock. The output clock rates are always of fixed value. 261 */ 262 index = ipq_cmn_pll_find_freq_index(parent_rate); 263 if (index < 0) 264 return index; 265 266 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 267 CMN_PLL_REFCLK_INDEX, 268 FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); 269 if (ret) 270 return ret; 271 272 /* 273 * Update the source clock rate selection and source clock 274 * divider as 2 when the parent clock rate is 96 MHZ. 275 */ 276 if (parent_rate == 96000000) { 277 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 278 CMN_PLL_REFCLK_DIV, 279 FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); 280 if (ret) 281 return ret; 282 283 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, 284 CMN_PLL_REFCLK_SRC_DIV, 285 FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); 286 if (ret) 287 return ret; 288 } 289 290 /* Enable PLL locked detect. */ 291 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, 292 CMN_PLL_CTRL_LOCK_DETECT_EN); 293 if (ret) 294 return ret; 295 296 /* 297 * Reset the CMN PLL block to ensure the updated configurations 298 * take effect. 299 */ 300 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 301 CMN_ANA_EN_SW_RSTN); 302 if (ret) 303 return ret; 304 305 usleep_range(1000, 1200); 306 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 307 CMN_ANA_EN_SW_RSTN); 308 if (ret) 309 return ret; 310 311 /* Stability check of CMN PLL output clocks. */ 312 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, 313 (val & CMN_PLL_CLKS_LOCKED), 314 100, 100 * USEC_PER_MSEC); 315 } 316 317 static const struct clk_ops clk_cmn_pll_ops = { 318 .recalc_rate = clk_cmn_pll_recalc_rate, 319 .determine_rate = clk_cmn_pll_determine_rate, 320 .set_rate = clk_cmn_pll_set_rate, 321 }; 322 323 static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) 324 { 325 struct clk_parent_data pdata = { .index = 0 }; 326 struct device *dev = &pdev->dev; 327 struct clk_init_data init = {}; 328 struct clk_cmn_pll *cmn_pll; 329 struct regmap *regmap; 330 void __iomem *base; 331 int ret; 332 333 base = devm_platform_ioremap_resource(pdev, 0); 334 if (IS_ERR(base)) 335 return ERR_CAST(base); 336 337 regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); 338 if (IS_ERR(regmap)) 339 return ERR_CAST(regmap); 340 341 cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); 342 if (!cmn_pll) 343 return ERR_PTR(-ENOMEM); 344 345 init.name = "cmn_pll"; 346 init.parent_data = &pdata; 347 init.num_parents = 1; 348 init.ops = &clk_cmn_pll_ops; 349 350 cmn_pll->hw.init = &init; 351 cmn_pll->regmap = regmap; 352 353 ret = devm_clk_hw_register(dev, &cmn_pll->hw); 354 if (ret) 355 return ERR_PTR(ret); 356 357 return &cmn_pll->hw; 358 } 359 360 static int ipq_cmn_pll_register_clks(struct platform_device *pdev) 361 { 362 const struct cmn_pll_fixed_output_clk *p, *fixed_clk; 363 struct clk_hw_onecell_data *hw_data; 364 struct device *dev = &pdev->dev; 365 struct clk_hw *cmn_pll_hw; 366 unsigned int num_clks; 367 struct clk_hw *hw; 368 int ret, i; 369 370 fixed_clk = device_get_match_data(dev); 371 if (!fixed_clk) 372 return -EINVAL; 373 374 num_clks = 0; 375 for (p = fixed_clk; p->name; p++) 376 num_clks++; 377 378 hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), 379 GFP_KERNEL); 380 if (!hw_data) 381 return -ENOMEM; 382 383 /* 384 * Register the CMN PLL clock, which is the parent clock of 385 * the fixed rate output clocks. 386 */ 387 cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); 388 if (IS_ERR(cmn_pll_hw)) 389 return PTR_ERR(cmn_pll_hw); 390 391 /* Register the fixed rate output clocks. */ 392 for (i = 0; i < num_clks; i++) { 393 hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, 394 cmn_pll_hw, 0, 395 fixed_clk[i].rate); 396 if (IS_ERR(hw)) { 397 ret = PTR_ERR(hw); 398 goto unregister_fixed_clk; 399 } 400 401 hw_data->hws[fixed_clk[i].id] = hw; 402 } 403 404 /* 405 * Provide the CMN PLL clock. The clock rate of CMN PLL 406 * is configured to 12 GHZ by DT property assigned-clock-rates-u64. 407 */ 408 hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; 409 hw_data->num = num_clks + 1; 410 411 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); 412 if (ret) 413 goto unregister_fixed_clk; 414 415 platform_set_drvdata(pdev, hw_data); 416 417 return 0; 418 419 unregister_fixed_clk: 420 while (i > 0) 421 clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); 422 423 return ret; 424 } 425 426 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) 427 { 428 struct device *dev = &pdev->dev; 429 int ret; 430 431 ret = devm_pm_runtime_enable(dev); 432 if (ret) 433 return ret; 434 435 ret = devm_pm_clk_create(dev); 436 if (ret) 437 return ret; 438 439 /* 440 * To access the CMN PLL registers, the GCC AHB & SYS clocks 441 * of CMN PLL block need to be enabled. 442 */ 443 ret = pm_clk_add(dev, "ahb"); 444 if (ret) 445 return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); 446 447 ret = pm_clk_add(dev, "sys"); 448 if (ret) 449 return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); 450 451 ret = pm_runtime_resume_and_get(dev); 452 if (ret) 453 return ret; 454 455 /* Register CMN PLL clock and fixed rate output clocks. */ 456 ret = ipq_cmn_pll_register_clks(pdev); 457 pm_runtime_put(dev); 458 if (ret) 459 return dev_err_probe(dev, ret, 460 "Failed to register CMN PLL clocks\n"); 461 462 return 0; 463 } 464 465 static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) 466 { 467 struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); 468 int i; 469 470 /* 471 * The clock with index CMN_PLL_CLK is unregistered by 472 * device management. 473 */ 474 for (i = 0; i < hw_data->num; i++) { 475 if (i != CMN_PLL_CLK) 476 clk_hw_unregister(hw_data->hws[i]); 477 } 478 } 479 480 static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { 481 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 482 }; 483 484 static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 485 { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, 486 { .compatible = "qcom,ipq5332-cmn-pll", .data = &ipq5332_output_clks }, 487 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, 488 { .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks }, 489 { .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks }, 490 { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 491 { } 492 }; 493 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); 494 495 static struct platform_driver ipq_cmn_pll_clk_driver = { 496 .probe = ipq_cmn_pll_clk_probe, 497 .remove = ipq_cmn_pll_clk_remove, 498 .driver = { 499 .name = "ipq_cmn_pll", 500 .of_match_table = ipq_cmn_pll_clk_ids, 501 .pm = &ipq_cmn_pll_pm_ops, 502 }, 503 }; 504 module_platform_driver(ipq_cmn_pll_clk_driver); 505 506 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); 507 MODULE_LICENSE("GPL"); 508