1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 /* 7 * CMN PLL block expects the reference clock from on-board Wi-Fi block, 8 * and supplies fixed rate clocks as output to the networking hardware 9 * blocks and to GCC. The networking related blocks include PPE (packet 10 * process engine), the externally connected PHY or switch devices, and 11 * the PCS. 12 * 13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock 14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), 15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks 16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS 17 * with 31.25 MHZ. 18 * 19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, 20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output 21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. 22 * 23 * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to 24 * the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200 25 * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS 26 * are the same as those in the IPQ9574 SoC. 27 * 28 * +---------+ 29 * | GCC | 30 * +--+---+--+ 31 * AHB CLK| |SYS CLK 32 * V V 33 * +-------+---+------+ 34 * | +-------------> eth0-50mhz 35 * REF CLK | IPQ9574 | 36 * -------->+ +-------------> eth1-50mhz 37 * | CMN PLL block | 38 * | +-------------> eth2-50mhz 39 * | | 40 * +----+----+----+---+-------------> eth-25mhz 41 * | | | 42 * V V V 43 * GCC PCS NSS/PPE 44 */ 45 46 #include <linux/bitfield.h> 47 #include <linux/clk-provider.h> 48 #include <linux/delay.h> 49 #include <linux/err.h> 50 #include <linux/mod_devicetable.h> 51 #include <linux/module.h> 52 #include <linux/platform_device.h> 53 #include <linux/pm_clock.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/regmap.h> 56 57 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 58 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 59 #include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h> 60 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 61 #include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h> 62 #include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h> 63 64 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 65 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) 66 67 #define CMN_PLL_LOCKED 0x64 68 #define CMN_PLL_CLKS_LOCKED BIT(8) 69 70 #define CMN_PLL_POWER_ON_AND_RESET 0x780 71 #define CMN_ANA_EN_SW_RSTN BIT(6) 72 73 #define CMN_PLL_REFCLK_CONFIG 0x784 74 #define CMN_PLL_REFCLK_EXTERNAL BIT(9) 75 #define CMN_PLL_REFCLK_DIV GENMASK(8, 4) 76 #define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) 77 78 #define CMN_PLL_CTRL 0x78c 79 #define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) 80 81 #define CMN_PLL_DIVIDER_CTRL 0x794 82 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) 83 84 /** 85 * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information 86 * @id: Clock specifier to be supplied 87 * @name: Clock name to be registered 88 * @rate: Clock rate 89 */ 90 struct cmn_pll_fixed_output_clk { 91 unsigned int id; 92 const char *name; 93 unsigned long rate; 94 }; 95 96 /** 97 * struct clk_cmn_pll - CMN PLL hardware specific data 98 * @regmap: hardware regmap. 99 * @hw: handle between common and hardware-specific interfaces 100 */ 101 struct clk_cmn_pll { 102 struct regmap *regmap; 103 struct clk_hw hw; 104 }; 105 106 #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ 107 .id = _id, \ 108 .name = _name, \ 109 .rate = _rate, \ 110 } 111 112 #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) 113 114 static const struct regmap_config ipq_cmn_pll_regmap_config = { 115 .reg_bits = 32, 116 .reg_stride = 4, 117 .val_bits = 32, 118 .max_register = 0x7fc, 119 }; 120 121 static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { 122 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 123 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 124 CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 125 { /* Sentinel */ } 126 }; 127 128 static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] = { 129 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 130 CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 131 { /* Sentinel */ } 132 }; 133 134 static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = { 135 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), 136 CLK_PLL_OUTPUT(IPQ8074_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 416500000UL), 137 { /* Sentinel */ } 138 }; 139 140 static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = { 141 CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 142 CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 143 CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 144 CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 145 CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL), 146 CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 147 { /* Sentinel */ } 148 }; 149 150 static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { 151 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 152 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 153 CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 154 CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 155 CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), 156 CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 157 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 158 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 159 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 160 { /* Sentinel */ } 161 }; 162 163 static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 164 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 165 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 166 CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 167 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 168 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 169 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 170 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 171 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 172 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 173 { /* Sentinel */ } 174 }; 175 176 /* 177 * CMN PLL has the single parent clock, which supports the several 178 * possible parent clock rates, each parent clock rate is reflected 179 * by the specific reference index value in the hardware. 180 */ 181 static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) 182 { 183 int index = -EINVAL; 184 185 switch (parent_rate) { 186 case 25000000: 187 index = 3; 188 break; 189 case 31250000: 190 index = 4; 191 break; 192 case 40000000: 193 index = 6; 194 break; 195 case 48000000: 196 case 96000000: 197 /* 198 * Parent clock rate 48 MHZ and 96 MHZ take the same value 199 * of reference clock index. 96 MHZ needs the source clock 200 * divider to be programmed as 2. 201 */ 202 index = 7; 203 break; 204 case 50000000: 205 index = 8; 206 break; 207 default: 208 break; 209 } 210 211 return index; 212 } 213 214 static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, 215 unsigned long parent_rate) 216 { 217 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 218 u32 val, factor, ref_div; 219 220 /* 221 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted 222 * by HW according to the parent clock rate. 223 */ 224 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); 225 factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); 226 if (WARN_ON(factor == 0)) 227 factor = 1; 228 229 regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val); 230 ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val); 231 if (WARN_ON(ref_div == 0)) 232 ref_div = 1; 233 234 return div_u64((u64)parent_rate * 2 * factor, ref_div); 235 } 236 237 static int clk_cmn_pll_determine_rate(struct clk_hw *hw, 238 struct clk_rate_request *req) 239 { 240 int ret; 241 242 /* Validate the rate of the single parent clock. */ 243 ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); 244 245 return ret < 0 ? ret : 0; 246 } 247 248 /* 249 * This function is used to initialize the CMN PLL to enable the fixed 250 * rate output clocks. It is expected to be configured once. 251 */ 252 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, 253 unsigned long parent_rate) 254 { 255 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 256 int ret, index; 257 u32 val; 258 259 /* 260 * Configure the reference input clock selection as per the given 261 * parent clock. The output clock rates are always of fixed value. 262 */ 263 index = ipq_cmn_pll_find_freq_index(parent_rate); 264 if (index < 0) 265 return index; 266 267 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 268 CMN_PLL_REFCLK_INDEX, 269 FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); 270 if (ret) 271 return ret; 272 273 /* 274 * Update the source clock rate selection and source clock 275 * divider as 2 when the parent clock rate is 96 MHZ. 276 */ 277 if (parent_rate == 96000000) { 278 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 279 CMN_PLL_REFCLK_DIV, 280 FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); 281 if (ret) 282 return ret; 283 284 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, 285 CMN_PLL_REFCLK_SRC_DIV, 286 FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); 287 if (ret) 288 return ret; 289 } 290 291 /* Enable PLL locked detect. */ 292 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, 293 CMN_PLL_CTRL_LOCK_DETECT_EN); 294 if (ret) 295 return ret; 296 297 /* 298 * Reset the CMN PLL block to ensure the updated configurations 299 * take effect. 300 */ 301 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 302 CMN_ANA_EN_SW_RSTN); 303 if (ret) 304 return ret; 305 306 usleep_range(1000, 1200); 307 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 308 CMN_ANA_EN_SW_RSTN); 309 if (ret) 310 return ret; 311 312 /* Stability check of CMN PLL output clocks. */ 313 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, 314 (val & CMN_PLL_CLKS_LOCKED), 315 100, 100 * USEC_PER_MSEC); 316 } 317 318 static const struct clk_ops clk_cmn_pll_ops = { 319 .recalc_rate = clk_cmn_pll_recalc_rate, 320 .determine_rate = clk_cmn_pll_determine_rate, 321 .set_rate = clk_cmn_pll_set_rate, 322 }; 323 324 static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) 325 { 326 struct clk_parent_data pdata = { .index = 0 }; 327 struct device *dev = &pdev->dev; 328 struct clk_init_data init = {}; 329 struct clk_cmn_pll *cmn_pll; 330 struct regmap *regmap; 331 void __iomem *base; 332 int ret; 333 334 base = devm_platform_ioremap_resource(pdev, 0); 335 if (IS_ERR(base)) 336 return ERR_CAST(base); 337 338 regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); 339 if (IS_ERR(regmap)) 340 return ERR_CAST(regmap); 341 342 cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); 343 if (!cmn_pll) 344 return ERR_PTR(-ENOMEM); 345 346 init.name = "cmn_pll"; 347 init.parent_data = &pdata; 348 init.num_parents = 1; 349 init.ops = &clk_cmn_pll_ops; 350 351 cmn_pll->hw.init = &init; 352 cmn_pll->regmap = regmap; 353 354 ret = devm_clk_hw_register(dev, &cmn_pll->hw); 355 if (ret) 356 return ERR_PTR(ret); 357 358 return &cmn_pll->hw; 359 } 360 361 static int ipq_cmn_pll_register_clks(struct platform_device *pdev) 362 { 363 const struct cmn_pll_fixed_output_clk *p, *fixed_clk; 364 struct clk_hw_onecell_data *hw_data; 365 struct device *dev = &pdev->dev; 366 struct clk_hw *cmn_pll_hw; 367 unsigned int num_clks; 368 struct clk_hw *hw; 369 int ret, i; 370 371 fixed_clk = device_get_match_data(dev); 372 if (!fixed_clk) 373 return -EINVAL; 374 375 num_clks = 0; 376 for (p = fixed_clk; p->name; p++) 377 num_clks++; 378 379 hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), 380 GFP_KERNEL); 381 if (!hw_data) 382 return -ENOMEM; 383 384 /* 385 * Register the CMN PLL clock, which is the parent clock of 386 * the fixed rate output clocks. 387 */ 388 cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); 389 if (IS_ERR(cmn_pll_hw)) 390 return PTR_ERR(cmn_pll_hw); 391 392 /* Register the fixed rate output clocks. */ 393 for (i = 0; i < num_clks; i++) { 394 hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, 395 cmn_pll_hw, 0, 396 fixed_clk[i].rate); 397 if (IS_ERR(hw)) { 398 ret = PTR_ERR(hw); 399 goto unregister_fixed_clk; 400 } 401 402 hw_data->hws[fixed_clk[i].id] = hw; 403 } 404 405 /* 406 * Provide the CMN PLL clock. The clock rate of CMN PLL 407 * is configured to 12 GHZ by DT property assigned-clock-rates-u64. 408 */ 409 hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; 410 hw_data->num = num_clks + 1; 411 412 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); 413 if (ret) 414 goto unregister_fixed_clk; 415 416 platform_set_drvdata(pdev, hw_data); 417 418 return 0; 419 420 unregister_fixed_clk: 421 while (i > 0) 422 clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); 423 424 return ret; 425 } 426 427 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) 428 { 429 struct device *dev = &pdev->dev; 430 int ret; 431 432 ret = devm_pm_runtime_enable(dev); 433 if (ret) 434 return ret; 435 436 ret = devm_pm_clk_create(dev); 437 if (ret) 438 return ret; 439 440 /* 441 * To access the CMN PLL registers, the GCC AHB & SYS clocks 442 * of CMN PLL block need to be enabled. 443 */ 444 ret = pm_clk_add(dev, "ahb"); 445 if (ret) 446 return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); 447 448 ret = pm_clk_add(dev, "sys"); 449 if (ret) 450 return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); 451 452 ret = pm_runtime_resume_and_get(dev); 453 if (ret) 454 return ret; 455 456 /* Register CMN PLL clock and fixed rate output clocks. */ 457 ret = ipq_cmn_pll_register_clks(pdev); 458 pm_runtime_put(dev); 459 if (ret) 460 return dev_err_probe(dev, ret, 461 "Failed to register CMN PLL clocks\n"); 462 463 return 0; 464 } 465 466 static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) 467 { 468 struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); 469 int i; 470 471 /* 472 * The clock with index CMN_PLL_CLK is unregistered by 473 * device management. 474 */ 475 for (i = 0; i < hw_data->num; i++) { 476 if (i != CMN_PLL_CLK) 477 clk_hw_unregister(hw_data->hws[i]); 478 } 479 } 480 481 static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { 482 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 483 }; 484 485 static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 486 { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, 487 { .compatible = "qcom,ipq5332-cmn-pll", .data = &ipq5332_output_clks }, 488 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, 489 { .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks }, 490 { .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks }, 491 { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 492 { } 493 }; 494 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); 495 496 static struct platform_driver ipq_cmn_pll_clk_driver = { 497 .probe = ipq_cmn_pll_clk_probe, 498 .remove = ipq_cmn_pll_clk_remove, 499 .driver = { 500 .name = "ipq_cmn_pll", 501 .of_match_table = ipq_cmn_pll_clk_ids, 502 .pm = &ipq_cmn_pll_pm_ops, 503 }, 504 }; 505 module_platform_driver(ipq_cmn_pll_clk_driver); 506 507 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); 508 MODULE_LICENSE("GPL"); 509