1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 /* 7 * CMN PLL block expects the reference clock from on-board Wi-Fi block, 8 * and supplies fixed rate clocks as output to the networking hardware 9 * blocks and to GCC. The networking related blocks include PPE (packet 10 * process engine), the externally connected PHY or switch devices, and 11 * the PCS. 12 * 13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock 14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), 15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks 16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS 17 * with 31.25 MHZ. 18 * 19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ, 20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output 21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574. 22 * 23 * +---------+ 24 * | GCC | 25 * +--+---+--+ 26 * AHB CLK| |SYS CLK 27 * V V 28 * +-------+---+------+ 29 * | +-------------> eth0-50mhz 30 * REF CLK | IPQ9574 | 31 * -------->+ +-------------> eth1-50mhz 32 * | CMN PLL block | 33 * | +-------------> eth2-50mhz 34 * | | 35 * +----+----+----+---+-------------> eth-25mhz 36 * | | | 37 * V V V 38 * GCC PCS NSS/PPE 39 */ 40 41 #include <linux/bitfield.h> 42 #include <linux/clk-provider.h> 43 #include <linux/delay.h> 44 #include <linux/err.h> 45 #include <linux/mod_devicetable.h> 46 #include <linux/module.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_clock.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/regmap.h> 51 52 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 53 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 54 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 55 56 #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 57 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) 58 59 #define CMN_PLL_LOCKED 0x64 60 #define CMN_PLL_CLKS_LOCKED BIT(8) 61 62 #define CMN_PLL_POWER_ON_AND_RESET 0x780 63 #define CMN_ANA_EN_SW_RSTN BIT(6) 64 65 #define CMN_PLL_REFCLK_CONFIG 0x784 66 #define CMN_PLL_REFCLK_EXTERNAL BIT(9) 67 #define CMN_PLL_REFCLK_DIV GENMASK(8, 4) 68 #define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) 69 70 #define CMN_PLL_CTRL 0x78c 71 #define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) 72 73 #define CMN_PLL_DIVIDER_CTRL 0x794 74 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) 75 76 /** 77 * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information 78 * @id: Clock specifier to be supplied 79 * @name: Clock name to be registered 80 * @rate: Clock rate 81 */ 82 struct cmn_pll_fixed_output_clk { 83 unsigned int id; 84 const char *name; 85 unsigned long rate; 86 }; 87 88 /** 89 * struct clk_cmn_pll - CMN PLL hardware specific data 90 * @regmap: hardware regmap. 91 * @hw: handle between common and hardware-specific interfaces 92 */ 93 struct clk_cmn_pll { 94 struct regmap *regmap; 95 struct clk_hw hw; 96 }; 97 98 #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ 99 .id = _id, \ 100 .name = _name, \ 101 .rate = _rate, \ 102 } 103 104 #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) 105 106 static const struct regmap_config ipq_cmn_pll_regmap_config = { 107 .reg_bits = 32, 108 .reg_stride = 4, 109 .val_bits = 32, 110 .max_register = 0x7fc, 111 }; 112 113 static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = { 114 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 115 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 116 CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), 117 { /* Sentinel */ } 118 }; 119 120 static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = { 121 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 122 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 123 CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 124 CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), 125 CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL), 126 CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 127 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 128 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 129 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 130 { /* Sentinel */ } 131 }; 132 133 static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { 134 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), 135 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), 136 CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), 137 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), 138 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), 139 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), 140 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), 141 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), 142 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), 143 { /* Sentinel */ } 144 }; 145 146 /* 147 * CMN PLL has the single parent clock, which supports the several 148 * possible parent clock rates, each parent clock rate is reflected 149 * by the specific reference index value in the hardware. 150 */ 151 static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) 152 { 153 int index = -EINVAL; 154 155 switch (parent_rate) { 156 case 25000000: 157 index = 3; 158 break; 159 case 31250000: 160 index = 4; 161 break; 162 case 40000000: 163 index = 6; 164 break; 165 case 48000000: 166 case 96000000: 167 /* 168 * Parent clock rate 48 MHZ and 96 MHZ take the same value 169 * of reference clock index. 96 MHZ needs the source clock 170 * divider to be programmed as 2. 171 */ 172 index = 7; 173 break; 174 case 50000000: 175 index = 8; 176 break; 177 default: 178 break; 179 } 180 181 return index; 182 } 183 184 static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, 185 unsigned long parent_rate) 186 { 187 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 188 u32 val, factor; 189 190 /* 191 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted 192 * by HW according to the parent clock rate. 193 */ 194 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); 195 factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); 196 197 return parent_rate * 2 * factor; 198 } 199 200 static int clk_cmn_pll_determine_rate(struct clk_hw *hw, 201 struct clk_rate_request *req) 202 { 203 int ret; 204 205 /* Validate the rate of the single parent clock. */ 206 ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); 207 208 return ret < 0 ? ret : 0; 209 } 210 211 /* 212 * This function is used to initialize the CMN PLL to enable the fixed 213 * rate output clocks. It is expected to be configured once. 214 */ 215 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, 216 unsigned long parent_rate) 217 { 218 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); 219 int ret, index; 220 u32 val; 221 222 /* 223 * Configure the reference input clock selection as per the given 224 * parent clock. The output clock rates are always of fixed value. 225 */ 226 index = ipq_cmn_pll_find_freq_index(parent_rate); 227 if (index < 0) 228 return index; 229 230 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 231 CMN_PLL_REFCLK_INDEX, 232 FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); 233 if (ret) 234 return ret; 235 236 /* 237 * Update the source clock rate selection and source clock 238 * divider as 2 when the parent clock rate is 96 MHZ. 239 */ 240 if (parent_rate == 96000000) { 241 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, 242 CMN_PLL_REFCLK_DIV, 243 FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); 244 if (ret) 245 return ret; 246 247 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, 248 CMN_PLL_REFCLK_SRC_DIV, 249 FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); 250 if (ret) 251 return ret; 252 } 253 254 /* Enable PLL locked detect. */ 255 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, 256 CMN_PLL_CTRL_LOCK_DETECT_EN); 257 if (ret) 258 return ret; 259 260 /* 261 * Reset the CMN PLL block to ensure the updated configurations 262 * take effect. 263 */ 264 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 265 CMN_ANA_EN_SW_RSTN); 266 if (ret) 267 return ret; 268 269 usleep_range(1000, 1200); 270 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, 271 CMN_ANA_EN_SW_RSTN); 272 if (ret) 273 return ret; 274 275 /* Stability check of CMN PLL output clocks. */ 276 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, 277 (val & CMN_PLL_CLKS_LOCKED), 278 100, 100 * USEC_PER_MSEC); 279 } 280 281 static const struct clk_ops clk_cmn_pll_ops = { 282 .recalc_rate = clk_cmn_pll_recalc_rate, 283 .determine_rate = clk_cmn_pll_determine_rate, 284 .set_rate = clk_cmn_pll_set_rate, 285 }; 286 287 static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) 288 { 289 struct clk_parent_data pdata = { .index = 0 }; 290 struct device *dev = &pdev->dev; 291 struct clk_init_data init = {}; 292 struct clk_cmn_pll *cmn_pll; 293 struct regmap *regmap; 294 void __iomem *base; 295 int ret; 296 297 base = devm_platform_ioremap_resource(pdev, 0); 298 if (IS_ERR(base)) 299 return ERR_CAST(base); 300 301 regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); 302 if (IS_ERR(regmap)) 303 return ERR_CAST(regmap); 304 305 cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); 306 if (!cmn_pll) 307 return ERR_PTR(-ENOMEM); 308 309 init.name = "cmn_pll"; 310 init.parent_data = &pdata; 311 init.num_parents = 1; 312 init.ops = &clk_cmn_pll_ops; 313 314 cmn_pll->hw.init = &init; 315 cmn_pll->regmap = regmap; 316 317 ret = devm_clk_hw_register(dev, &cmn_pll->hw); 318 if (ret) 319 return ERR_PTR(ret); 320 321 return &cmn_pll->hw; 322 } 323 324 static int ipq_cmn_pll_register_clks(struct platform_device *pdev) 325 { 326 const struct cmn_pll_fixed_output_clk *p, *fixed_clk; 327 struct clk_hw_onecell_data *hw_data; 328 struct device *dev = &pdev->dev; 329 struct clk_hw *cmn_pll_hw; 330 unsigned int num_clks; 331 struct clk_hw *hw; 332 int ret, i; 333 334 fixed_clk = device_get_match_data(dev); 335 if (!fixed_clk) 336 return -EINVAL; 337 338 num_clks = 0; 339 for (p = fixed_clk; p->name; p++) 340 num_clks++; 341 342 hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), 343 GFP_KERNEL); 344 if (!hw_data) 345 return -ENOMEM; 346 347 /* 348 * Register the CMN PLL clock, which is the parent clock of 349 * the fixed rate output clocks. 350 */ 351 cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); 352 if (IS_ERR(cmn_pll_hw)) 353 return PTR_ERR(cmn_pll_hw); 354 355 /* Register the fixed rate output clocks. */ 356 for (i = 0; i < num_clks; i++) { 357 hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, 358 cmn_pll_hw, 0, 359 fixed_clk[i].rate); 360 if (IS_ERR(hw)) { 361 ret = PTR_ERR(hw); 362 goto unregister_fixed_clk; 363 } 364 365 hw_data->hws[fixed_clk[i].id] = hw; 366 } 367 368 /* 369 * Provide the CMN PLL clock. The clock rate of CMN PLL 370 * is configured to 12 GHZ by DT property assigned-clock-rates-u64. 371 */ 372 hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; 373 hw_data->num = num_clks + 1; 374 375 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); 376 if (ret) 377 goto unregister_fixed_clk; 378 379 platform_set_drvdata(pdev, hw_data); 380 381 return 0; 382 383 unregister_fixed_clk: 384 while (i > 0) 385 clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); 386 387 return ret; 388 } 389 390 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) 391 { 392 struct device *dev = &pdev->dev; 393 int ret; 394 395 ret = devm_pm_runtime_enable(dev); 396 if (ret) 397 return ret; 398 399 ret = devm_pm_clk_create(dev); 400 if (ret) 401 return ret; 402 403 /* 404 * To access the CMN PLL registers, the GCC AHB & SYS clocks 405 * of CMN PLL block need to be enabled. 406 */ 407 ret = pm_clk_add(dev, "ahb"); 408 if (ret) 409 return dev_err_probe(dev, ret, "Failed to add AHB clock\n"); 410 411 ret = pm_clk_add(dev, "sys"); 412 if (ret) 413 return dev_err_probe(dev, ret, "Failed to add SYS clock\n"); 414 415 ret = pm_runtime_resume_and_get(dev); 416 if (ret) 417 return ret; 418 419 /* Register CMN PLL clock and fixed rate output clocks. */ 420 ret = ipq_cmn_pll_register_clks(pdev); 421 pm_runtime_put(dev); 422 if (ret) 423 return dev_err_probe(dev, ret, 424 "Failed to register CMN PLL clocks\n"); 425 426 return 0; 427 } 428 429 static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) 430 { 431 struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); 432 int i; 433 434 /* 435 * The clock with index CMN_PLL_CLK is unregistered by 436 * device management. 437 */ 438 for (i = 0; i < hw_data->num; i++) { 439 if (i != CMN_PLL_CLK) 440 clk_hw_unregister(hw_data->hws[i]); 441 } 442 } 443 444 static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { 445 SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 446 }; 447 448 static const struct of_device_id ipq_cmn_pll_clk_ids[] = { 449 { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks }, 450 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks }, 451 { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks }, 452 { } 453 }; 454 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); 455 456 static struct platform_driver ipq_cmn_pll_clk_driver = { 457 .probe = ipq_cmn_pll_clk_probe, 458 .remove = ipq_cmn_pll_clk_remove, 459 .driver = { 460 .name = "ipq_cmn_pll", 461 .of_match_table = ipq_cmn_pll_clk_ids, 462 .pm = &ipq_cmn_pll_pm_ops, 463 }, 464 }; 465 module_platform_driver(ipq_cmn_pll_clk_driver); 466 467 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); 468 MODULE_LICENSE("GPL"); 469