1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,sm8650-gpucc.h> 13 #include <dt-bindings/reset/qcom,sm8650-gpucc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "gdsc.h" 23 #include "reset.h" 24 25 enum { 26 DT_BI_TCXO, 27 DT_GPLL0_OUT_MAIN, 28 DT_GPLL0_OUT_MAIN_DIV, 29 }; 30 31 enum { 32 P_BI_TCXO, 33 P_GPLL0_OUT_MAIN, 34 P_GPLL0_OUT_MAIN_DIV, 35 P_GPU_CC_PLL0_OUT_MAIN, 36 P_GPU_CC_PLL1_OUT_MAIN, 37 }; 38 39 static const struct pll_vco lucid_ole_vco[] = { 40 { 249600000, 2100000000, 0 }, 41 }; 42 43 static const struct alpha_pll_config gpu_cc_pll0_config = { 44 .l = 0x20, 45 .alpha = 0x4aaa, 46 .config_ctl_val = 0x20485699, 47 .config_ctl_hi_val = 0x00182261, 48 .config_ctl_hi1_val = 0x82aa299c, 49 .test_ctl_val = 0x00000000, 50 .test_ctl_hi_val = 0x00000003, 51 .test_ctl_hi1_val = 0x00009000, 52 .test_ctl_hi2_val = 0x00000034, 53 .user_ctl_val = 0x00000000, 54 .user_ctl_hi_val = 0x00000005, 55 }; 56 57 static struct clk_alpha_pll gpu_cc_pll0 = { 58 .offset = 0x0, 59 .vco_table = lucid_ole_vco, 60 .num_vco = ARRAY_SIZE(lucid_ole_vco), 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 62 .clkr = { 63 .hw.init = &(struct clk_init_data){ 64 .name = "gpu_cc_pll0", 65 .parent_data = &(const struct clk_parent_data){ 66 .index = DT_BI_TCXO, 67 }, 68 .num_parents = 1, 69 .ops = &clk_alpha_pll_lucid_evo_ops, 70 }, 71 }, 72 }; 73 74 static const struct alpha_pll_config gpu_cc_pll1_config = { 75 .l = 0x1b, 76 .alpha = 0x1555, 77 .config_ctl_val = 0x20485699, 78 .config_ctl_hi_val = 0x00182261, 79 .config_ctl_hi1_val = 0x82aa299c, 80 .test_ctl_val = 0x00000000, 81 .test_ctl_hi_val = 0x00000003, 82 .test_ctl_hi1_val = 0x00009000, 83 .test_ctl_hi2_val = 0x00000034, 84 .user_ctl_val = 0x00000000, 85 .user_ctl_hi_val = 0x00000005, 86 }; 87 88 static struct clk_alpha_pll gpu_cc_pll1 = { 89 .offset = 0x1000, 90 .vco_table = lucid_ole_vco, 91 .num_vco = ARRAY_SIZE(lucid_ole_vco), 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 93 .clkr = { 94 .hw.init = &(struct clk_init_data){ 95 .name = "gpu_cc_pll1", 96 .parent_data = &(const struct clk_parent_data){ 97 .index = DT_BI_TCXO, 98 }, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_lucid_evo_ops, 101 }, 102 }, 103 }; 104 105 static const struct parent_map gpu_cc_parent_map_0[] = { 106 { P_BI_TCXO, 0 }, 107 { P_GPLL0_OUT_MAIN, 5 }, 108 { P_GPLL0_OUT_MAIN_DIV, 6 }, 109 }; 110 111 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 112 { .index = DT_BI_TCXO }, 113 { .index = DT_GPLL0_OUT_MAIN }, 114 { .index = DT_GPLL0_OUT_MAIN_DIV }, 115 }; 116 117 static const struct parent_map gpu_cc_parent_map_1[] = { 118 { P_BI_TCXO, 0 }, 119 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 120 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 121 { P_GPLL0_OUT_MAIN, 5 }, 122 { P_GPLL0_OUT_MAIN_DIV, 6 }, 123 }; 124 125 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 126 { .index = DT_BI_TCXO }, 127 { .hw = &gpu_cc_pll0.clkr.hw }, 128 { .hw = &gpu_cc_pll1.clkr.hw }, 129 { .index = DT_GPLL0_OUT_MAIN }, 130 { .index = DT_GPLL0_OUT_MAIN_DIV }, 131 }; 132 133 static const struct parent_map gpu_cc_parent_map_2[] = { 134 { P_BI_TCXO, 0 }, 135 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 136 { P_GPLL0_OUT_MAIN, 5 }, 137 { P_GPLL0_OUT_MAIN_DIV, 6 }, 138 }; 139 140 static const struct clk_parent_data gpu_cc_parent_data_2[] = { 141 { .index = DT_BI_TCXO }, 142 { .hw = &gpu_cc_pll1.clkr.hw }, 143 { .index = DT_GPLL0_OUT_MAIN }, 144 { .index = DT_GPLL0_OUT_MAIN_DIV }, 145 }; 146 147 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 148 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 149 { } 150 }; 151 152 static struct clk_rcg2 gpu_cc_ff_clk_src = { 153 .cmd_rcgr = 0x9474, 154 .mnd_width = 0, 155 .hid_width = 5, 156 .parent_map = gpu_cc_parent_map_0, 157 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 158 .hw_clk_ctrl = true, 159 .clkr.hw.init = &(struct clk_init_data){ 160 .name = "gpu_cc_ff_clk_src", 161 .parent_data = gpu_cc_parent_data_0, 162 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 163 .flags = CLK_SET_RATE_PARENT, 164 .ops = &clk_rcg2_shared_ops, 165 }, 166 }; 167 168 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 169 F(19200000, P_BI_TCXO, 1, 0, 0), 170 F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 171 F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 172 { } 173 }; 174 175 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 176 .cmd_rcgr = 0x9318, 177 .mnd_width = 0, 178 .hid_width = 5, 179 .parent_map = gpu_cc_parent_map_1, 180 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 181 .hw_clk_ctrl = true, 182 .clkr.hw.init = &(struct clk_init_data){ 183 .name = "gpu_cc_gmu_clk_src", 184 .parent_data = gpu_cc_parent_data_1, 185 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 186 .flags = CLK_SET_RATE_PARENT, 187 .ops = &clk_rcg2_shared_ops, 188 }, 189 }; 190 191 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 192 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 193 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 194 { } 195 }; 196 197 static struct clk_rcg2 gpu_cc_hub_clk_src = { 198 .cmd_rcgr = 0x93ec, 199 .mnd_width = 0, 200 .hid_width = 5, 201 .parent_map = gpu_cc_parent_map_2, 202 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 203 .hw_clk_ctrl = true, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "gpu_cc_hub_clk_src", 206 .parent_data = gpu_cc_parent_data_2, 207 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 208 .flags = CLK_SET_RATE_PARENT, 209 .ops = &clk_rcg2_shared_ops, 210 }, 211 }; 212 213 static struct clk_regmap_div gpu_cc_hub_div_clk_src = { 214 .reg = 0x942c, 215 .shift = 0, 216 .width = 4, 217 .clkr.hw.init = &(const struct clk_init_data) { 218 .name = "gpu_cc_hub_div_clk_src", 219 .parent_hws = (const struct clk_hw*[]){ 220 &gpu_cc_hub_clk_src.clkr.hw, 221 }, 222 .num_parents = 1, 223 .flags = CLK_SET_RATE_PARENT, 224 .ops = &clk_regmap_div_ro_ops, 225 }, 226 }; 227 228 static struct clk_branch gpu_cc_ahb_clk = { 229 .halt_reg = 0x911c, 230 .halt_check = BRANCH_HALT_DELAY, 231 .clkr = { 232 .enable_reg = 0x911c, 233 .enable_mask = BIT(0), 234 .hw.init = &(struct clk_init_data){ 235 .name = "gpu_cc_ahb_clk", 236 .parent_hws = (const struct clk_hw*[]){ 237 &gpu_cc_hub_div_clk_src.clkr.hw, 238 }, 239 .num_parents = 1, 240 .flags = CLK_SET_RATE_PARENT, 241 .ops = &clk_branch2_ops, 242 }, 243 }, 244 }; 245 246 static struct clk_branch gpu_cc_crc_ahb_clk = { 247 .halt_reg = 0x9120, 248 .halt_check = BRANCH_HALT_VOTED, 249 .clkr = { 250 .enable_reg = 0x9120, 251 .enable_mask = BIT(0), 252 .hw.init = &(struct clk_init_data){ 253 .name = "gpu_cc_crc_ahb_clk", 254 .parent_hws = (const struct clk_hw*[]){ 255 &gpu_cc_hub_clk_src.clkr.hw, 256 }, 257 .num_parents = 1, 258 .flags = CLK_SET_RATE_PARENT, 259 .ops = &clk_branch2_ops, 260 }, 261 }, 262 }; 263 264 static struct clk_branch gpu_cc_cx_accu_shift_clk = { 265 .halt_reg = 0x9160, 266 .halt_check = BRANCH_HALT_VOTED, 267 .clkr = { 268 .enable_reg = 0x9160, 269 .enable_mask = BIT(0), 270 .hw.init = &(const struct clk_init_data){ 271 .name = "gpu_cc_cx_accu_shift_clk", 272 .ops = &clk_branch2_ops, 273 }, 274 }, 275 }; 276 277 static struct clk_branch gpu_cc_cx_ff_clk = { 278 .halt_reg = 0x914c, 279 .halt_check = BRANCH_HALT, 280 .clkr = { 281 .enable_reg = 0x914c, 282 .enable_mask = BIT(0), 283 .hw.init = &(struct clk_init_data){ 284 .name = "gpu_cc_cx_ff_clk", 285 .parent_hws = (const struct clk_hw*[]){ 286 &gpu_cc_ff_clk_src.clkr.hw, 287 }, 288 .num_parents = 1, 289 .flags = CLK_SET_RATE_PARENT, 290 .ops = &clk_branch2_ops, 291 }, 292 }, 293 }; 294 295 static struct clk_branch gpu_cc_cx_gmu_clk = { 296 .halt_reg = 0x913c, 297 .halt_check = BRANCH_HALT_VOTED, 298 .clkr = { 299 .enable_reg = 0x913c, 300 .enable_mask = BIT(0), 301 .hw.init = &(struct clk_init_data){ 302 .name = "gpu_cc_cx_gmu_clk", 303 .parent_hws = (const struct clk_hw*[]){ 304 &gpu_cc_gmu_clk_src.clkr.hw, 305 }, 306 .num_parents = 1, 307 .flags = CLK_SET_RATE_PARENT, 308 .ops = &clk_branch2_aon_ops, 309 }, 310 }, 311 }; 312 313 static struct clk_branch gpu_cc_cxo_aon_clk = { 314 .halt_reg = 0x9004, 315 .halt_check = BRANCH_HALT_VOTED, 316 .clkr = { 317 .enable_reg = 0x9004, 318 .enable_mask = BIT(0), 319 .hw.init = &(struct clk_init_data){ 320 .name = "gpu_cc_cxo_aon_clk", 321 .ops = &clk_branch2_ops, 322 }, 323 }, 324 }; 325 326 static struct clk_branch gpu_cc_cxo_clk = { 327 .halt_reg = 0x9144, 328 .halt_check = BRANCH_HALT, 329 .clkr = { 330 .enable_reg = 0x9144, 331 .enable_mask = BIT(0), 332 .hw.init = &(struct clk_init_data){ 333 .name = "gpu_cc_cxo_clk", 334 .ops = &clk_branch2_ops, 335 }, 336 }, 337 }; 338 339 static struct clk_branch gpu_cc_demet_clk = { 340 .halt_reg = 0x900c, 341 .halt_check = BRANCH_HALT, 342 .clkr = { 343 .enable_reg = 0x900c, 344 .enable_mask = BIT(0), 345 .hw.init = &(struct clk_init_data){ 346 .name = "gpu_cc_demet_clk", 347 .ops = &clk_branch2_aon_ops, 348 }, 349 }, 350 }; 351 352 static struct clk_branch gpu_cc_freq_measure_clk = { 353 .halt_reg = 0x9008, 354 .halt_check = BRANCH_HALT, 355 .clkr = { 356 .enable_reg = 0x9008, 357 .enable_mask = BIT(0), 358 .hw.init = &(struct clk_init_data){ 359 .name = "gpu_cc_freq_measure_clk", 360 .ops = &clk_branch2_ops, 361 }, 362 }, 363 }; 364 365 static struct clk_branch gpu_cc_gx_gfx3d_clk = { 366 .halt_reg = 0x90a8, 367 .halt_check = BRANCH_HALT, 368 .clkr = { 369 .enable_reg = 0x90a8, 370 .enable_mask = BIT(0), 371 .hw.init = &(struct clk_init_data){ 372 .name = "gpu_cc_gx_gfx3d_clk", 373 .ops = &clk_branch2_ops, 374 }, 375 }, 376 }; 377 378 static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { 379 .halt_reg = 0x90c8, 380 .halt_check = BRANCH_HALT, 381 .clkr = { 382 .enable_reg = 0x90c8, 383 .enable_mask = BIT(0), 384 .hw.init = &(struct clk_init_data){ 385 .name = "gpu_cc_gx_gfx3d_rdvm_clk", 386 .ops = &clk_branch2_ops, 387 }, 388 }, 389 }; 390 391 static struct clk_branch gpu_cc_gx_gmu_clk = { 392 .halt_reg = 0x90bc, 393 .halt_check = BRANCH_HALT, 394 .clkr = { 395 .enable_reg = 0x90bc, 396 .enable_mask = BIT(0), 397 .hw.init = &(struct clk_init_data){ 398 .name = "gpu_cc_gx_gmu_clk", 399 .parent_hws = (const struct clk_hw*[]){ 400 &gpu_cc_gmu_clk_src.clkr.hw, 401 }, 402 .num_parents = 1, 403 .flags = CLK_SET_RATE_PARENT, 404 .ops = &clk_branch2_ops, 405 }, 406 }, 407 }; 408 409 static struct clk_branch gpu_cc_gx_vsense_clk = { 410 .halt_reg = 0x90b0, 411 .halt_check = BRANCH_HALT_VOTED, 412 .clkr = { 413 .enable_reg = 0x90b0, 414 .enable_mask = BIT(0), 415 .hw.init = &(struct clk_init_data){ 416 .name = "gpu_cc_gx_vsense_clk", 417 .ops = &clk_branch2_ops, 418 }, 419 }, 420 }; 421 422 static struct clk_branch gpu_cc_gx_accu_shift_clk = { 423 .halt_reg = 0x90d0, 424 .halt_check = BRANCH_HALT_VOTED, 425 .clkr = { 426 .enable_reg = 0x90d0, 427 .enable_mask = BIT(0), 428 .hw.init = &(const struct clk_init_data){ 429 .name = "gpu_cc_gx_accu_shift_clk", 430 .ops = &clk_branch2_ops, 431 }, 432 }, 433 }; 434 435 static struct clk_branch gpu_cc_gx_ff_clk = { 436 .halt_reg = 0x90c0, 437 .halt_check = BRANCH_HALT, 438 .clkr = { 439 .enable_reg = 0x90c0, 440 .enable_mask = BIT(0), 441 .hw.init = &(const struct clk_init_data){ 442 .name = "gpu_cc_gx_ff_clk", 443 .parent_hws = (const struct clk_hw*[]){ 444 &gpu_cc_ff_clk_src.clkr.hw, 445 }, 446 .num_parents = 1, 447 .flags = CLK_SET_RATE_PARENT, 448 .ops = &clk_branch2_ops, 449 }, 450 }, 451 }; 452 453 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 454 .halt_reg = 0x7000, 455 .halt_check = BRANCH_HALT_VOTED, 456 .clkr = { 457 .enable_reg = 0x7000, 458 .enable_mask = BIT(0), 459 .hw.init = &(struct clk_init_data){ 460 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 461 .ops = &clk_branch2_ops, 462 }, 463 }, 464 }; 465 466 static struct clk_branch gpu_cc_hub_aon_clk = { 467 .halt_reg = 0x93e8, 468 .halt_check = BRANCH_HALT_VOTED, 469 .clkr = { 470 .enable_reg = 0x93e8, 471 .enable_mask = BIT(0), 472 .hw.init = &(struct clk_init_data){ 473 .name = "gpu_cc_hub_aon_clk", 474 .parent_hws = (const struct clk_hw*[]){ 475 &gpu_cc_hub_clk_src.clkr.hw, 476 }, 477 .num_parents = 1, 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_branch2_aon_ops, 480 }, 481 }, 482 }; 483 484 static struct clk_branch gpu_cc_hub_cx_int_clk = { 485 .halt_reg = 0x9148, 486 .halt_check = BRANCH_HALT_VOTED, 487 .clkr = { 488 .enable_reg = 0x9148, 489 .enable_mask = BIT(0), 490 .hw.init = &(struct clk_init_data){ 491 .name = "gpu_cc_hub_cx_int_clk", 492 .parent_hws = (const struct clk_hw*[]){ 493 &gpu_cc_hub_clk_src.clkr.hw, 494 }, 495 .num_parents = 1, 496 .flags = CLK_SET_RATE_PARENT, 497 .ops = &clk_branch2_aon_ops, 498 }, 499 }, 500 }; 501 502 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 503 .halt_reg = 0x9150, 504 .halt_check = BRANCH_HALT_VOTED, 505 .clkr = { 506 .enable_reg = 0x9150, 507 .enable_mask = BIT(0), 508 .hw.init = &(struct clk_init_data){ 509 .name = "gpu_cc_memnoc_gfx_clk", 510 .ops = &clk_branch2_ops, 511 }, 512 }, 513 }; 514 515 static struct clk_branch gpu_cc_sleep_clk = { 516 .halt_reg = 0x9134, 517 .halt_check = BRANCH_HALT_VOTED, 518 .clkr = { 519 .enable_reg = 0x9134, 520 .enable_mask = BIT(0), 521 .hw.init = &(struct clk_init_data){ 522 .name = "gpu_cc_sleep_clk", 523 .ops = &clk_branch2_ops, 524 }, 525 }, 526 }; 527 528 static struct clk_branch gpu_cc_dpm_clk = { 529 .halt_reg = 0x9164, 530 .halt_check = BRANCH_HALT, 531 .clkr = { 532 .enable_reg = 0x9164, 533 .enable_mask = BIT(0), 534 .hw.init = &(const struct clk_init_data){ 535 .name = "gpu_cc_dpm_clk", 536 .ops = &clk_branch2_ops, 537 }, 538 }, 539 }; 540 541 static struct gdsc gpu_cx_gdsc = { 542 .gdscr = 0x9108, 543 .gds_hw_ctrl = 0x9168, 544 .clk_dis_wait_val = 8, 545 .pd = { 546 .name = "gpu_cx_gdsc", 547 }, 548 .pwrsts = PWRSTS_OFF_ON, 549 .flags = VOTABLE | RETAIN_FF_ENABLE, 550 }; 551 552 static struct gdsc gpu_gx_gdsc = { 553 .gdscr = 0x905c, 554 .clamp_io_ctrl = 0x9504, 555 .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, 556 GPUCC_GPU_CC_ACD_BCR, 557 GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, 558 .reset_count = 3, 559 .pd = { 560 .name = "gpu_gx_gdsc", 561 .power_on = gdsc_gx_do_nothing_enable, 562 }, 563 .pwrsts = PWRSTS_OFF_ON, 564 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, 565 }; 566 567 static struct clk_regmap *gpu_cc_sm8650_clocks[] = { 568 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 569 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 570 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, 571 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 572 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 573 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 574 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 575 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 576 [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, 577 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 578 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, 579 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 580 [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, 581 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, 582 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, 583 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, 584 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, 585 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, 586 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 587 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 588 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 589 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 590 [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, 591 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 592 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 593 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 594 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 595 }; 596 597 static const struct qcom_reset_map gpu_cc_sm8650_resets[] = { 598 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 599 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 600 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 601 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 602 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 603 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 604 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 605 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 606 [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, 607 }; 608 609 static struct gdsc *gpu_cc_sm8650_gdscs[] = { 610 [GPU_CX_GDSC] = &gpu_cx_gdsc, 611 [GPU_GX_GDSC] = &gpu_gx_gdsc, 612 }; 613 614 static const struct regmap_config gpu_cc_sm8650_regmap_config = { 615 .reg_bits = 32, 616 .reg_stride = 4, 617 .val_bits = 32, 618 .max_register = 0xa000, 619 .fast_io = true, 620 }; 621 622 static const struct qcom_cc_desc gpu_cc_sm8650_desc = { 623 .config = &gpu_cc_sm8650_regmap_config, 624 .clks = gpu_cc_sm8650_clocks, 625 .num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks), 626 .resets = gpu_cc_sm8650_resets, 627 .num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets), 628 .gdscs = gpu_cc_sm8650_gdscs, 629 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs), 630 }; 631 632 static const struct of_device_id gpu_cc_sm8650_match_table[] = { 633 { .compatible = "qcom,sm8650-gpucc" }, 634 { } 635 }; 636 MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table); 637 638 static int gpu_cc_sm8650_probe(struct platform_device *pdev) 639 { 640 struct regmap *regmap; 641 642 regmap = qcom_cc_map(pdev, &gpu_cc_sm8650_desc); 643 if (IS_ERR(regmap)) 644 return PTR_ERR(regmap); 645 646 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 647 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 648 649 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8650_desc, regmap); 650 } 651 652 static struct platform_driver gpu_cc_sm8650_driver = { 653 .probe = gpu_cc_sm8650_probe, 654 .driver = { 655 .name = "sm8650-gpucc", 656 .of_match_table = gpu_cc_sm8650_match_table, 657 }, 658 }; 659 module_platform_driver(gpu_cc_sm8650_driver); 660 661 MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver"); 662 MODULE_LICENSE("GPL"); 663