1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020, AngeloGioacchino Del Regno 5 * <angelogioacchino.delregno@somainline.org> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk-provider.h> 10 #include <linux/err.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include <dt-bindings/clock/qcom,gpucc-sdm660.h> 17 18 #include "clk-alpha-pll.h" 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 enum { 28 P_GPU_XO, 29 P_GPLL0_OUT_MAIN, 30 P_GPLL0_OUT_MAIN_DIV, 31 P_GPU_PLL0_PLL_OUT_MAIN, 32 P_GPU_PLL1_PLL_OUT_MAIN, 33 }; 34 35 static struct clk_branch gpucc_cxo_clk = { 36 .halt_reg = 0x1020, 37 .clkr = { 38 .enable_reg = 0x1020, 39 .enable_mask = BIT(0), 40 .hw.init = &(struct clk_init_data){ 41 .name = "gpucc_cxo_clk", 42 .parent_data = &(const struct clk_parent_data){ 43 .fw_name = "xo" 44 }, 45 .num_parents = 1, 46 .ops = &clk_branch2_ops, 47 .flags = CLK_IS_CRITICAL, 48 }, 49 }, 50 }; 51 52 static const struct pll_vco gpu_vco[] = { 53 { 1000000000, 2000000000, 0 }, 54 { 500000000, 1000000000, 2 }, 55 { 250000000, 500000000, 3 }, 56 }; 57 58 static struct clk_alpha_pll gpu_pll0_pll_out_main = { 59 .offset = 0x0, 60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 61 .vco_table = gpu_vco, 62 .num_vco = ARRAY_SIZE(gpu_vco), 63 .clkr.hw.init = &(struct clk_init_data){ 64 .name = "gpu_pll0_pll_out_main", 65 .parent_hws = (const struct clk_hw*[]){ 66 &gpucc_cxo_clk.clkr.hw, 67 }, 68 .num_parents = 1, 69 .ops = &clk_alpha_pll_ops, 70 }, 71 }; 72 73 static struct clk_alpha_pll gpu_pll1_pll_out_main = { 74 .offset = 0x40, 75 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 76 .vco_table = gpu_vco, 77 .num_vco = ARRAY_SIZE(gpu_vco), 78 .clkr.hw.init = &(struct clk_init_data){ 79 .name = "gpu_pll1_pll_out_main", 80 .parent_hws = (const struct clk_hw*[]){ 81 &gpucc_cxo_clk.clkr.hw, 82 }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_ops, 85 }, 86 }; 87 88 static const struct parent_map gpucc_parent_map_1[] = { 89 { P_GPU_XO, 0 }, 90 { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, 91 { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, 92 { P_GPLL0_OUT_MAIN, 5 }, 93 }; 94 95 static const struct clk_parent_data gpucc_parent_data_1[] = { 96 { .hw = &gpucc_cxo_clk.clkr.hw }, 97 { .hw = &gpu_pll0_pll_out_main.clkr.hw }, 98 { .hw = &gpu_pll1_pll_out_main.clkr.hw }, 99 { .fw_name = "gcc_gpu_gpll0_clk" }, 100 }; 101 102 static struct clk_rcg2_gfx3d gfx3d_clk_src = { 103 .div = 2, 104 .rcg = { 105 .cmd_rcgr = 0x1070, 106 .mnd_width = 0, 107 .hid_width = 5, 108 .parent_map = gpucc_parent_map_1, 109 .clkr.hw.init = &(struct clk_init_data){ 110 .name = "gfx3d_clk_src", 111 .parent_data = gpucc_parent_data_1, 112 .num_parents = ARRAY_SIZE(gpucc_parent_data_1), 113 .ops = &clk_gfx3d_ops, 114 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 115 }, 116 }, 117 .hws = (struct clk_hw*[]){ 118 &gpucc_cxo_clk.clkr.hw, 119 &gpu_pll0_pll_out_main.clkr.hw, 120 &gpu_pll1_pll_out_main.clkr.hw, 121 } 122 }; 123 124 static struct clk_branch gpucc_gfx3d_clk = { 125 .halt_reg = 0x1098, 126 .halt_check = BRANCH_HALT, 127 .hwcg_reg = 0x1098, 128 .hwcg_bit = 1, 129 .clkr = { 130 .enable_reg = 0x1098, 131 .enable_mask = BIT(0), 132 .hw.init = &(struct clk_init_data){ 133 .name = "gpucc_gfx3d_clk", 134 .parent_hws = (const struct clk_hw*[]){ 135 &gfx3d_clk_src.rcg.clkr.hw, 136 }, 137 .num_parents = 1, 138 .ops = &clk_branch2_ops, 139 .flags = CLK_SET_RATE_PARENT, 140 }, 141 }, 142 }; 143 144 static const struct parent_map gpucc_parent_map_0[] = { 145 { P_GPU_XO, 0 }, 146 { P_GPLL0_OUT_MAIN, 5 }, 147 { P_GPLL0_OUT_MAIN_DIV, 6 }, 148 }; 149 150 static const struct clk_parent_data gpucc_parent_data_0[] = { 151 { .hw = &gpucc_cxo_clk.clkr.hw }, 152 { .fw_name = "gcc_gpu_gpll0_clk" }, 153 { .fw_name = "gcc_gpu_gpll0_div_clk" }, 154 }; 155 156 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 157 F(19200000, P_GPU_XO, 1, 0, 0), 158 { } 159 }; 160 161 static struct clk_rcg2 rbbmtimer_clk_src = { 162 .cmd_rcgr = 0x10b0, 163 .mnd_width = 0, 164 .hid_width = 5, 165 .parent_map = gpucc_parent_map_0, 166 .freq_tbl = ftbl_rbbmtimer_clk_src, 167 .clkr.hw.init = &(struct clk_init_data){ 168 .name = "rbbmtimer_clk_src", 169 .parent_data = gpucc_parent_data_0, 170 .num_parents = ARRAY_SIZE(gpucc_parent_data_0), 171 .ops = &clk_rcg2_ops, 172 }, 173 }; 174 175 static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 176 F(19200000, P_GPU_XO, 1, 0, 0), 177 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), 178 { } 179 }; 180 181 static struct clk_rcg2 rbcpr_clk_src = { 182 .cmd_rcgr = 0x1030, 183 .mnd_width = 0, 184 .hid_width = 5, 185 .parent_map = gpucc_parent_map_0, 186 .freq_tbl = ftbl_rbcpr_clk_src, 187 .clkr.hw.init = &(struct clk_init_data){ 188 .name = "rbcpr_clk_src", 189 .parent_data = gpucc_parent_data_0, 190 .num_parents = ARRAY_SIZE(gpucc_parent_data_0), 191 .ops = &clk_rcg2_ops, 192 }, 193 }; 194 195 static struct clk_branch gpucc_rbbmtimer_clk = { 196 .halt_reg = 0x10d0, 197 .halt_check = BRANCH_HALT, 198 .clkr = { 199 .enable_reg = 0x10d0, 200 .enable_mask = BIT(0), 201 .hw.init = &(struct clk_init_data){ 202 .name = "gpucc_rbbmtimer_clk", 203 .parent_hws = (const struct clk_hw*[]){ 204 &rbbmtimer_clk_src.clkr.hw, 205 }, 206 .num_parents = 1, 207 .flags = CLK_SET_RATE_PARENT, 208 .ops = &clk_branch2_ops, 209 }, 210 }, 211 }; 212 213 static struct clk_branch gpucc_rbcpr_clk = { 214 .halt_reg = 0x1054, 215 .halt_check = BRANCH_HALT, 216 .clkr = { 217 .enable_reg = 0x1054, 218 .enable_mask = BIT(0), 219 .hw.init = &(struct clk_init_data){ 220 .name = "gpucc_rbcpr_clk", 221 .parent_hws = (const struct clk_hw*[]){ 222 &rbcpr_clk_src.clkr.hw, 223 }, 224 .num_parents = 1, 225 .flags = CLK_SET_RATE_PARENT, 226 .ops = &clk_branch2_ops, 227 }, 228 }, 229 }; 230 231 static struct gdsc gpu_cx_gdsc = { 232 .gdscr = 0x1004, 233 .gds_hw_ctrl = 0x1008, 234 .pd = { 235 .name = "gpu_cx", 236 }, 237 .pwrsts = PWRSTS_OFF_ON, 238 .flags = VOTABLE, 239 }; 240 241 static struct gdsc gpu_gx_gdsc = { 242 .gdscr = 0x1094, 243 .clamp_io_ctrl = 0x130, 244 .resets = (unsigned int []){ GPU_GX_BCR }, 245 .reset_count = 1, 246 .cxcs = (unsigned int []){ 0x1098 }, 247 .cxc_count = 1, 248 .pd = { 249 .name = "gpu_gx", 250 }, 251 .parent = &gpu_cx_gdsc.pd, 252 .pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET, 253 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH, 254 }; 255 256 static struct gdsc *gpucc_sdm660_gdscs[] = { 257 [GPU_CX_GDSC] = &gpu_cx_gdsc, 258 [GPU_GX_GDSC] = &gpu_gx_gdsc, 259 }; 260 261 static const struct qcom_reset_map gpucc_sdm660_resets[] = { 262 [GPU_CX_BCR] = { 0x1000 }, 263 [RBCPR_BCR] = { 0x1050 }, 264 [GPU_GX_BCR] = { 0x1090 }, 265 [SPDM_BCR] = { 0x10E0 }, 266 }; 267 268 static struct clk_regmap *gpucc_sdm660_clocks[] = { 269 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, 270 [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, 271 [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, 272 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr, 273 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 274 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 275 [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, 276 [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, 277 [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, 278 }; 279 280 static const struct regmap_config gpucc_660_regmap_config = { 281 .reg_bits = 32, 282 .reg_stride = 4, 283 .val_bits = 32, 284 .max_register = 0x9034, 285 .fast_io = true, 286 }; 287 288 static const struct qcom_cc_desc gpucc_sdm660_desc = { 289 .config = &gpucc_660_regmap_config, 290 .clks = gpucc_sdm660_clocks, 291 .num_clks = ARRAY_SIZE(gpucc_sdm660_clocks), 292 .resets = gpucc_sdm660_resets, 293 .num_resets = ARRAY_SIZE(gpucc_sdm660_resets), 294 .gdscs = gpucc_sdm660_gdscs, 295 .num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs), 296 }; 297 298 static const struct of_device_id gpucc_sdm660_match_table[] = { 299 { .compatible = "qcom,gpucc-sdm660" }, 300 { .compatible = "qcom,gpucc-sdm630" }, 301 { } 302 }; 303 MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table); 304 305 static int gpucc_sdm660_probe(struct platform_device *pdev) 306 { 307 struct regmap *regmap; 308 struct alpha_pll_config gpu_pll_config = { 309 .config_ctl_val = 0x4001055b, 310 .alpha = 0xaaaaab00, 311 .alpha_en_mask = BIT(24), 312 .vco_val = 0x2 << 20, 313 .vco_mask = 0x3 << 20, 314 .main_output_mask = 0x1, 315 }; 316 317 regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc); 318 if (IS_ERR(regmap)) 319 return PTR_ERR(regmap); 320 321 /* 800MHz configuration for GPU PLL0 */ 322 gpu_pll_config.l = 0x29; 323 gpu_pll_config.alpha_hi = 0xaa; 324 clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config); 325 326 /* 740MHz configuration for GPU PLL1 */ 327 gpu_pll_config.l = 0x26; 328 gpu_pll_config.alpha_hi = 0x8a; 329 clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config); 330 331 return qcom_cc_really_probe(&pdev->dev, &gpucc_sdm660_desc, regmap); 332 } 333 334 static struct platform_driver gpucc_sdm660_driver = { 335 .probe = gpucc_sdm660_probe, 336 .driver = { 337 .name = "gpucc-sdm660", 338 .of_match_table = gpucc_sdm660_match_table, 339 }, 340 }; 341 module_platform_driver(gpucc_sdm660_driver); 342 343 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver"); 344 MODULE_LICENSE("GPL v2"); 345