1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,qcs8300-gpucc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "common.h" 22 #include "reset.h" 23 #include "gdsc.h" 24 25 /* Need to match the order of clocks in DT binding */ 26 enum { 27 DT_BI_TCXO, 28 DT_GCC_GPU_GPLL0_CLK_SRC, 29 DT_GCC_GPU_GPLL0_DIV_CLK_SRC, 30 }; 31 32 enum { 33 P_BI_TCXO, 34 P_GPLL0_OUT_MAIN, 35 P_GPLL0_OUT_MAIN_DIV, 36 P_GPU_CC_PLL0_OUT_MAIN, 37 P_GPU_CC_PLL1_OUT_MAIN, 38 }; 39 40 static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; 41 42 static const struct pll_vco lucid_evo_vco[] = { 43 { 249600000, 2020000000, 0 }, 44 }; 45 46 /* 810MHz configuration */ 47 static struct alpha_pll_config gpu_cc_pll0_config = { 48 .l = 0x2a, 49 .alpha = 0x3000, 50 .config_ctl_val = 0x20485699, 51 .config_ctl_hi_val = 0x00182261, 52 .config_ctl_hi1_val = 0x32aa299c, 53 .user_ctl_val = 0x00000001, 54 .user_ctl_hi_val = 0x00400805, 55 }; 56 57 static struct clk_alpha_pll gpu_cc_pll0 = { 58 .offset = 0x0, 59 .vco_table = lucid_evo_vco, 60 .num_vco = ARRAY_SIZE(lucid_evo_vco), 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 62 .clkr = { 63 .hw.init = &(const struct clk_init_data){ 64 .name = "gpu_cc_pll0", 65 .parent_data = &parent_data_tcxo, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_lucid_evo_ops, 68 }, 69 }, 70 }; 71 72 /* 1000MHz configuration */ 73 static struct alpha_pll_config gpu_cc_pll1_config = { 74 .l = 0x34, 75 .alpha = 0x1555, 76 .config_ctl_val = 0x20485699, 77 .config_ctl_hi_val = 0x00182261, 78 .config_ctl_hi1_val = 0x32aa299c, 79 .user_ctl_val = 0x00000001, 80 .user_ctl_hi_val = 0x00400805, 81 }; 82 83 static struct clk_alpha_pll gpu_cc_pll1 = { 84 .offset = 0x1000, 85 .vco_table = lucid_evo_vco, 86 .num_vco = ARRAY_SIZE(lucid_evo_vco), 87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], 88 .clkr = { 89 .hw.init = &(const struct clk_init_data){ 90 .name = "gpu_cc_pll1", 91 .parent_data = &parent_data_tcxo, 92 .num_parents = 1, 93 .ops = &clk_alpha_pll_lucid_evo_ops, 94 }, 95 }, 96 }; 97 98 static const struct parent_map gpu_cc_parent_map_0[] = { 99 { P_BI_TCXO, 0 }, 100 { P_GPLL0_OUT_MAIN, 5 }, 101 { P_GPLL0_OUT_MAIN_DIV, 6 }, 102 }; 103 104 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 105 { .index = DT_BI_TCXO }, 106 { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, 107 { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, 108 }; 109 110 static const struct parent_map gpu_cc_parent_map_1[] = { 111 { P_BI_TCXO, 0 }, 112 { P_GPU_CC_PLL0_OUT_MAIN, 1 }, 113 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 114 { P_GPLL0_OUT_MAIN, 5 }, 115 { P_GPLL0_OUT_MAIN_DIV, 6 }, 116 }; 117 118 static const struct clk_parent_data gpu_cc_parent_data_1[] = { 119 { .index = DT_BI_TCXO }, 120 { .hw = &gpu_cc_pll0.clkr.hw }, 121 { .hw = &gpu_cc_pll1.clkr.hw }, 122 { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, 123 { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, 124 }; 125 126 static const struct parent_map gpu_cc_parent_map_2[] = { 127 { P_BI_TCXO, 0 }, 128 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 129 { P_GPLL0_OUT_MAIN, 5 }, 130 { P_GPLL0_OUT_MAIN_DIV, 6 }, 131 }; 132 133 static const struct clk_parent_data gpu_cc_parent_data_2[] = { 134 { .index = DT_BI_TCXO }, 135 { .hw = &gpu_cc_pll1.clkr.hw }, 136 { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, 137 { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, 138 }; 139 140 static const struct parent_map gpu_cc_parent_map_3[] = { 141 { P_BI_TCXO, 0 }, 142 }; 143 144 static const struct clk_parent_data gpu_cc_parent_data_3[] = { 145 { .index = DT_BI_TCXO }, 146 }; 147 148 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { 149 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 150 { } 151 }; 152 153 static struct clk_rcg2 gpu_cc_ff_clk_src = { 154 .cmd_rcgr = 0x9474, 155 .mnd_width = 0, 156 .hid_width = 5, 157 .parent_map = gpu_cc_parent_map_0, 158 .freq_tbl = ftbl_gpu_cc_ff_clk_src, 159 .clkr.hw.init = &(const struct clk_init_data){ 160 .name = "gpu_cc_ff_clk_src", 161 .parent_data = gpu_cc_parent_data_0, 162 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 163 .ops = &clk_rcg2_shared_ops, 164 }, 165 }; 166 167 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 168 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), 169 { } 170 }; 171 172 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 173 .cmd_rcgr = 0x9318, 174 .mnd_width = 0, 175 .hid_width = 5, 176 .parent_map = gpu_cc_parent_map_1, 177 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 178 .clkr.hw.init = &(const struct clk_init_data){ 179 .name = "gpu_cc_gmu_clk_src", 180 .parent_data = gpu_cc_parent_data_1, 181 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), 182 .flags = CLK_SET_RATE_PARENT, 183 .ops = &clk_rcg2_shared_ops, 184 }, 185 }; 186 187 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { 188 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 189 { } 190 }; 191 192 static struct clk_rcg2 gpu_cc_hub_clk_src = { 193 .cmd_rcgr = 0x93ec, 194 .mnd_width = 0, 195 .hid_width = 5, 196 .parent_map = gpu_cc_parent_map_2, 197 .freq_tbl = ftbl_gpu_cc_hub_clk_src, 198 .clkr.hw.init = &(const struct clk_init_data){ 199 .name = "gpu_cc_hub_clk_src", 200 .parent_data = gpu_cc_parent_data_2, 201 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), 202 .ops = &clk_rcg2_shared_ops, 203 }, 204 }; 205 206 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { 207 F(19200000, P_BI_TCXO, 1, 0, 0), 208 { } 209 }; 210 211 static struct clk_rcg2 gpu_cc_xo_clk_src = { 212 .cmd_rcgr = 0x9010, 213 .mnd_width = 0, 214 .hid_width = 5, 215 .parent_map = gpu_cc_parent_map_3, 216 .freq_tbl = ftbl_gpu_cc_xo_clk_src, 217 .clkr.hw.init = &(const struct clk_init_data){ 218 .name = "gpu_cc_xo_clk_src", 219 .parent_data = gpu_cc_parent_data_3, 220 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), 221 .ops = &clk_rcg2_ops, 222 }, 223 }; 224 225 static struct clk_regmap_div gpu_cc_demet_div_clk_src = { 226 .reg = 0x9054, 227 .shift = 0, 228 .width = 4, 229 .clkr.hw.init = &(const struct clk_init_data) { 230 .name = "gpu_cc_demet_div_clk_src", 231 .parent_hws = (const struct clk_hw*[]){ 232 &gpu_cc_xo_clk_src.clkr.hw, 233 }, 234 .num_parents = 1, 235 .flags = CLK_SET_RATE_PARENT, 236 .ops = &clk_regmap_div_ro_ops, 237 }, 238 }; 239 240 static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { 241 .reg = 0x9430, 242 .shift = 0, 243 .width = 4, 244 .clkr.hw.init = &(const struct clk_init_data) { 245 .name = "gpu_cc_hub_ahb_div_clk_src", 246 .parent_hws = (const struct clk_hw*[]){ 247 &gpu_cc_hub_clk_src.clkr.hw, 248 }, 249 .num_parents = 1, 250 .flags = CLK_SET_RATE_PARENT, 251 .ops = &clk_regmap_div_ro_ops, 252 }, 253 }; 254 255 static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { 256 .reg = 0x942c, 257 .shift = 0, 258 .width = 4, 259 .clkr.hw.init = &(const struct clk_init_data) { 260 .name = "gpu_cc_hub_cx_int_div_clk_src", 261 .parent_hws = (const struct clk_hw*[]){ 262 &gpu_cc_hub_clk_src.clkr.hw, 263 }, 264 .num_parents = 1, 265 .flags = CLK_SET_RATE_PARENT, 266 .ops = &clk_regmap_div_ro_ops, 267 }, 268 }; 269 270 static struct clk_branch gpu_cc_ahb_clk = { 271 .halt_reg = 0x911c, 272 .halt_check = BRANCH_HALT_DELAY, 273 .clkr = { 274 .enable_reg = 0x911c, 275 .enable_mask = BIT(0), 276 .hw.init = &(const struct clk_init_data){ 277 .name = "gpu_cc_ahb_clk", 278 .parent_hws = (const struct clk_hw*[]){ 279 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 280 }, 281 .num_parents = 1, 282 .flags = CLK_SET_RATE_PARENT, 283 .ops = &clk_branch2_ops, 284 }, 285 }, 286 }; 287 288 static struct clk_branch gpu_cc_cb_clk = { 289 .halt_reg = 0x93a4, 290 .halt_check = BRANCH_HALT, 291 .clkr = { 292 .enable_reg = 0x93a4, 293 .enable_mask = BIT(0), 294 .hw.init = &(const struct clk_init_data){ 295 .name = "gpu_cc_cb_clk", 296 .ops = &clk_branch2_aon_ops, 297 }, 298 }, 299 }; 300 301 static struct clk_branch gpu_cc_crc_ahb_clk = { 302 .halt_reg = 0x9120, 303 .halt_check = BRANCH_HALT_VOTED, 304 .clkr = { 305 .enable_reg = 0x9120, 306 .enable_mask = BIT(0), 307 .hw.init = &(const struct clk_init_data){ 308 .name = "gpu_cc_crc_ahb_clk", 309 .parent_hws = (const struct clk_hw*[]){ 310 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 311 }, 312 .num_parents = 1, 313 .flags = CLK_SET_RATE_PARENT, 314 .ops = &clk_branch2_ops, 315 }, 316 }, 317 }; 318 319 static struct clk_branch gpu_cc_cx_accu_shift_clk = { 320 .halt_reg = 0x95e8, 321 .halt_check = BRANCH_HALT, 322 .clkr = { 323 .enable_reg = 0x95e8, 324 .enable_mask = BIT(0), 325 .hw.init = &(const struct clk_init_data){ 326 .name = "gpu_cc_cx_accu_shift_clk", 327 .parent_hws = (const struct clk_hw*[]){ 328 &gpu_cc_xo_clk_src.clkr.hw, 329 }, 330 .num_parents = 1, 331 .flags = CLK_SET_RATE_PARENT, 332 .ops = &clk_branch2_ops, 333 }, 334 }, 335 }; 336 337 static struct clk_branch gpu_cc_cx_ff_clk = { 338 .halt_reg = 0x914c, 339 .halt_check = BRANCH_HALT, 340 .clkr = { 341 .enable_reg = 0x914c, 342 .enable_mask = BIT(0), 343 .hw.init = &(const struct clk_init_data){ 344 .name = "gpu_cc_cx_ff_clk", 345 .parent_hws = (const struct clk_hw*[]){ 346 &gpu_cc_ff_clk_src.clkr.hw, 347 }, 348 .num_parents = 1, 349 .flags = CLK_SET_RATE_PARENT, 350 .ops = &clk_branch2_ops, 351 }, 352 }, 353 }; 354 355 static struct clk_branch gpu_cc_cx_gmu_clk = { 356 .halt_reg = 0x913c, 357 .halt_check = BRANCH_HALT, 358 .clkr = { 359 .enable_reg = 0x913c, 360 .enable_mask = BIT(0), 361 .hw.init = &(const struct clk_init_data){ 362 .name = "gpu_cc_cx_gmu_clk", 363 .parent_hws = (const struct clk_hw*[]){ 364 &gpu_cc_gmu_clk_src.clkr.hw, 365 }, 366 .num_parents = 1, 367 .flags = CLK_SET_RATE_PARENT, 368 .ops = &clk_branch2_aon_ops, 369 }, 370 }, 371 }; 372 373 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 374 .halt_reg = 0x9130, 375 .halt_check = BRANCH_HALT_VOTED, 376 .clkr = { 377 .enable_reg = 0x9130, 378 .enable_mask = BIT(0), 379 .hw.init = &(const struct clk_init_data){ 380 .name = "gpu_cc_cx_snoc_dvm_clk", 381 .ops = &clk_branch2_ops, 382 }, 383 }, 384 }; 385 386 static struct clk_branch gpu_cc_cxo_aon_clk = { 387 .halt_reg = 0x9004, 388 .halt_check = BRANCH_HALT_VOTED, 389 .clkr = { 390 .enable_reg = 0x9004, 391 .enable_mask = BIT(0), 392 .hw.init = &(const struct clk_init_data){ 393 .name = "gpu_cc_cxo_aon_clk", 394 .parent_hws = (const struct clk_hw*[]){ 395 &gpu_cc_xo_clk_src.clkr.hw, 396 }, 397 .num_parents = 1, 398 .flags = CLK_SET_RATE_PARENT, 399 .ops = &clk_branch2_ops, 400 }, 401 }, 402 }; 403 404 static struct clk_branch gpu_cc_cxo_clk = { 405 .halt_reg = 0x9144, 406 .halt_check = BRANCH_HALT, 407 .clkr = { 408 .enable_reg = 0x9144, 409 .enable_mask = BIT(0), 410 .hw.init = &(const struct clk_init_data){ 411 .name = "gpu_cc_cxo_clk", 412 .parent_hws = (const struct clk_hw*[]){ 413 &gpu_cc_xo_clk_src.clkr.hw, 414 }, 415 .num_parents = 1, 416 .flags = CLK_SET_RATE_PARENT, 417 .ops = &clk_branch2_ops, 418 }, 419 }, 420 }; 421 422 static struct clk_branch gpu_cc_demet_clk = { 423 .halt_reg = 0x900c, 424 .halt_check = BRANCH_HALT, 425 .clkr = { 426 .enable_reg = 0x900c, 427 .enable_mask = BIT(0), 428 .hw.init = &(const struct clk_init_data){ 429 .name = "gpu_cc_demet_clk", 430 .parent_hws = (const struct clk_hw*[]){ 431 &gpu_cc_demet_div_clk_src.clkr.hw, 432 }, 433 .num_parents = 1, 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_branch2_aon_ops, 436 }, 437 }, 438 }; 439 440 static struct clk_branch gpu_cc_gx_accu_shift_clk = { 441 .halt_reg = 0x95e4, 442 .halt_check = BRANCH_HALT, 443 .clkr = { 444 .enable_reg = 0x95e4, 445 .enable_mask = BIT(0), 446 .hw.init = &(const struct clk_init_data){ 447 .name = "gpu_cc_gx_accu_shift_clk", 448 .parent_hws = (const struct clk_hw*[]){ 449 &gpu_cc_xo_clk_src.clkr.hw, 450 }, 451 .num_parents = 1, 452 .flags = CLK_SET_RATE_PARENT, 453 .ops = &clk_branch2_ops, 454 }, 455 }, 456 }; 457 458 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { 459 .halt_reg = 0x7000, 460 .halt_check = BRANCH_HALT_VOTED, 461 .clkr = { 462 .enable_reg = 0x7000, 463 .enable_mask = BIT(0), 464 .hw.init = &(const struct clk_init_data){ 465 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 466 .ops = &clk_branch2_ops, 467 }, 468 }, 469 }; 470 471 static struct clk_branch gpu_cc_hub_aon_clk = { 472 .halt_reg = 0x93e8, 473 .halt_check = BRANCH_HALT, 474 .clkr = { 475 .enable_reg = 0x93e8, 476 .enable_mask = BIT(0), 477 .hw.init = &(const struct clk_init_data){ 478 .name = "gpu_cc_hub_aon_clk", 479 .parent_hws = (const struct clk_hw*[]){ 480 &gpu_cc_hub_clk_src.clkr.hw, 481 }, 482 .num_parents = 1, 483 .flags = CLK_SET_RATE_PARENT, 484 .ops = &clk_branch2_aon_ops, 485 }, 486 }, 487 }; 488 489 static struct clk_branch gpu_cc_hub_cx_int_clk = { 490 .halt_reg = 0x9148, 491 .halt_check = BRANCH_HALT, 492 .clkr = { 493 .enable_reg = 0x9148, 494 .enable_mask = BIT(0), 495 .hw.init = &(const struct clk_init_data){ 496 .name = "gpu_cc_hub_cx_int_clk", 497 .parent_hws = (const struct clk_hw*[]){ 498 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 499 }, 500 .num_parents = 1, 501 .flags = CLK_SET_RATE_PARENT, 502 .ops = &clk_branch2_aon_ops, 503 }, 504 }, 505 }; 506 507 static struct clk_branch gpu_cc_memnoc_gfx_clk = { 508 .halt_reg = 0x9150, 509 .halt_check = BRANCH_HALT, 510 .clkr = { 511 .enable_reg = 0x9150, 512 .enable_mask = BIT(0), 513 .hw.init = &(const struct clk_init_data){ 514 .name = "gpu_cc_memnoc_gfx_clk", 515 .ops = &clk_branch2_ops, 516 }, 517 }, 518 }; 519 520 static struct clk_branch gpu_cc_sleep_clk = { 521 .halt_reg = 0x9134, 522 .halt_check = BRANCH_HALT_VOTED, 523 .clkr = { 524 .enable_reg = 0x9134, 525 .enable_mask = BIT(0), 526 .hw.init = &(const struct clk_init_data){ 527 .name = "gpu_cc_sleep_clk", 528 .ops = &clk_branch2_ops, 529 }, 530 }, 531 }; 532 533 static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { 534 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, 535 [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, 536 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 537 [GPU_CC_CX_ACCU_SHIFT_CLK] = NULL, 538 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, 539 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 540 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 541 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 542 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 543 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, 544 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, 545 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, 546 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 547 [GPU_CC_GX_ACCU_SHIFT_CLK] = NULL, 548 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, 549 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, 550 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, 551 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, 552 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, 553 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, 554 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, 555 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, 556 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 557 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, 558 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, 559 }; 560 561 static struct gdsc cx_gdsc = { 562 .gdscr = 0x9108, 563 .en_rest_wait_val = 0x2, 564 .en_few_wait_val = 0x2, 565 .clk_dis_wait_val = 0xf, 566 .gds_hw_ctrl = 0x953c, 567 .pd = { 568 .name = "cx_gdsc", 569 }, 570 .pwrsts = PWRSTS_OFF_ON, 571 .flags = VOTABLE | RETAIN_FF_ENABLE, 572 }; 573 574 static struct gdsc gx_gdsc = { 575 .gdscr = 0x905c, 576 .en_rest_wait_val = 0x2, 577 .en_few_wait_val = 0x2, 578 .clk_dis_wait_val = 0xf, 579 .pd = { 580 .name = "gx_gdsc", 581 .power_on = gdsc_gx_do_nothing_enable, 582 }, 583 .pwrsts = PWRSTS_OFF_ON, 584 .flags = AON_RESET | RETAIN_FF_ENABLE, 585 }; 586 587 static struct gdsc *gpu_cc_sa8775p_gdscs[] = { 588 [GPU_CC_CX_GDSC] = &cx_gdsc, 589 [GPU_CC_GX_GDSC] = &gx_gdsc, 590 }; 591 592 static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = { 593 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, 594 [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 }, 595 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, 596 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, 597 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, 598 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, 599 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, 600 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, 601 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, 602 }; 603 604 static const struct regmap_config gpu_cc_sa8775p_regmap_config = { 605 .reg_bits = 32, 606 .reg_stride = 4, 607 .val_bits = 32, 608 .max_register = 0x9988, 609 .fast_io = true, 610 }; 611 612 static const struct qcom_cc_desc gpu_cc_sa8775p_desc = { 613 .config = &gpu_cc_sa8775p_regmap_config, 614 .clks = gpu_cc_sa8775p_clocks, 615 .num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks), 616 .resets = gpu_cc_sa8775p_resets, 617 .num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets), 618 .gdscs = gpu_cc_sa8775p_gdscs, 619 .num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs), 620 }; 621 622 static const struct of_device_id gpu_cc_sa8775p_match_table[] = { 623 { .compatible = "qcom,qcs8300-gpucc" }, 624 { .compatible = "qcom,sa8775p-gpucc" }, 625 { } 626 }; 627 MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table); 628 629 static int gpu_cc_sa8775p_probe(struct platform_device *pdev) 630 { 631 struct regmap *regmap; 632 633 regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc); 634 if (IS_ERR(regmap)) 635 return PTR_ERR(regmap); 636 637 if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { 638 gpu_cc_pll0_config.l = 0x31; 639 gpu_cc_pll0_config.alpha = 0xe555; 640 641 gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr; 642 gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr; 643 } 644 645 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 646 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 647 648 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sa8775p_desc, regmap); 649 } 650 651 static struct platform_driver gpu_cc_sa8775p_driver = { 652 .probe = gpu_cc_sa8775p_probe, 653 .driver = { 654 .name = "gpu_cc-sa8775p", 655 .of_match_table = gpu_cc_sa8775p_match_table, 656 }, 657 }; 658 659 module_platform_driver(gpu_cc_sa8775p_driver); 660 661 MODULE_DESCRIPTION("SA8775P GPUCC driver"); 662 MODULE_LICENSE("GPL"); 663