1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019, Jeffrey Hugo 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/clk-provider.h> 12 #include <linux/regmap.h> 13 14 #include <dt-bindings/clock/qcom,gpucc-msm8998.h> 15 16 #include "common.h" 17 #include "clk-regmap.h" 18 #include "clk-regmap-divider.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-rcg.h" 21 #include "clk-branch.h" 22 #include "reset.h" 23 #include "gdsc.h" 24 25 enum { 26 P_XO, 27 P_GPLL0, 28 P_GPUPLL0_OUT_EVEN, 29 }; 30 31 /* Instead of going directly to the block, XO is routed through this branch */ 32 static struct clk_branch gpucc_cxo_clk = { 33 .halt_reg = 0x1020, 34 .clkr = { 35 .enable_reg = 0x1020, 36 .enable_mask = BIT(0), 37 .hw.init = &(struct clk_init_data){ 38 .name = "gpucc_cxo_clk", 39 .parent_data = &(const struct clk_parent_data){ 40 .fw_name = "xo" 41 }, 42 .num_parents = 1, 43 .ops = &clk_branch2_ops, 44 .flags = CLK_IS_CRITICAL, 45 }, 46 }, 47 }; 48 49 static const struct pll_vco fabia_vco[] = { 50 { 249600000, 2000000000, 0 }, 51 { 125000000, 1000000000, 1 }, 52 }; 53 54 static const struct clk_div_table post_div_table_fabia_even[] = { 55 { 0x0, 1 }, 56 { 0x1, 2 }, 57 { 0x3, 4 }, 58 { 0x7, 8 }, 59 { } 60 }; 61 62 static struct clk_alpha_pll gpupll0 = { 63 .offset = 0x0, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 65 .vco_table = fabia_vco, 66 .num_vco = ARRAY_SIZE(fabia_vco), 67 .clkr.hw.init = &(struct clk_init_data){ 68 .name = "gpupll0", 69 .parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_fabia_ops, 72 }, 73 }; 74 75 static struct clk_alpha_pll_postdiv gpupll0_out_even = { 76 .offset = 0x0, 77 .post_div_shift = 8, 78 .post_div_table = post_div_table_fabia_even, 79 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 82 .clkr.hw.init = &(struct clk_init_data){ 83 .name = "gpupll0_out_even", 84 .parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw }, 85 .num_parents = 1, 86 .flags = CLK_SET_RATE_PARENT, 87 .ops = &clk_alpha_pll_postdiv_fabia_ops, 88 }, 89 }; 90 91 static const struct parent_map gpu_xo_gpll0_map[] = { 92 { P_XO, 0 }, 93 { P_GPLL0, 5 }, 94 }; 95 96 static const struct clk_parent_data gpu_xo_gpll0[] = { 97 { .hw = &gpucc_cxo_clk.clkr.hw }, 98 { .fw_name = "gpll0", .name = "gcc_gpu_gpll0_clk" }, 99 }; 100 101 static const struct parent_map gpu_xo_gpupll0_map[] = { 102 { P_XO, 0 }, 103 { P_GPUPLL0_OUT_EVEN, 1 }, 104 }; 105 106 static const struct clk_hw *gpu_xo_gpupll0[] = { 107 &gpucc_cxo_clk.clkr.hw, 108 &gpupll0_out_even.clkr.hw, 109 }; 110 111 static const struct freq_tbl ftbl_rbcpr_clk_src[] = { 112 F(19200000, P_XO, 1, 0, 0), 113 F(50000000, P_GPLL0, 12, 0, 0), 114 { } 115 }; 116 117 static struct clk_rcg2 rbcpr_clk_src = { 118 .cmd_rcgr = 0x1030, 119 .hid_width = 5, 120 .parent_map = gpu_xo_gpll0_map, 121 .freq_tbl = ftbl_rbcpr_clk_src, 122 .clkr.hw.init = &(struct clk_init_data){ 123 .name = "rbcpr_clk_src", 124 .parent_data = gpu_xo_gpll0, 125 .num_parents = ARRAY_SIZE(gpu_xo_gpll0), 126 .ops = &clk_rcg2_ops, 127 }, 128 }; 129 130 static const struct freq_tbl ftbl_gfx3d_clk_src[] = { 131 { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }, 132 { } 133 }; 134 135 static struct clk_rcg2 gfx3d_clk_src = { 136 .cmd_rcgr = 0x1070, 137 .hid_width = 5, 138 .parent_map = gpu_xo_gpupll0_map, 139 .freq_tbl = ftbl_gfx3d_clk_src, 140 .clkr.hw.init = &(struct clk_init_data){ 141 .name = "gfx3d_clk_src", 142 .parent_hws = gpu_xo_gpupll0, 143 .num_parents = ARRAY_SIZE(gpu_xo_gpupll0), 144 .ops = &clk_rcg2_ops, 145 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 146 }, 147 }; 148 149 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { 150 F(19200000, P_XO, 1, 0, 0), 151 { } 152 }; 153 154 static struct clk_rcg2 rbbmtimer_clk_src = { 155 .cmd_rcgr = 0x10b0, 156 .hid_width = 5, 157 .parent_map = gpu_xo_gpll0_map, 158 .freq_tbl = ftbl_rbbmtimer_clk_src, 159 .clkr.hw.init = &(struct clk_init_data){ 160 .name = "rbbmtimer_clk_src", 161 .parent_data = gpu_xo_gpll0, 162 .num_parents = ARRAY_SIZE(gpu_xo_gpll0), 163 .ops = &clk_rcg2_ops, 164 }, 165 }; 166 167 static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = { 168 F(19200000, P_XO, 1, 0, 0), 169 F(40000000, P_GPLL0, 15, 0, 0), 170 F(200000000, P_GPLL0, 3, 0, 0), 171 F(300000000, P_GPLL0, 2, 0, 0), 172 { } 173 }; 174 175 static struct clk_rcg2 gfx3d_isense_clk_src = { 176 .cmd_rcgr = 0x1100, 177 .hid_width = 5, 178 .parent_map = gpu_xo_gpll0_map, 179 .freq_tbl = ftbl_gfx3d_isense_clk_src, 180 .clkr.hw.init = &(struct clk_init_data){ 181 .name = "gfx3d_isense_clk_src", 182 .parent_data = gpu_xo_gpll0, 183 .num_parents = ARRAY_SIZE(gpu_xo_gpll0), 184 .ops = &clk_rcg2_ops, 185 }, 186 }; 187 188 static struct clk_branch rbcpr_clk = { 189 .halt_reg = 0x1054, 190 .clkr = { 191 .enable_reg = 0x1054, 192 .enable_mask = BIT(0), 193 .hw.init = &(struct clk_init_data){ 194 .name = "rbcpr_clk", 195 .parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw }, 196 .num_parents = 1, 197 .ops = &clk_branch2_ops, 198 .flags = CLK_SET_RATE_PARENT, 199 }, 200 }, 201 }; 202 203 static struct clk_branch gfx3d_clk = { 204 .halt_reg = 0x1098, 205 .clkr = { 206 .enable_reg = 0x1098, 207 .enable_mask = BIT(0), 208 .hw.init = &(struct clk_init_data){ 209 .name = "gfx3d_clk", 210 .parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw }, 211 .num_parents = 1, 212 .ops = &clk_branch2_ops, 213 .flags = CLK_SET_RATE_PARENT, 214 }, 215 }, 216 }; 217 218 static struct clk_branch rbbmtimer_clk = { 219 .halt_reg = 0x10d0, 220 .clkr = { 221 .enable_reg = 0x10d0, 222 .enable_mask = BIT(0), 223 .hw.init = &(struct clk_init_data){ 224 .name = "rbbmtimer_clk", 225 .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw }, 226 .num_parents = 1, 227 .ops = &clk_branch2_ops, 228 .flags = CLK_SET_RATE_PARENT, 229 }, 230 }, 231 }; 232 233 static struct clk_branch gfx3d_isense_clk = { 234 .halt_reg = 0x1124, 235 .clkr = { 236 .enable_reg = 0x1124, 237 .enable_mask = BIT(0), 238 .hw.init = &(struct clk_init_data){ 239 .name = "gfx3d_isense_clk", 240 .parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw }, 241 .num_parents = 1, 242 .ops = &clk_branch2_ops, 243 }, 244 }, 245 }; 246 247 static struct gdsc gpu_cx_gdsc = { 248 .gdscr = 0x1004, 249 .gds_hw_ctrl = 0x1008, 250 .pd = { 251 .name = "gpu_cx", 252 }, 253 .pwrsts = PWRSTS_OFF_ON, 254 .flags = VOTABLE, 255 }; 256 257 static struct gdsc gpu_gx_gdsc = { 258 .gdscr = 0x1094, 259 .clamp_io_ctrl = 0x130, 260 .resets = (unsigned int []){ GPU_GX_BCR }, 261 .reset_count = 1, 262 .cxcs = (unsigned int []){ 0x1098 }, 263 .cxc_count = 1, 264 .pd = { 265 .name = "gpu_gx", 266 }, 267 .parent = &gpu_cx_gdsc.pd, 268 .pwrsts = PWRSTS_OFF_ON | PWRSTS_RET, 269 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH, 270 }; 271 272 static struct clk_regmap *gpucc_msm8998_clocks[] = { 273 [GPUPLL0] = &gpupll0.clkr, 274 [GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr, 275 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, 276 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 277 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, 278 [GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr, 279 [RBCPR_CLK] = &rbcpr_clk.clkr, 280 [GFX3D_CLK] = &gfx3d_clk.clkr, 281 [RBBMTIMER_CLK] = &rbbmtimer_clk.clkr, 282 [GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr, 283 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, 284 }; 285 286 static struct gdsc *gpucc_msm8998_gdscs[] = { 287 [GPU_CX_GDSC] = &gpu_cx_gdsc, 288 [GPU_GX_GDSC] = &gpu_gx_gdsc, 289 }; 290 291 static const struct qcom_reset_map gpucc_msm8998_resets[] = { 292 [GPU_CX_BCR] = { 0x1000 }, 293 [RBCPR_BCR] = { 0x1050 }, 294 [GPU_GX_BCR] = { 0x1090 }, 295 [GPU_ISENSE_BCR] = { 0x1120 }, 296 }; 297 298 static const struct regmap_config gpucc_msm8998_regmap_config = { 299 .reg_bits = 32, 300 .reg_stride = 4, 301 .val_bits = 32, 302 .max_register = 0x9000, 303 .fast_io = true, 304 }; 305 306 static const struct qcom_cc_desc gpucc_msm8998_desc = { 307 .config = &gpucc_msm8998_regmap_config, 308 .clks = gpucc_msm8998_clocks, 309 .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks), 310 .resets = gpucc_msm8998_resets, 311 .num_resets = ARRAY_SIZE(gpucc_msm8998_resets), 312 .gdscs = gpucc_msm8998_gdscs, 313 .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs), 314 }; 315 316 static const struct of_device_id gpucc_msm8998_match_table[] = { 317 { .compatible = "qcom,msm8998-gpucc" }, 318 { } 319 }; 320 MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table); 321 322 static int gpucc_msm8998_probe(struct platform_device *pdev) 323 { 324 struct regmap *regmap; 325 326 regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc); 327 if (IS_ERR(regmap)) 328 return PTR_ERR(regmap); 329 330 /* force periph logic on to avoid perf counter corruption */ 331 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13)); 332 /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */ 333 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); 334 335 return qcom_cc_really_probe(&pdev->dev, &gpucc_msm8998_desc, regmap); 336 } 337 338 static struct platform_driver gpucc_msm8998_driver = { 339 .probe = gpucc_msm8998_probe, 340 .driver = { 341 .name = "gpucc-msm8998", 342 .of_match_table = gpucc_msm8998_match_table, 343 }, 344 }; 345 module_platform_driver(gpucc_msm8998_driver); 346 347 MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver"); 348 MODULE_LICENSE("GPL v2"); 349