1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_GDSC_H__ 7 #define __QCOM_GDSC_H__ 8 9 #include <linux/err.h> 10 #include <linux/pm_domain.h> 11 12 struct icc_path; 13 struct regmap; 14 struct regulator; 15 struct reset_controller_dev; 16 17 /** 18 * struct gdsc - Globally Distributed Switch Controller 19 * @pd: generic power domain 20 * @regmap: regmap for MMIO accesses 21 * @gdscr: gsdc control register 22 * @collapse_ctrl: APCS collapse-vote register 23 * @collapse_mask: APCS collapse-vote mask 24 * @gds_hw_ctrl: gds_hw_ctrl register 25 * @cxcs: offsets of branch registers to toggle mem/periph bits in 26 * @cxc_count: number of @cxcs 27 * @pwrsts: Possible powerdomain power states 28 * @en_rest_wait_val: transition delay value for receiving enr ack signal 29 * @en_few_wait_val: transition delay value for receiving enf ack signal 30 * @clk_dis_wait_val: transition delay value for halting clock 31 * @resets: ids of resets associated with this gdsc 32 * @reset_count: number of @resets 33 * @rcdev: reset controller 34 */ 35 struct gdsc { 36 struct generic_pm_domain pd; 37 struct generic_pm_domain *parent; 38 struct regmap *regmap; 39 unsigned int gdscr; 40 unsigned int collapse_ctrl; 41 unsigned int collapse_mask; 42 unsigned int gds_hw_ctrl; 43 unsigned int clamp_io_ctrl; 44 unsigned int *cxcs; 45 unsigned int cxc_count; 46 unsigned int en_rest_wait_val; 47 unsigned int en_few_wait_val; 48 unsigned int clk_dis_wait_val; 49 const u8 pwrsts; 50 /* Powerdomain allowable state bitfields */ 51 #define PWRSTS_OFF BIT(0) 52 /* 53 * There is no SW control to transition a GDSC into 54 * PWRSTS_RET. This happens in HW when the parent 55 * domain goes down to a low power state 56 */ 57 #define PWRSTS_RET BIT(1) 58 #define PWRSTS_ON BIT(2) 59 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 60 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 61 const u16 flags; 62 #define VOTABLE BIT(0) 63 #define CLAMP_IO BIT(1) 64 #define HW_CTRL BIT(2) 65 #define SW_RESET BIT(3) 66 #define AON_RESET BIT(4) 67 #define POLL_CFG_GDSCR BIT(5) 68 #define ALWAYS_ON BIT(6) 69 #define RETAIN_FF_ENABLE BIT(7) 70 #define NO_RET_PERIPH BIT(8) 71 #define HW_CTRL_TRIGGER BIT(9) 72 struct reset_controller_dev *rcdev; 73 unsigned int *resets; 74 unsigned int reset_count; 75 76 const char *supply; 77 struct regulator *rsupply; 78 79 bool needs_icc; 80 unsigned int icc_path_index; 81 struct icc_path *icc_path; 82 }; 83 84 struct gdsc_desc { 85 struct device *dev; 86 struct gdsc **scs; 87 size_t num; 88 struct dev_pm_domain_list *pd_list; 89 }; 90 91 #ifdef CONFIG_QCOM_GDSC 92 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, 93 struct regmap *); 94 void gdsc_unregister(struct gdsc_desc *desc); 95 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); 96 #else 97 static inline int gdsc_register(struct gdsc_desc *desc, 98 struct reset_controller_dev *rcdev, 99 struct regmap *r) 100 { 101 return -ENOSYS; 102 } 103 104 static inline void gdsc_unregister(struct gdsc_desc *desc) {}; 105 #endif /* CONFIG_QCOM_GDSC */ 106 #endif /* __QCOM_GDSC_H__ */ 107